ARM: PL08x: fix spelling errors
Correct mis-spellings in comments and printk strings. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
This commit is contained in:
Russell King - ARM Linux
Dan Williams
Родитель
e8a7e48bb2
Коммит
e8b5e11df3
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@ -19,7 +19,7 @@
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* this program; if not, write to the Free Software Foundation, Inc., 59
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* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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* The full GNU General Public License is iin this distribution in the
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* The full GNU General Public License is in this distribution in the
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* file called COPYING.
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*
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* Documentation: ARM DDI 0196G == PL080
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@ -82,7 +82,7 @@
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/**
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* struct vendor_data - vendor-specific config parameters
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* for PL08x derivates
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* for PL08x derivatives
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* @name: the name of this specific variant
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* @channels: the number of channels available in this variant
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* @dualmaster: whether this version supports dual AHB masters
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@ -96,10 +96,8 @@ struct vendor_data {
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/*
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* PL08X private data structures
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* An LLI struct - see pl08x TRM
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* Note that next uses bit[0] as a bus bit,
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* start & end do not - their bus bit info
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* is in cctl
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* An LLI struct - see PL08x TRM. Note that next uses bit[0] as a bus bit,
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* start & end do not - their bus bit info is in cctl.
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*/
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struct lli {
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dma_addr_t src;
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@ -152,7 +150,7 @@ struct pl08x_driver_data {
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/* Size (bytes) of each LLI buffer allocated for one transfer */
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# define PL08X_LLI_TSFR_SIZE 0x2000
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/* Maximimum times we call dma_pool_alloc on this pool without freeing */
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/* Maximum times we call dma_pool_alloc on this pool without freeing */
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#define PL08X_MAX_ALLOCS 0x40
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#define MAX_NUM_TSFR_LLIS (PL08X_LLI_TSFR_SIZE/sizeof(struct lli))
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#define PL08X_ALIGN 8
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@ -177,7 +175,7 @@ static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch)
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/*
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* Set the initial DMA register values i.e. those for the first LLI
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* The next lli pointer and the configuration interrupt bit have
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* The next LLI pointer and the configuration interrupt bit have
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* been set when the LLIs were constructed
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*/
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static void pl08x_set_cregs(struct pl08x_driver_data *pl08x,
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@ -366,8 +364,7 @@ static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
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while (clli) {
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bytes += get_bytes_in_cctl(llis_va[i].cctl);
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/*
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* A clli of 0x00000000 will terminate the
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* LLI list
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* A LLI pointer of 0 terminates the LLI list
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*/
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clli = llis_va[i].next;
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i++;
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@ -469,7 +466,7 @@ static inline u32 pl08x_cctl_bits(u32 cctl, u8 srcwidth, u8 dstwidth,
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{
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u32 retbits = cctl;
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/* Remove all src, dst and transfersize bits */
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/* Remove all src, dst and transfer size bits */
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retbits &= ~PL080_CONTROL_DWIDTH_MASK;
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retbits &= ~PL080_CONTROL_SWIDTH_MASK;
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retbits &= ~PL080_CONTROL_TRANSFER_SIZE_MASK;
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@ -701,7 +698,7 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
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* Choose bus to align to
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* - prefers destination bus if both available
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* - if fixed address on one bus chooses other
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* - modifies cctl to choose an apropriate master
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* - modifies cctl to choose an appropriate master
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*/
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pl08x_choose_master_bus(&txd->srcbus, &txd->dstbus,
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&mbus, &sbus, cctl);
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@ -775,7 +772,7 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
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target_len = max_bytes_per_lli;
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/*
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* Set bus lengths for incrementing busses
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* Set bus lengths for incrementing buses
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* to number of bytes which fill to next memory
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* boundary
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*/
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@ -826,7 +823,7 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
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/*
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* So now we know how many bytes to transfer
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* to get to the nearest boundary
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* The next lli will past the boundary
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* The next LLI will past the boundary
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* - however we may be working to a boundary
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* on the slave bus
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* We need to ensure the master stays aligned
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@ -884,7 +881,7 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
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&& (remainder); j++) {
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cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
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dev_vdbg(&pl08x->adev->dev,
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"%s align with boundardy, single byte (remain %08x)\n",
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"%s align with boundary, single byte (remain %08x)\n",
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__func__, remainder);
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num_llis =
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pl08x_fill_lli_for_desc(pl08x,
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@ -907,7 +904,7 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
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while (remainder) {
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cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
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dev_vdbg(&pl08x->adev->dev,
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"%s align with boundardy, single odd byte (remain %d)\n",
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"%s align with boundary, single odd byte (remain %d)\n",
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__func__, remainder);
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num_llis = pl08x_fill_lli_for_desc(pl08x, txd, num_llis,
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1, cctl, &remainder);
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@ -1367,8 +1364,8 @@ static int pl08x_prep_channel_resources(struct pl08x_dma_chan *plchan,
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* available to handle it whereas slave transfers may
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* have been denied due to platform channel muxing restrictions
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* and since there is no guarantee that this will ever be
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* resolved, and since the signal must be aquired AFTER
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* aquiring the physical channel, we will let them be NACK:ed
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* resolved, and since the signal must be acquired AFTER
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* acquiring the physical channel, we will let them be NACK:ed
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* with -EBUSY here. The drivers can alway retry the prep()
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* call if they are eager on doing this using DMA.
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*/
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@ -1620,7 +1617,7 @@ static void pl08x_ensure_on(struct pl08x_driver_data *pl08x)
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val = readl(pl08x->base + PL080_CONFIG);
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val &= ~(PL080_CONFIG_M2_BE | PL080_CONFIG_M1_BE | PL080_CONFIG_ENABLE);
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/* We implictly clear bit 1 and that means little-endian mode */
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/* We implicitly clear bit 1 and that means little-endian mode */
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val |= PL080_CONFIG_ENABLE;
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writel(val, pl08x->base + PL080_CONFIG);
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}
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@ -2160,7 +2157,7 @@ static int __init pl08x_init(void)
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retval = amba_driver_register(&pl08x_amba_driver);
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if (retval)
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printk(KERN_WARNING DRIVER_NAME
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"failed to register as an amba device (%d)\n",
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"failed to register as an AMBA device (%d)\n",
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retval);
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return retval;
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}
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