ARM: i.MX27 clk: Introduce DT include for clock provider
Use clock defines in order to make devicetrees more human readable. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
This commit is contained in:
Alexander Shiyan
Shawn Guo
Родитель
3543fc54bc
Коммит
e8e3faa039
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@ -7,117 +7,22 @@ Required properties:
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- #clock-cells: Should be <1>
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell. The following is a full list of i.MX27
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clocks and IDs.
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Clock ID
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-----------------------
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dummy 0
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ckih 1
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ckil 2
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mpll 3
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spll 4
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mpll_main2 5
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ahb 6
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ipg 7
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nfc_div 8
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per1_div 9
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per2_div 10
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per3_div 11
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per4_div 12
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vpu_sel 13
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vpu_div 14
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usb_div 15
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cpu_sel 16
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clko_sel 17
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cpu_div 18
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clko_div 19
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ssi1_sel 20
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ssi2_sel 21
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ssi1_div 22
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ssi2_div 23
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clko_en 24
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ssi2_ipg_gate 25
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ssi1_ipg_gate 26
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slcdc_ipg_gate 27
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sdhc3_ipg_gate 28
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sdhc2_ipg_gate 29
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sdhc1_ipg_gate 30
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scc_ipg_gate 31
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sahara_ipg_gate 32
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rtc_ipg_gate 33
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pwm_ipg_gate 34
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owire_ipg_gate 35
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lcdc_ipg_gate 36
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kpp_ipg_gate 37
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iim_ipg_gate 38
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i2c2_ipg_gate 39
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i2c1_ipg_gate 40
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gpt6_ipg_gate 41
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gpt5_ipg_gate 42
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gpt4_ipg_gate 43
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gpt3_ipg_gate 44
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gpt2_ipg_gate 45
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gpt1_ipg_gate 46
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gpio_ipg_gate 47
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fec_ipg_gate 48
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emma_ipg_gate 49
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dma_ipg_gate 50
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cspi3_ipg_gate 51
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cspi2_ipg_gate 52
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cspi1_ipg_gate 53
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nfc_baud_gate 54
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ssi2_baud_gate 55
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ssi1_baud_gate 56
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vpu_baud_gate 57
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per4_gate 58
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per3_gate 59
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per2_gate 60
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per1_gate 61
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usb_ahb_gate 62
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slcdc_ahb_gate 63
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sahara_ahb_gate 64
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lcdc_ahb_gate 65
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vpu_ahb_gate 66
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fec_ahb_gate 67
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emma_ahb_gate 68
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emi_ahb_gate 69
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dma_ahb_gate 70
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csi_ahb_gate 71
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brom_ahb_gate 72
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ata_ahb_gate 73
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wdog_ipg_gate 74
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usb_ipg_gate 75
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uart6_ipg_gate 76
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uart5_ipg_gate 77
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uart4_ipg_gate 78
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uart3_ipg_gate 79
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uart2_ipg_gate 80
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uart1_ipg_gate 81
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ckih_div1p5 82
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fpm 83
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mpll_osc_sel 84
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mpll_sel 85
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spll_gate 86
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mshc_div 87
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rtic_ipg_gate 88
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mshc_ipg_gate 89
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rtic_ahb_gate 90
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mshc_baud_gate 91
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ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx27-clock.h
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for the full list of i.MX27 clock IDs.
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Examples:
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clks: ccm@10027000{
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compatible = "fsl,imx27-ccm";
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reg = <0x10027000 0x1000>;
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#clock-cells = <1>;
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};
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clks: ccm@10027000{
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compatible = "fsl,imx27-ccm";
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reg = <0x10027000 0x1000>;
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#clock-cells = <1>;
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};
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uart1: serial@1000a000 {
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compatible = "fsl,imx27-uart", "fsl,imx21-uart";
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reg = <0x1000a000 0x1000>;
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interrupts = <20>;
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clocks = <&clks 81>, <&clks 61>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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uart1: serial@1000a000 {
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compatible = "fsl,imx27-uart", "fsl,imx21-uart";
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reg = <0x1000a000 0x1000>;
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interrupts = <20>;
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clocks = <&clks IMX27_CLK_UART1_IPG_GATE>,
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<&clks IMX27_CLK_PER1_GATE>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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@ -4,6 +4,7 @@
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#include <linux/err.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <dt-bindings/clock/imx27-clock.h>
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#include "clk.h"
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#include "common.h"
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@ -63,147 +64,123 @@ static const char *clko_sel_clks[] = {
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static const char *ssi_sel_clks[] = { "spll_gate", "mpll", };
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enum mx27_clks {
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dummy, ckih, ckil, mpll, spll, mpll_main2, ahb, ipg, nfc_div, per1_div,
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per2_div, per3_div, per4_div, vpu_sel, vpu_div, usb_div, cpu_sel,
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clko_sel, cpu_div, clko_div, ssi1_sel, ssi2_sel, ssi1_div, ssi2_div,
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clko_en, ssi2_ipg_gate, ssi1_ipg_gate, slcdc_ipg_gate, sdhc3_ipg_gate,
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sdhc2_ipg_gate, sdhc1_ipg_gate, scc_ipg_gate, sahara_ipg_gate,
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rtc_ipg_gate, pwm_ipg_gate, owire_ipg_gate, lcdc_ipg_gate,
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kpp_ipg_gate, iim_ipg_gate, i2c2_ipg_gate, i2c1_ipg_gate,
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gpt6_ipg_gate, gpt5_ipg_gate, gpt4_ipg_gate, gpt3_ipg_gate,
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gpt2_ipg_gate, gpt1_ipg_gate, gpio_ipg_gate, fec_ipg_gate,
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emma_ipg_gate, dma_ipg_gate, cspi3_ipg_gate, cspi2_ipg_gate,
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cspi1_ipg_gate, nfc_baud_gate, ssi2_baud_gate, ssi1_baud_gate,
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vpu_baud_gate, per4_gate, per3_gate, per2_gate, per1_gate,
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usb_ahb_gate, slcdc_ahb_gate, sahara_ahb_gate, lcdc_ahb_gate,
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vpu_ahb_gate, fec_ahb_gate, emma_ahb_gate, emi_ahb_gate, dma_ahb_gate,
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csi_ahb_gate, brom_ahb_gate, ata_ahb_gate, wdog_ipg_gate, usb_ipg_gate,
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uart6_ipg_gate, uart5_ipg_gate, uart4_ipg_gate, uart3_ipg_gate,
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uart2_ipg_gate, uart1_ipg_gate, ckih_div1p5, fpm, mpll_osc_sel,
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mpll_sel, spll_gate, mshc_div, rtic_ipg_gate, mshc_ipg_gate,
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rtic_ahb_gate, mshc_baud_gate, clk_max
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};
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static struct clk *clk[clk_max];
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static struct clk *clk[IMX27_CLK_MAX];
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static struct clk_onecell_data clk_data;
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static void __init _mx27_clocks_init(unsigned long fref)
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{
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BUG_ON(!ccm);
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clk[dummy] = imx_clk_fixed("dummy", 0);
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clk[ckih] = imx_clk_fixed("ckih", fref);
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clk[ckil] = imx_clk_fixed("ckil", 32768);
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clk[fpm] = imx_clk_fixed_factor("fpm", "ckil", 1024, 1);
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clk[ckih_div1p5] = imx_clk_fixed_factor("ckih_div1p5", "ckih", 2, 3);
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clk[mpll_osc_sel] = imx_clk_mux("mpll_osc_sel", CCM_CSCR, 4, 1,
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mpll_osc_sel_clks,
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ARRAY_SIZE(mpll_osc_sel_clks));
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clk[mpll_sel] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks,
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ARRAY_SIZE(mpll_sel_clks));
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clk[mpll] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0);
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clk[spll] = imx_clk_pllv1("spll", "ckih", CCM_SPCTL0);
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clk[spll_gate] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1);
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clk[mpll_main2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3);
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clk[IMX27_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
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clk[IMX27_CLK_CKIH] = imx_clk_fixed("ckih", fref);
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clk[IMX27_CLK_CKIL] = imx_clk_fixed("ckil", 32768);
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clk[IMX27_CLK_FPM] = imx_clk_fixed_factor("fpm", "ckil", 1024, 1);
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clk[IMX27_CLK_CKIH_DIV1P5] = imx_clk_fixed_factor("ckih_div1p5", "ckih", 2, 3);
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clk[IMX27_CLK_MPLL_OSC_SEL] = imx_clk_mux("mpll_osc_sel", CCM_CSCR, 4, 1, mpll_osc_sel_clks, ARRAY_SIZE(mpll_osc_sel_clks));
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clk[IMX27_CLK_MPLL_SEL] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks, ARRAY_SIZE(mpll_sel_clks));
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clk[IMX27_CLK_MPLL] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0);
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clk[IMX27_CLK_SPLL] = imx_clk_pllv1("spll", "ckih", CCM_SPCTL0);
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clk[IMX27_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1);
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clk[IMX27_CLK_MPLL_MAIN2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3);
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if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
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clk[ahb] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 8, 2);
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clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2);
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clk[IMX27_CLK_AHB] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 8, 2);
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clk[IMX27_CLK_IPG] = imx_clk_fixed_factor("ipg", "ahb", 1, 2);
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} else {
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clk[ahb] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 9, 4);
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clk[ipg] = imx_clk_divider("ipg", "ahb", CCM_CSCR, 8, 1);
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clk[IMX27_CLK_AHB] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 9, 4);
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clk[IMX27_CLK_IPG] = imx_clk_divider("ipg", "ahb", CCM_CSCR, 8, 1);
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}
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clk[mshc_div] = imx_clk_divider("mshc_div", "ahb", CCM_PCDR0, 0, 6);
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clk[nfc_div] = imx_clk_divider("nfc_div", "ahb", CCM_PCDR0, 6, 4);
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clk[per1_div] = imx_clk_divider("per1_div", "mpll_main2", CCM_PCDR1, 0, 6);
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clk[per2_div] = imx_clk_divider("per2_div", "mpll_main2", CCM_PCDR1, 8, 6);
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clk[per3_div] = imx_clk_divider("per3_div", "mpll_main2", CCM_PCDR1, 16, 6);
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clk[per4_div] = imx_clk_divider("per4_div", "mpll_main2", CCM_PCDR1, 24, 6);
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clk[vpu_sel] = imx_clk_mux("vpu_sel", CCM_CSCR, 21, 1, vpu_sel_clks, ARRAY_SIZE(vpu_sel_clks));
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clk[vpu_div] = imx_clk_divider("vpu_div", "vpu_sel", CCM_PCDR0, 10, 6);
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clk[usb_div] = imx_clk_divider("usb_div", "spll_gate", CCM_CSCR, 28, 3);
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clk[cpu_sel] = imx_clk_mux("cpu_sel", CCM_CSCR, 15, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks));
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clk[clko_sel] = imx_clk_mux("clko_sel", CCM_CCSR, 0, 5, clko_sel_clks, ARRAY_SIZE(clko_sel_clks));
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clk[IMX27_CLK_MSHC_DIV] = imx_clk_divider("mshc_div", "ahb", CCM_PCDR0, 0, 6);
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clk[IMX27_CLK_NFC_DIV] = imx_clk_divider("nfc_div", "ahb", CCM_PCDR0, 6, 4);
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clk[IMX27_CLK_PER1_DIV] = imx_clk_divider("per1_div", "mpll_main2", CCM_PCDR1, 0, 6);
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clk[IMX27_CLK_PER2_DIV] = imx_clk_divider("per2_div", "mpll_main2", CCM_PCDR1, 8, 6);
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clk[IMX27_CLK_PER3_DIV] = imx_clk_divider("per3_div", "mpll_main2", CCM_PCDR1, 16, 6);
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clk[IMX27_CLK_PER4_DIV] = imx_clk_divider("per4_div", "mpll_main2", CCM_PCDR1, 24, 6);
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clk[IMX27_CLK_VPU_SEL] = imx_clk_mux("vpu_sel", CCM_CSCR, 21, 1, vpu_sel_clks, ARRAY_SIZE(vpu_sel_clks));
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clk[IMX27_CLK_VPU_DIV] = imx_clk_divider("vpu_div", "vpu_sel", CCM_PCDR0, 10, 6);
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clk[IMX27_CLK_USB_DIV] = imx_clk_divider("usb_div", "spll_gate", CCM_CSCR, 28, 3);
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clk[IMX27_CLK_CPU_SEL] = imx_clk_mux("cpu_sel", CCM_CSCR, 15, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks));
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clk[IMX27_CLK_CLKO_SEL] = imx_clk_mux("clko_sel", CCM_CCSR, 0, 5, clko_sel_clks, ARRAY_SIZE(clko_sel_clks));
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if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
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clk[cpu_div] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 12, 2);
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clk[IMX27_CLK_CPU_DIV] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 12, 2);
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else
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clk[cpu_div] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 13, 3);
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clk[clko_div] = imx_clk_divider("clko_div", "clko_sel", CCM_PCDR0, 22, 3);
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clk[ssi1_sel] = imx_clk_mux("ssi1_sel", CCM_CSCR, 22, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
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clk[ssi2_sel] = imx_clk_mux("ssi2_sel", CCM_CSCR, 23, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
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clk[ssi1_div] = imx_clk_divider("ssi1_div", "ssi1_sel", CCM_PCDR0, 16, 6);
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clk[ssi2_div] = imx_clk_divider("ssi2_div", "ssi2_sel", CCM_PCDR0, 26, 6);
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clk[clko_en] = imx_clk_gate("clko_en", "clko_div", CCM_PCCR0, 0);
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clk[ssi2_ipg_gate] = imx_clk_gate("ssi2_ipg_gate", "ipg", CCM_PCCR0, 0);
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clk[ssi1_ipg_gate] = imx_clk_gate("ssi1_ipg_gate", "ipg", CCM_PCCR0, 1);
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clk[slcdc_ipg_gate] = imx_clk_gate("slcdc_ipg_gate", "ipg", CCM_PCCR0, 2);
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clk[sdhc3_ipg_gate] = imx_clk_gate("sdhc3_ipg_gate", "ipg", CCM_PCCR0, 3);
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clk[sdhc2_ipg_gate] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 4);
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clk[sdhc1_ipg_gate] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 5);
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clk[scc_ipg_gate] = imx_clk_gate("scc_ipg_gate", "ipg", CCM_PCCR0, 6);
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clk[sahara_ipg_gate] = imx_clk_gate("sahara_ipg_gate", "ipg", CCM_PCCR0, 7);
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clk[rtic_ipg_gate] = imx_clk_gate("rtic_ipg_gate", "ipg", CCM_PCCR0, 8);
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clk[rtc_ipg_gate] = imx_clk_gate("rtc_ipg_gate", "ipg", CCM_PCCR0, 9);
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clk[pwm_ipg_gate] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR0, 11);
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clk[owire_ipg_gate] = imx_clk_gate("owire_ipg_gate", "ipg", CCM_PCCR0, 12);
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clk[mshc_ipg_gate] = imx_clk_gate("mshc_ipg_gate", "ipg", CCM_PCCR0, 13);
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clk[lcdc_ipg_gate] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 14);
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clk[kpp_ipg_gate] = imx_clk_gate("kpp_ipg_gate", "ipg", CCM_PCCR0, 15);
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clk[iim_ipg_gate] = imx_clk_gate("iim_ipg_gate", "ipg", CCM_PCCR0, 16);
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clk[i2c2_ipg_gate] = imx_clk_gate("i2c2_ipg_gate", "ipg", CCM_PCCR0, 17);
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clk[i2c1_ipg_gate] = imx_clk_gate("i2c1_ipg_gate", "ipg", CCM_PCCR0, 18);
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clk[gpt6_ipg_gate] = imx_clk_gate("gpt6_ipg_gate", "ipg", CCM_PCCR0, 19);
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clk[gpt5_ipg_gate] = imx_clk_gate("gpt5_ipg_gate", "ipg", CCM_PCCR0, 20);
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clk[gpt4_ipg_gate] = imx_clk_gate("gpt4_ipg_gate", "ipg", CCM_PCCR0, 21);
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clk[gpt3_ipg_gate] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR0, 22);
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clk[gpt2_ipg_gate] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR0, 23);
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clk[gpt1_ipg_gate] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR0, 24);
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clk[gpio_ipg_gate] = imx_clk_gate("gpio_ipg_gate", "ipg", CCM_PCCR0, 25);
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clk[fec_ipg_gate] = imx_clk_gate("fec_ipg_gate", "ipg", CCM_PCCR0, 26);
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clk[emma_ipg_gate] = imx_clk_gate("emma_ipg_gate", "ipg", CCM_PCCR0, 27);
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clk[dma_ipg_gate] = imx_clk_gate("dma_ipg_gate", "ipg", CCM_PCCR0, 28);
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clk[cspi3_ipg_gate] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR0, 29);
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clk[cspi2_ipg_gate] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 30);
|
||||
clk[cspi1_ipg_gate] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 31);
|
||||
clk[mshc_baud_gate] = imx_clk_gate("mshc_baud_gate", "mshc_div", CCM_PCCR1, 2);
|
||||
clk[nfc_baud_gate] = imx_clk_gate("nfc_baud_gate", "nfc_div", CCM_PCCR1, 3);
|
||||
clk[ssi2_baud_gate] = imx_clk_gate("ssi2_baud_gate", "ssi2_div", CCM_PCCR1, 4);
|
||||
clk[ssi1_baud_gate] = imx_clk_gate("ssi1_baud_gate", "ssi1_div", CCM_PCCR1, 5);
|
||||
clk[vpu_baud_gate] = imx_clk_gate("vpu_baud_gate", "vpu_div", CCM_PCCR1, 6);
|
||||
clk[per4_gate] = imx_clk_gate("per4_gate", "per4_div", CCM_PCCR1, 7);
|
||||
clk[per3_gate] = imx_clk_gate("per3_gate", "per3_div", CCM_PCCR1, 8);
|
||||
clk[per2_gate] = imx_clk_gate("per2_gate", "per2_div", CCM_PCCR1, 9);
|
||||
clk[per1_gate] = imx_clk_gate("per1_gate", "per1_div", CCM_PCCR1, 10);
|
||||
clk[usb_ahb_gate] = imx_clk_gate("usb_ahb_gate", "ahb", CCM_PCCR1, 11);
|
||||
clk[slcdc_ahb_gate] = imx_clk_gate("slcdc_ahb_gate", "ahb", CCM_PCCR1, 12);
|
||||
clk[sahara_ahb_gate] = imx_clk_gate("sahara_ahb_gate", "ahb", CCM_PCCR1, 13);
|
||||
clk[rtic_ahb_gate] = imx_clk_gate("rtic_ahb_gate", "ahb", CCM_PCCR1, 14);
|
||||
clk[lcdc_ahb_gate] = imx_clk_gate("lcdc_ahb_gate", "ahb", CCM_PCCR1, 15);
|
||||
clk[vpu_ahb_gate] = imx_clk_gate("vpu_ahb_gate", "ahb", CCM_PCCR1, 16);
|
||||
clk[fec_ahb_gate] = imx_clk_gate("fec_ahb_gate", "ahb", CCM_PCCR1, 17);
|
||||
clk[emma_ahb_gate] = imx_clk_gate("emma_ahb_gate", "ahb", CCM_PCCR1, 18);
|
||||
clk[emi_ahb_gate] = imx_clk_gate("emi_ahb_gate", "ahb", CCM_PCCR1, 19);
|
||||
clk[dma_ahb_gate] = imx_clk_gate("dma_ahb_gate", "ahb", CCM_PCCR1, 20);
|
||||
clk[csi_ahb_gate] = imx_clk_gate("csi_ahb_gate", "ahb", CCM_PCCR1, 21);
|
||||
clk[brom_ahb_gate] = imx_clk_gate("brom_ahb_gate", "ahb", CCM_PCCR1, 22);
|
||||
clk[ata_ahb_gate] = imx_clk_gate("ata_ahb_gate", "ahb", CCM_PCCR1, 23);
|
||||
clk[wdog_ipg_gate] = imx_clk_gate("wdog_ipg_gate", "ipg", CCM_PCCR1, 24);
|
||||
clk[usb_ipg_gate] = imx_clk_gate("usb_ipg_gate", "ipg", CCM_PCCR1, 25);
|
||||
clk[uart6_ipg_gate] = imx_clk_gate("uart6_ipg_gate", "ipg", CCM_PCCR1, 26);
|
||||
clk[uart5_ipg_gate] = imx_clk_gate("uart5_ipg_gate", "ipg", CCM_PCCR1, 27);
|
||||
clk[uart4_ipg_gate] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR1, 28);
|
||||
clk[uart3_ipg_gate] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR1, 29);
|
||||
clk[uart2_ipg_gate] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR1, 30);
|
||||
clk[uart1_ipg_gate] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR1, 31);
|
||||
clk[IMX27_CLK_CPU_DIV] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 13, 3);
|
||||
|
||||
clk[IMX27_CLK_CLKO_DIV] = imx_clk_divider("clko_div", "clko_sel", CCM_PCDR0, 22, 3);
|
||||
clk[IMX27_CLK_SSI1_SEL] = imx_clk_mux("ssi1_sel", CCM_CSCR, 22, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
|
||||
clk[IMX27_CLK_SSI2_SEL] = imx_clk_mux("ssi2_sel", CCM_CSCR, 23, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
|
||||
clk[IMX27_CLK_SSI1_DIV] = imx_clk_divider("ssi1_div", "ssi1_sel", CCM_PCDR0, 16, 6);
|
||||
clk[IMX27_CLK_SSI2_DIV] = imx_clk_divider("ssi2_div", "ssi2_sel", CCM_PCDR0, 26, 6);
|
||||
clk[IMX27_CLK_CLKO_EN] = imx_clk_gate("clko_en", "clko_div", CCM_PCCR0, 0);
|
||||
clk[IMX27_CLK_SSI2_IPG_GATE] = imx_clk_gate("ssi2_ipg_gate", "ipg", CCM_PCCR0, 0);
|
||||
clk[IMX27_CLK_SSI1_IPG_GATE] = imx_clk_gate("ssi1_ipg_gate", "ipg", CCM_PCCR0, 1);
|
||||
clk[IMX27_CLK_SLCDC_IPG_GATE] = imx_clk_gate("slcdc_ipg_gate", "ipg", CCM_PCCR0, 2);
|
||||
clk[IMX27_CLK_SDHC3_IPG_GATE] = imx_clk_gate("sdhc3_ipg_gate", "ipg", CCM_PCCR0, 3);
|
||||
clk[IMX27_CLK_SDHC2_IPG_GATE] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 4);
|
||||
clk[IMX27_CLK_SDHC1_IPG_GATE] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 5);
|
||||
clk[IMX27_CLK_SCC_IPG_GATE] = imx_clk_gate("scc_ipg_gate", "ipg", CCM_PCCR0, 6);
|
||||
clk[IMX27_CLK_SAHARA_IPG_GATE] = imx_clk_gate("sahara_ipg_gate", "ipg", CCM_PCCR0, 7);
|
||||
clk[IMX27_CLK_RTIC_IPG_GATE] = imx_clk_gate("rtic_ipg_gate", "ipg", CCM_PCCR0, 8);
|
||||
clk[IMX27_CLK_RTC_IPG_GATE] = imx_clk_gate("rtc_ipg_gate", "ipg", CCM_PCCR0, 9);
|
||||
clk[IMX27_CLK_PWM_IPG_GATE] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR0, 11);
|
||||
clk[IMX27_CLK_OWIRE_IPG_GATE] = imx_clk_gate("owire_ipg_gate", "ipg", CCM_PCCR0, 12);
|
||||
clk[IMX27_CLK_MSHC_IPG_GATE] = imx_clk_gate("mshc_ipg_gate", "ipg", CCM_PCCR0, 13);
|
||||
clk[IMX27_CLK_LCDC_IPG_GATE] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 14);
|
||||
clk[IMX27_CLK_KPP_IPG_GATE] = imx_clk_gate("kpp_ipg_gate", "ipg", CCM_PCCR0, 15);
|
||||
clk[IMX27_CLK_IIM_IPG_GATE] = imx_clk_gate("iim_ipg_gate", "ipg", CCM_PCCR0, 16);
|
||||
clk[IMX27_CLK_I2C2_IPG_GATE] = imx_clk_gate("i2c2_ipg_gate", "ipg", CCM_PCCR0, 17);
|
||||
clk[IMX27_CLK_I2C1_IPG_GATE] = imx_clk_gate("i2c1_ipg_gate", "ipg", CCM_PCCR0, 18);
|
||||
clk[IMX27_CLK_GPT6_IPG_GATE] = imx_clk_gate("gpt6_ipg_gate", "ipg", CCM_PCCR0, 19);
|
||||
clk[IMX27_CLK_GPT5_IPG_GATE] = imx_clk_gate("gpt5_ipg_gate", "ipg", CCM_PCCR0, 20);
|
||||
clk[IMX27_CLK_GPT4_IPG_GATE] = imx_clk_gate("gpt4_ipg_gate", "ipg", CCM_PCCR0, 21);
|
||||
clk[IMX27_CLK_GPT3_IPG_GATE] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR0, 22);
|
||||
clk[IMX27_CLK_GPT2_IPG_GATE] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR0, 23);
|
||||
clk[IMX27_CLK_GPT1_IPG_GATE] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR0, 24);
|
||||
clk[IMX27_CLK_GPIO_IPG_GATE] = imx_clk_gate("gpio_ipg_gate", "ipg", CCM_PCCR0, 25);
|
||||
clk[IMX27_CLK_FEC_IPG_GATE] = imx_clk_gate("fec_ipg_gate", "ipg", CCM_PCCR0, 26);
|
||||
clk[IMX27_CLK_EMMA_IPG_GATE] = imx_clk_gate("emma_ipg_gate", "ipg", CCM_PCCR0, 27);
|
||||
clk[IMX27_CLK_DMA_IPG_GATE] = imx_clk_gate("dma_ipg_gate", "ipg", CCM_PCCR0, 28);
|
||||
clk[IMX27_CLK_CSPI3_IPG_GATE] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR0, 29);
|
||||
clk[IMX27_CLK_CSPI2_IPG_GATE] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 30);
|
||||
clk[IMX27_CLK_CSPI1_IPG_GATE] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 31);
|
||||
clk[IMX27_CLK_MSHC_BAUD_GATE] = imx_clk_gate("mshc_baud_gate", "mshc_div", CCM_PCCR1, 2);
|
||||
clk[IMX27_CLK_NFC_BAUD_GATE] = imx_clk_gate("nfc_baud_gate", "nfc_div", CCM_PCCR1, 3);
|
||||
clk[IMX27_CLK_SSI2_BAUD_GATE] = imx_clk_gate("ssi2_baud_gate", "ssi2_div", CCM_PCCR1, 4);
|
||||
clk[IMX27_CLK_SSI1_BAUD_GATE] = imx_clk_gate("ssi1_baud_gate", "ssi1_div", CCM_PCCR1, 5);
|
||||
clk[IMX27_CLK_VPU_BAUD_GATE] = imx_clk_gate("vpu_baud_gate", "vpu_div", CCM_PCCR1, 6);
|
||||
clk[IMX27_CLK_PER4_GATE] = imx_clk_gate("per4_gate", "per4_div", CCM_PCCR1, 7);
|
||||
clk[IMX27_CLK_PER3_GATE] = imx_clk_gate("per3_gate", "per3_div", CCM_PCCR1, 8);
|
||||
clk[IMX27_CLK_PER2_GATE] = imx_clk_gate("per2_gate", "per2_div", CCM_PCCR1, 9);
|
||||
clk[IMX27_CLK_PER1_GATE] = imx_clk_gate("per1_gate", "per1_div", CCM_PCCR1, 10);
|
||||
clk[IMX27_CLK_USB_AHB_GATE] = imx_clk_gate("usb_ahb_gate", "ahb", CCM_PCCR1, 11);
|
||||
clk[IMX27_CLK_SLCDC_AHB_GATE] = imx_clk_gate("slcdc_ahb_gate", "ahb", CCM_PCCR1, 12);
|
||||
clk[IMX27_CLK_SAHARA_AHB_GATE] = imx_clk_gate("sahara_ahb_gate", "ahb", CCM_PCCR1, 13);
|
||||
clk[IMX27_CLK_RTIC_AHB_GATE] = imx_clk_gate("rtic_ahb_gate", "ahb", CCM_PCCR1, 14);
|
||||
clk[IMX27_CLK_LCDC_AHB_GATE] = imx_clk_gate("lcdc_ahb_gate", "ahb", CCM_PCCR1, 15);
|
||||
clk[IMX27_CLK_VPU_AHB_GATE] = imx_clk_gate("vpu_ahb_gate", "ahb", CCM_PCCR1, 16);
|
||||
clk[IMX27_CLK_FEC_AHB_GATE] = imx_clk_gate("fec_ahb_gate", "ahb", CCM_PCCR1, 17);
|
||||
clk[IMX27_CLK_EMMA_AHB_GATE] = imx_clk_gate("emma_ahb_gate", "ahb", CCM_PCCR1, 18);
|
||||
clk[IMX27_CLK_EMI_AHB_GATE] = imx_clk_gate("emi_ahb_gate", "ahb", CCM_PCCR1, 19);
|
||||
clk[IMX27_CLK_DMA_AHB_GATE] = imx_clk_gate("dma_ahb_gate", "ahb", CCM_PCCR1, 20);
|
||||
clk[IMX27_CLK_CSI_AHB_GATE] = imx_clk_gate("csi_ahb_gate", "ahb", CCM_PCCR1, 21);
|
||||
clk[IMX27_CLK_BROM_AHB_GATE] = imx_clk_gate("brom_ahb_gate", "ahb", CCM_PCCR1, 22);
|
||||
clk[IMX27_CLK_ATA_AHB_GATE] = imx_clk_gate("ata_ahb_gate", "ahb", CCM_PCCR1, 23);
|
||||
clk[IMX27_CLK_WDOG_IPG_GATE] = imx_clk_gate("wdog_ipg_gate", "ipg", CCM_PCCR1, 24);
|
||||
clk[IMX27_CLK_USB_IPG_GATE] = imx_clk_gate("usb_ipg_gate", "ipg", CCM_PCCR1, 25);
|
||||
clk[IMX27_CLK_UART6_IPG_GATE] = imx_clk_gate("uart6_ipg_gate", "ipg", CCM_PCCR1, 26);
|
||||
clk[IMX27_CLK_UART5_IPG_GATE] = imx_clk_gate("uart5_ipg_gate", "ipg", CCM_PCCR1, 27);
|
||||
clk[IMX27_CLK_UART4_IPG_GATE] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR1, 28);
|
||||
clk[IMX27_CLK_UART3_IPG_GATE] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR1, 29);
|
||||
clk[IMX27_CLK_UART2_IPG_GATE] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR1, 30);
|
||||
clk[IMX27_CLK_UART1_IPG_GATE] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR1, 31);
|
||||
|
||||
imx_check_clocks(clk, ARRAY_SIZE(clk));
|
||||
|
||||
clk_register_clkdev(clk[cpu_div], NULL, "cpu0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_CPU_DIV], NULL, "cpu0");
|
||||
|
||||
clk_prepare_enable(clk[emi_ahb_gate]);
|
||||
clk_prepare_enable(clk[IMX27_CLK_EMI_AHB_GATE]);
|
||||
|
||||
imx_print_silicon_rev("i.MX27", mx27_revision());
|
||||
}
|
||||
|
|
@ -214,67 +191,67 @@ int __init mx27_clocks_init(unsigned long fref)
|
|||
|
||||
_mx27_clocks_init(fref);
|
||||
|
||||
clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0");
|
||||
clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.0");
|
||||
clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1");
|
||||
clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.1");
|
||||
clk_register_clkdev(clk[uart3_ipg_gate], "ipg", "imx21-uart.2");
|
||||
clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.2");
|
||||
clk_register_clkdev(clk[uart4_ipg_gate], "ipg", "imx21-uart.3");
|
||||
clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.3");
|
||||
clk_register_clkdev(clk[uart5_ipg_gate], "ipg", "imx21-uart.4");
|
||||
clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.4");
|
||||
clk_register_clkdev(clk[uart6_ipg_gate], "ipg", "imx21-uart.5");
|
||||
clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.5");
|
||||
clk_register_clkdev(clk[gpt1_ipg_gate], "ipg", "imx-gpt.0");
|
||||
clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.0");
|
||||
clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.0");
|
||||
clk_register_clkdev(clk[sdhc1_ipg_gate], "ipg", "imx21-mmc.0");
|
||||
clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.1");
|
||||
clk_register_clkdev(clk[sdhc2_ipg_gate], "ipg", "imx21-mmc.1");
|
||||
clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.2");
|
||||
clk_register_clkdev(clk[sdhc2_ipg_gate], "ipg", "imx21-mmc.2");
|
||||
clk_register_clkdev(clk[per2_gate], "per", "imx27-cspi.0");
|
||||
clk_register_clkdev(clk[cspi1_ipg_gate], "ipg", "imx27-cspi.0");
|
||||
clk_register_clkdev(clk[per2_gate], "per", "imx27-cspi.1");
|
||||
clk_register_clkdev(clk[cspi2_ipg_gate], "ipg", "imx27-cspi.1");
|
||||
clk_register_clkdev(clk[per2_gate], "per", "imx27-cspi.2");
|
||||
clk_register_clkdev(clk[cspi3_ipg_gate], "ipg", "imx27-cspi.2");
|
||||
clk_register_clkdev(clk[per3_gate], "per", "imx21-fb.0");
|
||||
clk_register_clkdev(clk[lcdc_ipg_gate], "ipg", "imx21-fb.0");
|
||||
clk_register_clkdev(clk[lcdc_ahb_gate], "ahb", "imx21-fb.0");
|
||||
clk_register_clkdev(clk[csi_ahb_gate], "ahb", "imx27-camera.0");
|
||||
clk_register_clkdev(clk[per4_gate], "per", "imx27-camera.0");
|
||||
clk_register_clkdev(clk[usb_div], "per", "imx-udc-mx27");
|
||||
clk_register_clkdev(clk[usb_ipg_gate], "ipg", "imx-udc-mx27");
|
||||
clk_register_clkdev(clk[usb_ahb_gate], "ahb", "imx-udc-mx27");
|
||||
clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0");
|
||||
clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.0");
|
||||
clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.0");
|
||||
clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.1");
|
||||
clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.1");
|
||||
clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.1");
|
||||
clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2");
|
||||
clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.2");
|
||||
clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.2");
|
||||
clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
|
||||
clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
|
||||
clk_register_clkdev(clk[nfc_baud_gate], NULL, "imx27-nand.0");
|
||||
clk_register_clkdev(clk[vpu_baud_gate], "per", "coda-imx27.0");
|
||||
clk_register_clkdev(clk[vpu_ahb_gate], "ahb", "coda-imx27.0");
|
||||
clk_register_clkdev(clk[dma_ahb_gate], "ahb", "imx27-dma");
|
||||
clk_register_clkdev(clk[dma_ipg_gate], "ipg", "imx27-dma");
|
||||
clk_register_clkdev(clk[fec_ipg_gate], "ipg", "imx27-fec.0");
|
||||
clk_register_clkdev(clk[fec_ahb_gate], "ahb", "imx27-fec.0");
|
||||
clk_register_clkdev(clk[wdog_ipg_gate], NULL, "imx2-wdt.0");
|
||||
clk_register_clkdev(clk[i2c1_ipg_gate], NULL, "imx21-i2c.0");
|
||||
clk_register_clkdev(clk[i2c2_ipg_gate], NULL, "imx21-i2c.1");
|
||||
clk_register_clkdev(clk[owire_ipg_gate], NULL, "mxc_w1.0");
|
||||
clk_register_clkdev(clk[kpp_ipg_gate], NULL, "imx-keypad");
|
||||
clk_register_clkdev(clk[emma_ahb_gate], "emma-ahb", "imx27-camera.0");
|
||||
clk_register_clkdev(clk[emma_ipg_gate], "emma-ipg", "imx27-camera.0");
|
||||
clk_register_clkdev(clk[emma_ahb_gate], "ahb", "m2m-emmaprp.0");
|
||||
clk_register_clkdev(clk[emma_ipg_gate], "ipg", "m2m-emmaprp.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_UART1_IPG_GATE], "ipg", "imx21-uart.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_UART2_IPG_GATE], "ipg", "imx21-uart.1");
|
||||
clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.1");
|
||||
clk_register_clkdev(clk[IMX27_CLK_UART3_IPG_GATE], "ipg", "imx21-uart.2");
|
||||
clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.2");
|
||||
clk_register_clkdev(clk[IMX27_CLK_UART4_IPG_GATE], "ipg", "imx21-uart.3");
|
||||
clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.3");
|
||||
clk_register_clkdev(clk[IMX27_CLK_UART5_IPG_GATE], "ipg", "imx21-uart.4");
|
||||
clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.4");
|
||||
clk_register_clkdev(clk[IMX27_CLK_UART6_IPG_GATE], "ipg", "imx21-uart.5");
|
||||
clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.5");
|
||||
clk_register_clkdev(clk[IMX27_CLK_GPT1_IPG_GATE], "ipg", "imx-gpt.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx-gpt.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx21-mmc.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_SDHC1_IPG_GATE], "ipg", "imx21-mmc.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx21-mmc.1");
|
||||
clk_register_clkdev(clk[IMX27_CLK_SDHC2_IPG_GATE], "ipg", "imx21-mmc.1");
|
||||
clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx21-mmc.2");
|
||||
clk_register_clkdev(clk[IMX27_CLK_SDHC2_IPG_GATE], "ipg", "imx21-mmc.2");
|
||||
clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx27-cspi.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_CSPI1_IPG_GATE], "ipg", "imx27-cspi.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx27-cspi.1");
|
||||
clk_register_clkdev(clk[IMX27_CLK_CSPI2_IPG_GATE], "ipg", "imx27-cspi.1");
|
||||
clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx27-cspi.2");
|
||||
clk_register_clkdev(clk[IMX27_CLK_CSPI3_IPG_GATE], "ipg", "imx27-cspi.2");
|
||||
clk_register_clkdev(clk[IMX27_CLK_PER3_GATE], "per", "imx21-fb.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_LCDC_IPG_GATE], "ipg", "imx21-fb.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_LCDC_AHB_GATE], "ahb", "imx21-fb.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_CSI_AHB_GATE], "ahb", "imx27-camera.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_PER4_GATE], "per", "imx27-camera.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "imx-udc-mx27");
|
||||
clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "imx-udc-mx27");
|
||||
clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "imx-udc-mx27");
|
||||
clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "mxc-ehci.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "mxc-ehci.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "mxc-ehci.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "mxc-ehci.1");
|
||||
clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "mxc-ehci.1");
|
||||
clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "mxc-ehci.1");
|
||||
clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "mxc-ehci.2");
|
||||
clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "mxc-ehci.2");
|
||||
clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "mxc-ehci.2");
|
||||
clk_register_clkdev(clk[IMX27_CLK_SSI1_IPG_GATE], NULL, "imx-ssi.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_SSI2_IPG_GATE], NULL, "imx-ssi.1");
|
||||
clk_register_clkdev(clk[IMX27_CLK_NFC_BAUD_GATE], NULL, "imx27-nand.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_VPU_BAUD_GATE], "per", "coda-imx27.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_VPU_AHB_GATE], "ahb", "coda-imx27.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_DMA_AHB_GATE], "ahb", "imx27-dma");
|
||||
clk_register_clkdev(clk[IMX27_CLK_DMA_IPG_GATE], "ipg", "imx27-dma");
|
||||
clk_register_clkdev(clk[IMX27_CLK_FEC_IPG_GATE], "ipg", "imx27-fec.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_FEC_AHB_GATE], "ahb", "imx27-fec.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_WDOG_IPG_GATE], NULL, "imx2-wdt.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_I2C1_IPG_GATE], NULL, "imx21-i2c.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_I2C2_IPG_GATE], NULL, "imx21-i2c.1");
|
||||
clk_register_clkdev(clk[IMX27_CLK_OWIRE_IPG_GATE], NULL, "mxc_w1.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_KPP_IPG_GATE], NULL, "imx-keypad");
|
||||
clk_register_clkdev(clk[IMX27_CLK_EMMA_AHB_GATE], "emma-ahb", "imx27-camera.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_EMMA_IPG_GATE], "emma-ipg", "imx27-camera.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_EMMA_AHB_GATE], "ahb", "m2m-emmaprp.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_EMMA_IPG_GATE], "ipg", "m2m-emmaprp.0");
|
||||
|
||||
mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1);
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,107 @@
|
|||
/*
|
||||
* Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_IMX27_H
|
||||
#define __DT_BINDINGS_CLOCK_IMX27_H
|
||||
|
||||
#define IMX27_CLK_DUMMY 0
|
||||
#define IMX27_CLK_CKIH 1
|
||||
#define IMX27_CLK_CKIL 2
|
||||
#define IMX27_CLK_MPLL 3
|
||||
#define IMX27_CLK_SPLL 4
|
||||
#define IMX27_CLK_MPLL_MAIN2 5
|
||||
#define IMX27_CLK_AHB 6
|
||||
#define IMX27_CLK_IPG 7
|
||||
#define IMX27_CLK_NFC_DIV 8
|
||||
#define IMX27_CLK_PER1_DIV 9
|
||||
#define IMX27_CLK_PER2_DIV 10
|
||||
#define IMX27_CLK_PER3_DIV 11
|
||||
#define IMX27_CLK_PER4_DIV 12
|
||||
#define IMX27_CLK_VPU_SEL 13
|
||||
#define IMX27_CLK_VPU_DIV 14
|
||||
#define IMX27_CLK_USB_DIV 15
|
||||
#define IMX27_CLK_CPU_SEL 16
|
||||
#define IMX27_CLK_CLKO_SEL 17
|
||||
#define IMX27_CLK_CPU_DIV 18
|
||||
#define IMX27_CLK_CLKO_DIV 19
|
||||
#define IMX27_CLK_SSI1_SEL 20
|
||||
#define IMX27_CLK_SSI2_SEL 21
|
||||
#define IMX27_CLK_SSI1_DIV 22
|
||||
#define IMX27_CLK_SSI2_DIV 23
|
||||
#define IMX27_CLK_CLKO_EN 24
|
||||
#define IMX27_CLK_SSI2_IPG_GATE 25
|
||||
#define IMX27_CLK_SSI1_IPG_GATE 26
|
||||
#define IMX27_CLK_SLCDC_IPG_GATE 27
|
||||
#define IMX27_CLK_SDHC3_IPG_GATE 28
|
||||
#define IMX27_CLK_SDHC2_IPG_GATE 29
|
||||
#define IMX27_CLK_SDHC1_IPG_GATE 30
|
||||
#define IMX27_CLK_SCC_IPG_GATE 31
|
||||
#define IMX27_CLK_SAHARA_IPG_GATE 32
|
||||
#define IMX27_CLK_RTC_IPG_GATE 33
|
||||
#define IMX27_CLK_PWM_IPG_GATE 34
|
||||
#define IMX27_CLK_OWIRE_IPG_GATE 35
|
||||
#define IMX27_CLK_LCDC_IPG_GATE 36
|
||||
#define IMX27_CLK_KPP_IPG_GATE 37
|
||||
#define IMX27_CLK_IIM_IPG_GATE 38
|
||||
#define IMX27_CLK_I2C2_IPG_GATE 39
|
||||
#define IMX27_CLK_I2C1_IPG_GATE 40
|
||||
#define IMX27_CLK_GPT6_IPG_GATE 41
|
||||
#define IMX27_CLK_GPT5_IPG_GATE 42
|
||||
#define IMX27_CLK_GPT4_IPG_GATE 43
|
||||
#define IMX27_CLK_GPT3_IPG_GATE 44
|
||||
#define IMX27_CLK_GPT2_IPG_GATE 45
|
||||
#define IMX27_CLK_GPT1_IPG_GATE 46
|
||||
#define IMX27_CLK_GPIO_IPG_GATE 47
|
||||
#define IMX27_CLK_FEC_IPG_GATE 48
|
||||
#define IMX27_CLK_EMMA_IPG_GATE 49
|
||||
#define IMX27_CLK_DMA_IPG_GATE 50
|
||||
#define IMX27_CLK_CSPI3_IPG_GATE 51
|
||||
#define IMX27_CLK_CSPI2_IPG_GATE 52
|
||||
#define IMX27_CLK_CSPI1_IPG_GATE 53
|
||||
#define IMX27_CLK_NFC_BAUD_GATE 54
|
||||
#define IMX27_CLK_SSI2_BAUD_GATE 55
|
||||
#define IMX27_CLK_SSI1_BAUD_GATE 56
|
||||
#define IMX27_CLK_VPU_BAUD_GATE 57
|
||||
#define IMX27_CLK_PER4_GATE 58
|
||||
#define IMX27_CLK_PER3_GATE 59
|
||||
#define IMX27_CLK_PER2_GATE 60
|
||||
#define IMX27_CLK_PER1_GATE 61
|
||||
#define IMX27_CLK_USB_AHB_GATE 62
|
||||
#define IMX27_CLK_SLCDC_AHB_GATE 63
|
||||
#define IMX27_CLK_SAHARA_AHB_GATE 64
|
||||
#define IMX27_CLK_LCDC_AHB_GATE 65
|
||||
#define IMX27_CLK_VPU_AHB_GATE 66
|
||||
#define IMX27_CLK_FEC_AHB_GATE 67
|
||||
#define IMX27_CLK_EMMA_AHB_GATE 68
|
||||
#define IMX27_CLK_EMI_AHB_GATE 69
|
||||
#define IMX27_CLK_DMA_AHB_GATE 70
|
||||
#define IMX27_CLK_CSI_AHB_GATE 71
|
||||
#define IMX27_CLK_BROM_AHB_GATE 72
|
||||
#define IMX27_CLK_ATA_AHB_GATE 73
|
||||
#define IMX27_CLK_WDOG_IPG_GATE 74
|
||||
#define IMX27_CLK_USB_IPG_GATE 75
|
||||
#define IMX27_CLK_UART6_IPG_GATE 76
|
||||
#define IMX27_CLK_UART5_IPG_GATE 77
|
||||
#define IMX27_CLK_UART4_IPG_GATE 78
|
||||
#define IMX27_CLK_UART3_IPG_GATE 79
|
||||
#define IMX27_CLK_UART2_IPG_GATE 80
|
||||
#define IMX27_CLK_UART1_IPG_GATE 81
|
||||
#define IMX27_CLK_CKIH_DIV1P5 82
|
||||
#define IMX27_CLK_FPM 83
|
||||
#define IMX27_CLK_MPLL_OSC_SEL 84
|
||||
#define IMX27_CLK_MPLL_SEL 85
|
||||
#define IMX27_CLK_SPLL_GATE 86
|
||||
#define IMX27_CLK_MSHC_DIV 87
|
||||
#define IMX27_CLK_RTIC_IPG_GATE 88
|
||||
#define IMX27_CLK_MSHC_IPG_GATE 89
|
||||
#define IMX27_CLK_RTIC_AHB_GATE 90
|
||||
#define IMX27_CLK_MSHC_BAUD_GATE 91
|
||||
#define IMX27_CLK_MAX 92
|
||||
|
||||
#endif
|
||||
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