drivers/net/wireless/ath5k - convert == (true|false) to simple logical tests
(test == true) is not nice. Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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Родитель
52933d815b
Коммит
e9010e2fdf
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@ -1,4 +1,4 @@
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/*
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/*
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* Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
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* Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
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* Copyright (c) 2007 Matthew W. S. Bell <mentor@madwifi.org>
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@ -85,12 +85,12 @@ static int ath5k_hw_disable_pspoll(struct ath5k_hw *);
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static inline unsigned int ath5k_hw_htoclock(unsigned int usec, bool turbo)
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{
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return turbo == true ? (usec * 80) : (usec * 40);
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return turbo ? (usec * 80) : (usec * 40);
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}
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static inline unsigned int ath5k_hw_clocktoh(unsigned int clock, bool turbo)
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{
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return turbo == true ? (clock / 80) : (clock / 40);
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return turbo ? (clock / 80) : (clock / 40);
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}
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/*
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@ -104,7 +104,7 @@ int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
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for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) {
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data = ath5k_hw_reg_read(ah, reg);
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if ((is_set == true) && (data & flag))
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if (is_set && (data & flag))
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break;
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else if ((data & flag) == val)
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break;
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@ -617,7 +617,7 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
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*/
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/*DCU/Antenna selection not available on 5210*/
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if (ah->ah_version != AR5K_AR5210) {
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if (change_channel == true) {
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if (change_channel) {
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/* Seq number for queue 0 -do this for all queues ? */
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s_seq = ath5k_hw_reg_read(ah,
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AR5K_QUEUE_DFS_SEQNUM(0));
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@ -631,7 +631,7 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
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s_led[1] = ath5k_hw_reg_read(ah, AR5K_GPIOCR);
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s_led[2] = ath5k_hw_reg_read(ah, AR5K_GPIODO);
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if (change_channel == true && ah->ah_rf_banks != NULL)
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if (change_channel && ah->ah_rf_banks != NULL)
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ath5k_hw_get_rf_gain(ah);
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@ -1122,7 +1122,7 @@ int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode,
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staid &= ~AR5K_STA_ID1_DEFAULT_ANTENNA;
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/* fallthrough */
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case AR5K_PM_NETWORK_SLEEP:
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if (set_chip == true)
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if (set_chip)
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ath5k_hw_reg_write(ah,
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AR5K_SLEEP_CTL_SLE | sleep_duration,
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AR5K_SLEEP_CTL);
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@ -1131,7 +1131,7 @@ int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode,
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break;
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case AR5K_PM_FULL_SLEEP:
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if (set_chip == true)
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if (set_chip)
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ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_SLP,
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AR5K_SLEEP_CTL);
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@ -1139,7 +1139,7 @@ int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode,
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break;
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case AR5K_PM_AWAKE:
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if (set_chip == false)
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if (!set_chip)
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goto commit;
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ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_WAKE,
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@ -1446,7 +1446,7 @@ int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase)
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trigger_level = AR5K_REG_MS(ath5k_hw_reg_read(ah, AR5K_TXCFG),
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AR5K_TXCFG_TXFULL);
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if (increase == false) {
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if (!increase) {
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if (--trigger_level < AR5K_TUNE_MIN_TX_FIFO_THRES)
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goto done;
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} else
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@ -3205,19 +3205,19 @@ int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
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return 0;
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/* Set Slot time */
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ath5k_hw_reg_write(ah, ah->ah_turbo == true ?
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ath5k_hw_reg_write(ah, ah->ah_turbo ?
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AR5K_INIT_SLOT_TIME_TURBO : AR5K_INIT_SLOT_TIME,
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AR5K_SLOT_TIME);
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/* Set ACK_CTS timeout */
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ath5k_hw_reg_write(ah, ah->ah_turbo == true ?
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ath5k_hw_reg_write(ah, ah->ah_turbo ?
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AR5K_INIT_ACK_CTS_TIMEOUT_TURBO :
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AR5K_INIT_ACK_CTS_TIMEOUT, AR5K_SLOT_TIME);
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/* Set Transmit Latency */
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ath5k_hw_reg_write(ah, ah->ah_turbo == true ?
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ath5k_hw_reg_write(ah, ah->ah_turbo ?
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AR5K_INIT_TRANSMIT_LATENCY_TURBO :
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AR5K_INIT_TRANSMIT_LATENCY, AR5K_USEC_5210);
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/* Set IFS0 */
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if (ah->ah_turbo == true)
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if (ah->ah_turbo)
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ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS_TURBO +
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(ah->ah_aifs + tq->tqi_aifs) *
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AR5K_INIT_SLOT_TIME_TURBO) <<
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@ -3230,16 +3230,16 @@ int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
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AR5K_INIT_SIFS, AR5K_IFS0);
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/* Set IFS1 */
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ath5k_hw_reg_write(ah, ah->ah_turbo == true ?
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ath5k_hw_reg_write(ah, ah->ah_turbo ?
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AR5K_INIT_PROTO_TIME_CNTRL_TURBO :
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AR5K_INIT_PROTO_TIME_CNTRL, AR5K_IFS1);
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/* Set PHY register 0x9844 (??) */
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ath5k_hw_reg_write(ah, ah->ah_turbo == true ?
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ath5k_hw_reg_write(ah, ah->ah_turbo ?
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(ath5k_hw_reg_read(ah, AR5K_PHY(17)) & ~0x7F) | 0x38 :
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(ath5k_hw_reg_read(ah, AR5K_PHY(17)) & ~0x7F) | 0x1C,
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AR5K_PHY(17));
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/* Set Frame Control Register */
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ath5k_hw_reg_write(ah, ah->ah_turbo == true ?
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ath5k_hw_reg_write(ah, ah->ah_turbo ?
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(AR5K_PHY_FRAME_CTL_INI | AR5K_PHY_TURBO_MODE |
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AR5K_PHY_TURBO_SHORT | 0x2020) :
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(AR5K_PHY_FRAME_CTL_INI | 0x1020),
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@ -3278,7 +3278,7 @@ int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
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/*
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* Calculate and set retry limits
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*/
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if (ah->ah_software_retry == true) {
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if (ah->ah_software_retry) {
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/* XXX Need to test this */
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retry_lg = ah->ah_limit_tx_retries;
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retry_sh = retry_lg = retry_lg > AR5K_DCU_RETRY_LMT_SH_RETRY ?
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@ -981,14 +981,14 @@ static unsigned int ath5k_hw_rfregs_op(u32 *rf, u32 offset, u32 reg, u32 bits,
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entry = ((first - 1) / 8) + offset;
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position = (first - 1) % 8;
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if (set == true)
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if (set)
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data = ath5k_hw_bitswap(reg, bits);
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for (i = shift = 0, left = bits; left > 0; position = 0, entry++, i++) {
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last = (position + left > 8) ? 8 : position + left;
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mask = (((1 << last) - 1) ^ ((1 << position) - 1)) << (col * 8);
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if (set == true) {
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if (set) {
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rf[entry] &= ~mask;
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rf[entry] |= ((data << position) << (col * 8)) & mask;
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data >>= (8 - position);
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@ -1001,7 +1001,7 @@ static unsigned int ath5k_hw_rfregs_op(u32 *rf, u32 offset, u32 reg, u32 bits,
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left -= 8 - position;
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}
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data = set == true ? 1 : ath5k_hw_bitswap(data, bits);
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data = set ? 1 : ath5k_hw_bitswap(data, bits);
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return data;
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}
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@ -1986,7 +1986,7 @@ static int ath5k_hw_rf511x_calibrate(struct ath5k_hw *ah,
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s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd;
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ATH5K_TRACE(ah->ah_sc);
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if (ah->ah_calibration == false ||
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if (!ah->ah_calibration ||
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ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN)
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goto done;
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@ -2218,7 +2218,7 @@ ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
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AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) |
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AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4);
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if (ah->ah_txpower.txp_tpc == true)
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if (ah->ah_txpower.txp_tpc)
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ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE |
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AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
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else
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