First round of arm devicetree changes.
Among the bigger changes are two new Veyron boards, support for the dual-core cortex-a7 rk3036 soc and addition of support for the crypto engine of the rk3288. Smaller changes include some IR receivers, updates of thermal settings more reflecting real- life and testing-results. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABCAAGBQJWYetUAAoJEPOmecmc0R2B4goIAIiVjdbuetKLxeEqDWmEdCnI AKlV+IM1CWt8ib2k5bCoaYmWwtujY6m/2oHhbJklHgv3+K32lltwgZMJPeJu7xi3 C02HCdq6DydsCb2154giKOXj+SMsNZ/c38Gk1sDFFPQCcwfgT9Hg+7HOXCim2Ac8 C/Ewi7z6bZKzkvwy28KrQVPDub2DB/JQAGp8DP9hfK9k23PtaQRoLhTExj68O6JK rRjB67hb1+xdKgf8ujXevIYvoacO1odW4fLnB7KC4ei/O2XycKK/4ohzrENe/zJ6 Y2wYnb1YGiLtjgx0DlpbPvaCE6/UyX+ZhVC4kUiB937/x1ZpCZX9ttLMT91gKx8= =F0Xt -----END PGP SIGNATURE----- Merge tag 'v4.5-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt Merge "rockchip dts32 changes for 4.5" from Heiko Stuebner: First round of arm devicetree changes. Among the bigger changes are two new Veyron boards, support for the dual-core cortex-a7 rk3036 soc and addition of support for the crypto engine of the rk3288. Smaller changes include some IR receivers, updates of thermal settings more reflecting real- life and testing-results. * tag 'v4.5-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: ARM: dts: rockchip: add gpio-ir-receiver to the R89 board ARM: dts: rockchip: add touchscreen node to veyron minnie ARM: dts: rockchip: add veyron-mickey board ARM: dts: rockchip: add veyron-brain board ARM: dts: rockchip: make sure edp_24m is associated to xin24m on veyron ARM: dts: rockchip: override thermal settings on veyron-speedy ARM: dts: rockchip: update the thermal management on rk3288 ARM: dts: rockchip: Add Crypto node for rk3288 ARM: dts: rockchip: add rk3036-evb board ARM: dts: rockchip: add core rk3036 dtsi clk: rockchip: add dt-binding header for rk3036 clk: rockchip: add an id for rk3288 crypto clk ARM: dts: rockchip: Add IR receiver to RK3288 Radxa Rock 2 Square ARM: dts: rockchip: add channels properties for i2s ARM: dts: rockchip: set system-power-controller property on rk3288-rock2 ARM: dts: rockchip: Setup rk3066/rk3188 ethernet0 alias for u-boot ARM: dts: rockchip: Setup rk3288 ethernet0 alias for u-boot
This commit is contained in:
Arnd Bergmann
Коммит
e9093d045a
|
|
@ -35,6 +35,11 @@ Rockchip platforms device tree bindings
|
|||
Required root node properties:
|
||||
- compatible = "netxeon,r89", "rockchip,rk3288";
|
||||
|
||||
- Google Brain (dev-board):
|
||||
Required root node properties:
|
||||
- compatible = "google,veyron-brain-rev0", "google,veyron-brain",
|
||||
"google,veyron", "rockchip,rk3288";
|
||||
|
||||
- Google Jaq (Haier Chromebook 11 and more):
|
||||
Required root node properties:
|
||||
- compatible = "google,veyron-jaq-rev5", "google,veyron-jaq-rev4",
|
||||
|
|
@ -49,6 +54,15 @@ Rockchip platforms device tree bindings
|
|||
"google,veyron-jerry-rev3", "google,veyron-jerry",
|
||||
"google,veyron", "rockchip,rk3288";
|
||||
|
||||
- Google Mickey (Asus Chromebit CS10):
|
||||
Required root node properties:
|
||||
- compatible = "google,veyron-mickey-rev8", "google,veyron-mickey-rev7",
|
||||
"google,veyron-mickey-rev6", "google,veyron-mickey-rev5",
|
||||
"google,veyron-mickey-rev4", "google,veyron-mickey-rev3",
|
||||
"google,veyron-mickey-rev2", "google,veyron-mickey-rev1",
|
||||
"google,veyron-mickey-rev0", "google,veyron-mickey",
|
||||
"google,veyron", "rockchip,rk3288";
|
||||
|
||||
- Google Minnie (Asus Chromebook Flip C100P):
|
||||
Required root node properties:
|
||||
- compatible = "google,veyron-minnie-rev4", "google,veyron-minnie-rev3",
|
||||
|
|
|
|||
|
|
@ -512,6 +512,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
|
|||
dtb-$(CONFIG_ARCH_REALVIEW) += \
|
||||
arm-realview-pb1176.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += \
|
||||
rk3036-evb.dtb \
|
||||
rk3066a-bqcurie2.dtb \
|
||||
rk3066a-marsboard.dtb \
|
||||
rk3066a-rayeager.dtb \
|
||||
|
|
@ -523,8 +524,10 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
|
|||
rk3288-popmetal.dtb \
|
||||
rk3288-r89.dtb \
|
||||
rk3288-rock2-square.dtb \
|
||||
rk3288-veyron-brain.dtb \
|
||||
rk3288-veyron-jaq.dtb \
|
||||
rk3288-veyron-jerry.dtb \
|
||||
rk3288-veyron-mickey.dtb \
|
||||
rk3288-veyron-minnie.dtb \
|
||||
rk3288-veyron-pinky.dtb \
|
||||
rk3288-veyron-speedy.dtb
|
||||
|
|
|
|||
|
|
@ -0,0 +1,64 @@
|
|||
/*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "rk3036.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Rockchip RK3036 Evaluation board";
|
||||
compatible = "rockchip,rk3036-evb", "rockchip,rk3036";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
|
||||
hym8563: hym8563@51 {
|
||||
compatible = "haoyu,hym8563";
|
||||
reg = <0x51>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "xin32k";
|
||||
};
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,554 @@
|
|||
/*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include <dt-bindings/clock/rk3036-cru.h>
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "rockchip,rk3036";
|
||||
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
aliases {
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
i2c2 = &i2c2;
|
||||
mshc0 = &emmc;
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
serial2 = &uart2;
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x60000000 0x40000000>;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enable-method = "rockchip,rk3036-smp";
|
||||
|
||||
cpu0: cpu@f00 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0xf00>;
|
||||
resets = <&cru SRST_CORE0>;
|
||||
operating-points = <
|
||||
/* KHz uV */
|
||||
816000 1000000
|
||||
>;
|
||||
clock-latency = <40000>;
|
||||
clocks = <&cru ARMCLK>;
|
||||
};
|
||||
|
||||
cpu1: cpu@f01 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0xf01>;
|
||||
resets = <&cru SRST_CORE1>;
|
||||
};
|
||||
};
|
||||
|
||||
amba {
|
||||
compatible = "arm,amba-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
pdma: pdma@20078000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x20078000 0x4000>;
|
||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#dma-cells = <1>;
|
||||
clocks = <&cru ACLK_DMAC2>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
};
|
||||
|
||||
arm-pmu {
|
||||
compatible = "arm,cortex-a7-pmu";
|
||||
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&cpu0>, <&cpu1>;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
arm,cpu-registers-not-fw-configured;
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
|
||||
xin24m: oscillator {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <24000000>;
|
||||
clock-output-names = "xin24m";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
bus_intmem@10080000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x10080000 0x2000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x10080000 0x2000>;
|
||||
|
||||
smp-sram@0 {
|
||||
compatible = "rockchip,rk3066-smp-sram";
|
||||
reg = <0x00 0x10>;
|
||||
};
|
||||
};
|
||||
|
||||
gic: interrupt-controller@10139000 {
|
||||
compatible = "arm,gic-400";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
|
||||
reg = <0x10139000 0x1000>,
|
||||
<0x1013a000 0x1000>,
|
||||
<0x1013c000 0x2000>,
|
||||
<0x1013e000 0x2000>;
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
};
|
||||
|
||||
usb_otg: usb@10180000 {
|
||||
compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
|
||||
"snps,dwc2";
|
||||
reg = <0x10180000 0x40000>;
|
||||
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru HCLK_OTG0>;
|
||||
clock-names = "otg";
|
||||
dr_mode = "otg";
|
||||
g-np-tx-fifo-size = <16>;
|
||||
g-rx-fifo-size = <275>;
|
||||
g-tx-fifo-size = <256 128 128 64 64 32>;
|
||||
g-use-dma;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_host: usb@101c0000 {
|
||||
compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
|
||||
"snps,dwc2";
|
||||
reg = <0x101c0000 0x40000>;
|
||||
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru HCLK_OTG1>;
|
||||
clock-names = "otg";
|
||||
dr_mode = "host";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
emmc: dwmmc@1021c000 {
|
||||
compatible = "rockchip,rk3288-dw-mshc";
|
||||
reg = <0x1021c000 0x4000>;
|
||||
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
||||
broken-cd;
|
||||
bus-width = <8>;
|
||||
cap-mmc-highspeed;
|
||||
clock-frequency = <37500000>;
|
||||
clock-freq-min-max = <400000 37500000>;
|
||||
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
|
||||
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
|
||||
clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
|
||||
default-sample-phase = <158>;
|
||||
disable-wp;
|
||||
dmas = <&pdma 12>;
|
||||
dma-names = "rx-tx";
|
||||
fifo-depth = <0x100>;
|
||||
mmc-ddr-1_8v;
|
||||
non-removable;
|
||||
num-slots = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2s: i2s@10220000 {
|
||||
compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
|
||||
reg = <0x10220000 0x4000>;
|
||||
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "i2s_hclk", "i2s_clk";
|
||||
clocks = <&cru HCLK_I2S>, <&cru SCLK_I2S>;
|
||||
dmas = <&pdma 0>, <&pdma 1>;
|
||||
dma-names = "tx", "rx";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2s_bus>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cru: clock-controller@20000000 {
|
||||
compatible = "rockchip,rk3036-cru";
|
||||
reg = <0x20000000 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
assigned-clocks = <&cru PLL_GPLL>;
|
||||
assigned-clock-rates = <594000000>;
|
||||
};
|
||||
|
||||
grf: syscon@20008000 {
|
||||
compatible = "rockchip,rk3036-grf", "syscon";
|
||||
reg = <0x20008000 0x1000>;
|
||||
};
|
||||
|
||||
acodec: acodec-ana@20030000 {
|
||||
compatible = "rk3036-codec";
|
||||
reg = <0x20030000 0x4000>;
|
||||
rockchip,grf = <&grf>;
|
||||
clock-names = "acodec_pclk";
|
||||
clocks = <&cru PCLK_ACODEC>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer: timer@20044000 {
|
||||
compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
|
||||
reg = <0x20044000 0x20>;
|
||||
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&xin24m>, <&cru PCLK_TIMER>;
|
||||
clock-names = "timer", "pclk";
|
||||
};
|
||||
|
||||
pwm0: pwm@20050000 {
|
||||
compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
|
||||
reg = <0x20050000 0x10>;
|
||||
#pwm-cells = <3>;
|
||||
clocks = <&cru PCLK_PWM>;
|
||||
clock-names = "pwm";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm0_pin>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm1: pwm@20050010 {
|
||||
compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
|
||||
reg = <0x20050010 0x10>;
|
||||
#pwm-cells = <3>;
|
||||
clocks = <&cru PCLK_PWM>;
|
||||
clock-names = "pwm";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm1_pin>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm2: pwm@20050020 {
|
||||
compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
|
||||
reg = <0x20050020 0x10>;
|
||||
#pwm-cells = <3>;
|
||||
clocks = <&cru PCLK_PWM>;
|
||||
clock-names = "pwm";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm2_pin>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm3: pwm@20050030 {
|
||||
compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
|
||||
reg = <0x20050030 0x10>;
|
||||
#pwm-cells = <2>;
|
||||
clocks = <&cru PCLK_PWM>;
|
||||
clock-names = "pwm";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm3_pin>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@20056000 {
|
||||
compatible = "rockchip,rk3288-i2c";
|
||||
reg = <0x20056000 0x1000>;
|
||||
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "i2c";
|
||||
clocks = <&cru PCLK_I2C1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c1_xfer>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@2005a000 {
|
||||
compatible = "rockchip,rk3288-i2c";
|
||||
reg = <0x2005a000 0x1000>;
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "i2c";
|
||||
clocks = <&cru PCLK_I2C2>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c2_xfer>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart0: serial@20060000 {
|
||||
compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
|
||||
reg = <0x20060000 0x100>;
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clock-frequency = <24000000>;
|
||||
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@20064000 {
|
||||
compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
|
||||
reg = <0x20064000 0x100>;
|
||||
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clock-frequency = <24000000>;
|
||||
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1_xfer>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@20068000 {
|
||||
compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
|
||||
reg = <0x20068000 0x100>;
|
||||
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clock-frequency = <24000000>;
|
||||
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart2_xfer>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@20072000 {
|
||||
compatible = "rockchip,rk3288-i2c";
|
||||
reg = <0x20072000 0x1000>;
|
||||
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "i2c";
|
||||
clocks = <&cru PCLK_I2C0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_xfer>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pinctrl: pinctrl {
|
||||
compatible = "rockchip,rk3036-pinctrl";
|
||||
rockchip,grf = <&grf>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
gpio0: gpio0@2007c000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x2007c000 0x100>;
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru PCLK_GPIO0>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio1: gpio1@20080000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x20080000 0x100>;
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru PCLK_GPIO1>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio2: gpio2@20084000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x20084000 0x100>;
|
||||
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru PCLK_GPIO2>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
pcfg_pull_up: pcfg-pull-up {
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
pcfg_pull_down: pcfg-pull-down {
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
pcfg_pull_none: pcfg-pull-none {
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pwm0 {
|
||||
pwm0_pin: pwm0-pin {
|
||||
rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm1 {
|
||||
pwm1_pin: pwm1-pin {
|
||||
rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm2 {
|
||||
pwm2_pin: pwm2-pin {
|
||||
rockchip,pins = <0 1 2 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm3 {
|
||||
pwm3_pin: pwm3-pin {
|
||||
rockchip,pins = <0 27 1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
emmc {
|
||||
/*
|
||||
* We run eMMC at max speed; bump up drive strength.
|
||||
* We also have external pulls, so disable the internal ones.
|
||||
*/
|
||||
emmc_clk: emmc-clk {
|
||||
rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
emmc_cmd: emmc-cmd {
|
||||
rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
emmc_bus8: emmc-bus8 {
|
||||
rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<1 25 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<1 26 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<1 27 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<1 28 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<1 29 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<1 30 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<1 31 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c0 {
|
||||
i2c0_xfer: i2c0-xfer {
|
||||
rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<0 1 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c1 {
|
||||
i2c1_xfer: i2c1-xfer {
|
||||
rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<0 3 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c2 {
|
||||
i2c2_xfer: i2c2-xfer {
|
||||
rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<2 21 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
i2s {
|
||||
i2s_bus: i2s-bus {
|
||||
rockchip,pins = <1 0 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<1 1 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<1 2 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<1 3 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<1 4 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<1 5 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
uart0 {
|
||||
uart0_xfer: uart0-xfer {
|
||||
rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_up>,
|
||||
<0 17 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart0_cts: uart0-cts {
|
||||
rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
uart0_rts: uart0-rts {
|
||||
rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
uart1 {
|
||||
uart1_xfer: uart1-xfer {
|
||||
rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<2 23 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
/* no rts / cts for uart1 */
|
||||
};
|
||||
|
||||
uart2 {
|
||||
uart2_xfer: uart2-xfer {
|
||||
rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<1 19 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
/* no rts / cts for uart2 */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -103,6 +103,8 @@
|
|||
dma-names = "tx", "rx";
|
||||
clock-names = "i2s_hclk", "i2s_clk";
|
||||
clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
|
||||
rockchip,playback-channels = <8>;
|
||||
rockchip,capture-channels = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -118,6 +120,8 @@
|
|||
dma-names = "tx", "rx";
|
||||
clock-names = "i2s_hclk", "i2s_clk";
|
||||
clocks = <&cru HCLK_I2S1>, <&cru SCLK_I2S1>;
|
||||
rockchip,playback-channels = <2>;
|
||||
rockchip,capture-channels = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -133,6 +137,8 @@
|
|||
dma-names = "tx", "rx";
|
||||
clock-names = "i2s_hclk", "i2s_clk";
|
||||
clocks = <&cru HCLK_I2S2>, <&cru SCLK_I2S2>;
|
||||
rockchip,playback-channels = <2>;
|
||||
rockchip,capture-channels = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -118,6 +118,8 @@
|
|||
dma-names = "tx", "rx";
|
||||
clock-names = "i2s_hclk", "i2s_clk";
|
||||
clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
|
||||
rockchip,playback-channels = <2>;
|
||||
rockchip,capture-channels = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -78,6 +78,13 @@
|
|||
};
|
||||
};
|
||||
|
||||
ir: ir-receiver {
|
||||
compatible = "gpio-ir-receiver";
|
||||
gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ir_int>;
|
||||
};
|
||||
|
||||
vcc_host: vcc-host-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
|
|
@ -310,6 +317,12 @@
|
|||
};
|
||||
};
|
||||
|
||||
ir {
|
||||
ir_int: ir-int {
|
||||
rockchip,pins = <7 0 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
pmic_int: pmic-int {
|
||||
rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
|
|
|
|||
|
|
@ -109,6 +109,7 @@
|
|||
act8846: act8846@5a {
|
||||
compatible = "active-semi,act8846";
|
||||
reg = <0x5a>;
|
||||
system-power-controller;
|
||||
inl1-supply = <&vcc_io>;
|
||||
inl2-supply = <&vcc_sys>;
|
||||
inl3-supply = <&vcc_20>;
|
||||
|
|
|
|||
|
|
@ -49,6 +49,13 @@
|
|||
stdout-path = "serial2:115200n8";
|
||||
};
|
||||
|
||||
ir: ir-receiver {
|
||||
compatible = "gpio-ir-receiver";
|
||||
gpios = <&gpio8 1 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ir_int>;
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "SPDIF";
|
||||
|
|
@ -131,6 +138,12 @@
|
|||
};
|
||||
|
||||
&pinctrl {
|
||||
ir {
|
||||
ir_int: ir-int {
|
||||
rockchip,pins = <8 1 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
pmic_int: pmic-int {
|
||||
rockchip,pins = <0 4 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
|
|
|
|||
|
|
@ -52,7 +52,7 @@ reserve_thermal: reserve_thermal {
|
|||
};
|
||||
|
||||
cpu_thermal: cpu_thermal {
|
||||
polling-delay-passive = <1000>; /* milliseconds */
|
||||
polling-delay-passive = <100>; /* milliseconds */
|
||||
polling-delay = <5000>; /* milliseconds */
|
||||
|
||||
thermal-sensors = <&tsadc 1>;
|
||||
|
|
@ -63,6 +63,11 @@ cpu_thermal: cpu_thermal {
|
|||
hysteresis = <2000>; /* millicelsius */
|
||||
type = "passive";
|
||||
};
|
||||
cpu_alert1: cpu_alert1 {
|
||||
temperature = <75000>; /* millicelsius */
|
||||
hysteresis = <2000>; /* millicelsius */
|
||||
type = "passive";
|
||||
};
|
||||
cpu_crit: cpu_crit {
|
||||
temperature = <90000>; /* millicelsius */
|
||||
hysteresis = <2000>; /* millicelsius */
|
||||
|
|
@ -73,6 +78,11 @@ cpu_thermal: cpu_thermal {
|
|||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&cpu_alert0>;
|
||||
cooling-device =
|
||||
<&cpu0 THERMAL_NO_LIMIT 6>;
|
||||
};
|
||||
map1 {
|
||||
trip = <&cpu_alert1>;
|
||||
cooling-device =
|
||||
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
|
|
@ -80,7 +90,7 @@ cpu_thermal: cpu_thermal {
|
|||
};
|
||||
|
||||
gpu_thermal: gpu_thermal {
|
||||
polling-delay-passive = <1000>; /* milliseconds */
|
||||
polling-delay-passive = <100>; /* milliseconds */
|
||||
polling-delay = <5000>; /* milliseconds */
|
||||
|
||||
thermal-sensors = <&tsadc 2>;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,139 @@
|
|||
/*
|
||||
* Google Veyron Brain Rev 0 board device tree source
|
||||
*
|
||||
* Copyright 2014 Google, Inc
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "rk3288-veyron.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Google Brain";
|
||||
compatible = "google,veyron-brain-rev0", "google,veyron-brain",
|
||||
"google,veyron", "rockchip,rk3288";
|
||||
|
||||
vcc33_sys: vcc33-sys {
|
||||
vin-supply = <&vcc_5v>;
|
||||
};
|
||||
|
||||
vcc33_io: vcc33_io {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc33_io";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&vcc33_sys>;
|
||||
/* This is gated by vcc_18 too */
|
||||
};
|
||||
|
||||
/* This turns on vbus for host2 and otg (dwc2) */
|
||||
vcc5_host2: vcc5-host2-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb2_pwr_en>;
|
||||
regulator-name = "vcc5_host2";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
hdmi {
|
||||
vcc50_hdmi_en: vcc50-hdmi-en {
|
||||
rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
dvs_1: dvs-1 {
|
||||
rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
|
||||
dvs_2: dvs-2 {
|
||||
rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
};
|
||||
|
||||
usb-host {
|
||||
usb2_pwr_en: usb2-pwr-en {
|
||||
rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rk808 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
|
||||
dvs-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>,
|
||||
<&gpio7 15 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
/delete-property/ vcc6-supply;
|
||||
|
||||
regulators {
|
||||
/* vcc33_io is sourced directly from vcc33_sys */
|
||||
/delete-node/ LDO_REG1;
|
||||
|
||||
/* This is not a pwren anymore, but the real power supply */
|
||||
vdd10_lcd: LDO_REG7 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-name = "vdd10_lcd";
|
||||
regulator-suspend-mem-disabled;
|
||||
};
|
||||
|
||||
vcc18_hdmi: SWITCH_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc18_hdmi";
|
||||
regulator-suspend-mem-disabled;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&vcc50_hdmi {
|
||||
enable-active-high;
|
||||
gpio = <&gpio7 2 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc50_hdmi_en>;
|
||||
};
|
||||
|
|
@ -0,0 +1,250 @@
|
|||
/*
|
||||
* Google Veyron Mickey Rev 0 board device tree source
|
||||
*
|
||||
* Copyright 2015 Google, Inc
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "rk3288-veyron.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Google Mickey";
|
||||
compatible = "google,veyron-mickey-rev8", "google,veyron-mickey-rev7",
|
||||
"google,veyron-mickey-rev6", "google,veyron-mickey-rev5",
|
||||
"google,veyron-mickey-rev4", "google,veyron-mickey-rev3",
|
||||
"google,veyron-mickey-rev2", "google,veyron-mickey-rev1",
|
||||
"google,veyron-mickey-rev0", "google,veyron-mickey",
|
||||
"google,veyron", "rockchip,rk3288";
|
||||
|
||||
vcc_5v: vcc-5v {
|
||||
vin-supply = <&vcc33_sys>;
|
||||
};
|
||||
|
||||
vcc33_io: vcc33_io {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc33_io";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&vcc33_sys>;
|
||||
};
|
||||
};
|
||||
|
||||
&cpu_thermal {
|
||||
/delete-node/ trips;
|
||||
/delete-node/ cooling-maps;
|
||||
|
||||
trips {
|
||||
cpu_alert_almost_warm: cpu_alert_almost_warm {
|
||||
temperature = <63000>; /* millicelsius */
|
||||
hysteresis = <2000>; /* millicelsius */
|
||||
type = "passive";
|
||||
};
|
||||
cpu_alert_warm: cpu_alert_warm {
|
||||
temperature = <65000>; /* millicelsius */
|
||||
hysteresis = <2000>; /* millicelsius */
|
||||
type = "passive";
|
||||
};
|
||||
cpu_alert_almost_hot: cpu_alert_almost_hot {
|
||||
temperature = <80000>; /* millicelsius */
|
||||
hysteresis = <2000>; /* millicelsius */
|
||||
type = "passive";
|
||||
};
|
||||
cpu_alert_hot: cpu_alert_hot {
|
||||
temperature = <82000>; /* millicelsius */
|
||||
hysteresis = <2000>; /* millicelsius */
|
||||
type = "passive";
|
||||
};
|
||||
cpu_alert_hotter: cpu_alert_hotter {
|
||||
temperature = <84000>; /* millicelsius */
|
||||
hysteresis = <2000>; /* millicelsius */
|
||||
type = "passive";
|
||||
};
|
||||
cpu_alert_very_hot: cpu_alert_very_hot {
|
||||
temperature = <85000>; /* millicelsius */
|
||||
hysteresis = <2000>; /* millicelsius */
|
||||
type = "passive";
|
||||
};
|
||||
cpu_crit: cpu_crit {
|
||||
temperature = <90000>; /* millicelsius */
|
||||
hysteresis = <2000>; /* millicelsius */
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
/*
|
||||
* After 1st level, throttle the CPU down to as low as 1.4 GHz
|
||||
* and don't let the GPU go faster than 400 MHz. Note that we
|
||||
* won't throttle the GPU lower than 400 MHz due to CPU
|
||||
* heat--we'll let the GPU do the rest itself.
|
||||
*/
|
||||
cpu_warm_limit_cpu {
|
||||
trip = <&cpu_alert_warm>;
|
||||
cooling-device =
|
||||
<&cpu0 THERMAL_NO_LIMIT 4>;
|
||||
};
|
||||
|
||||
/*
|
||||
* Add some discrete steps to help throttling system deal
|
||||
* with the fact that there are two passive cooling devices:
|
||||
* the CPU and the GPU.
|
||||
*
|
||||
* - 1.2 GHz - 1.0 GHz (almost hot)
|
||||
* - 800 MHz (hot)
|
||||
* - 800 MHz - 696 MHz (hotter)
|
||||
* - 696 MHz - min (very hot)
|
||||
*
|
||||
* Note:
|
||||
* - 800 MHz appears to be a "sweet spot" for me. I can run
|
||||
* some pretty serious workload here and be happy.
|
||||
* - After 696 MHz we stop lowering voltage, so throttling
|
||||
* past there is less effective.
|
||||
*/
|
||||
cpu_almost_hot_limit_cpu {
|
||||
trip = <&cpu_alert_almost_hot>;
|
||||
cooling-device =
|
||||
<&cpu0 5 6>;
|
||||
};
|
||||
cpu_hot_limit_cpu {
|
||||
trip = <&cpu_alert_hot>;
|
||||
cooling-device =
|
||||
<&cpu0 7 7>;
|
||||
};
|
||||
cpu_hotter_limit_cpu {
|
||||
trip = <&cpu_alert_hotter>;
|
||||
cooling-device =
|
||||
<&cpu0 7 8>;
|
||||
};
|
||||
cpu_very_hot_limit_cpu {
|
||||
trip = <&cpu_alert_very_hot>;
|
||||
cooling-device =
|
||||
<&cpu0 8 THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&emmc {
|
||||
/delete-property/mmc-hs200-1_8v;
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&i2s {
|
||||
status = "okay";
|
||||
clock-names = "i2s_hclk", "i2s_clk", "i2s_clk_out";
|
||||
clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>, <&cru SCLK_I2S0_OUT>;
|
||||
};
|
||||
|
||||
&rk808 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
|
||||
dvs-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>,
|
||||
<&gpio7 15 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
/delete-property/ vcc6-supply;
|
||||
/delete-property/ vcc12-supply;
|
||||
|
||||
vcc11-supply = <&vcc33_sys>;
|
||||
|
||||
regulators {
|
||||
/* vcc33_io is sourced directly from vcc33_sys */
|
||||
/delete-node/ LDO_REG1;
|
||||
/delete-node/ LDO_REG7;
|
||||
|
||||
/* This is not a pwren anymore, but the real power supply */
|
||||
vdd10_lcd: LDO_REG7 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-name = "vdd10_lcd";
|
||||
regulator-suspend-mem-disabled;
|
||||
};
|
||||
|
||||
vcc18_lcd: LDO_REG8 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcc18_lcd";
|
||||
regulator-suspend-mem-disabled;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
hdmi {
|
||||
power_hdmi_on: power-hdmi-on {
|
||||
rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
dvs_1: dvs-1 {
|
||||
rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
|
||||
dvs_2: dvs-2 {
|
||||
rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&usb_host1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&vcc50_hdmi {
|
||||
enable-active-high;
|
||||
gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&power_hdmi_on>;
|
||||
};
|
||||
|
|
@ -121,6 +121,18 @@
|
|||
clock-frequency = <400000>;
|
||||
i2c-scl-falling-time-ns = <50>;
|
||||
i2c-scl-rising-time-ns = <300>;
|
||||
|
||||
touchscreen@10 {
|
||||
compatible = "elan,ekth3500";
|
||||
reg = <0x10>;
|
||||
interrupt-parent = <&gpio2>;
|
||||
interrupts = <14 IRQ_TYPE_EDGE_FALLING>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&touch_int &touch_rst>;
|
||||
reset-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
|
||||
vcc33-supply = <&vcc33_touch>;
|
||||
vccio-supply = <&vcc33_touch>;
|
||||
};
|
||||
};
|
||||
|
||||
&rk808 {
|
||||
|
|
|
|||
|
|
@ -88,6 +88,14 @@
|
|||
};
|
||||
};
|
||||
|
||||
&cpu_alert0 {
|
||||
temperature = <65000>;
|
||||
};
|
||||
|
||||
&cpu_alert1 {
|
||||
temperature = <70000>;
|
||||
};
|
||||
|
||||
&rk808 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int_l>;
|
||||
|
|
|
|||
|
|
@ -340,6 +340,11 @@
|
|||
i2c-scl-rising-time-ns = <1000>;
|
||||
};
|
||||
|
||||
&power {
|
||||
assigned-clocks = <&cru SCLK_EDP_24M>;
|
||||
assigned-clock-parents = <&xin24m>;
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -53,6 +53,7 @@
|
|||
interrupt-parent = <&gic>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gmac;
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
i2c2 = &i2c2;
|
||||
|
|
@ -777,9 +778,23 @@
|
|||
clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2s0_bus>;
|
||||
rockchip,playback-channels = <8>;
|
||||
rockchip,capture-channels = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
crypto: cypto-controller@ff8a0000 {
|
||||
compatible = "rockchip,rk3288-crypto";
|
||||
reg = <0xff8a0000 0x4000>;
|
||||
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
|
||||
<&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>;
|
||||
clock-names = "aclk", "hclk", "sclk", "apb_pclk";
|
||||
resets = <&cru SRST_CRYPTO>;
|
||||
reset-names = "crypto-rst";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
vopb: vop@ff930000 {
|
||||
compatible = "rockchip,rk3288-vop";
|
||||
reg = <0xff930000 0x19c>;
|
||||
|
|
|
|||
|
|
@ -49,6 +49,7 @@
|
|||
interrupt-parent = <&gic>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &emac;
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
i2c2 = &i2c2;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,193 @@
|
|||
/*
|
||||
* Copyright (c) 2015 Rockchip Electronics Co. Ltd.
|
||||
* Author: Xing Zheng <zhengxing@rock-chips.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H
|
||||
#define _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H
|
||||
|
||||
/* core clocks */
|
||||
#define PLL_APLL 1
|
||||
#define PLL_DPLL 2
|
||||
#define PLL_GPLL 3
|
||||
#define ARMCLK 4
|
||||
|
||||
/* sclk gates (special clocks) */
|
||||
#define SCLK_GPU 64
|
||||
#define SCLK_SPI 65
|
||||
#define SCLK_SDMMC 68
|
||||
#define SCLK_SDIO 69
|
||||
#define SCLK_EMMC 71
|
||||
#define SCLK_NANDC 76
|
||||
#define SCLK_UART0 77
|
||||
#define SCLK_UART1 78
|
||||
#define SCLK_UART2 79
|
||||
#define SCLK_I2S 82
|
||||
#define SCLK_SPDIF 83
|
||||
#define SCLK_TIMER0 85
|
||||
#define SCLK_TIMER1 86
|
||||
#define SCLK_TIMER2 87
|
||||
#define SCLK_TIMER3 88
|
||||
#define SCLK_OTGPHY0 93
|
||||
#define SCLK_LCDC 100
|
||||
#define SCLK_HDMI 109
|
||||
#define SCLK_HEVC 111
|
||||
#define SCLK_I2S_OUT 113
|
||||
#define SCLK_SDMMC_DRV 114
|
||||
#define SCLK_SDIO_DRV 115
|
||||
#define SCLK_EMMC_DRV 117
|
||||
#define SCLK_SDMMC_SAMPLE 118
|
||||
#define SCLK_SDIO_SAMPLE 119
|
||||
#define SCLK_EMMC_SAMPLE 121
|
||||
#define SCLK_PVTM_CORE 123
|
||||
#define SCLK_PVTM_GPU 124
|
||||
#define SCLK_PVTM_VIDEO 125
|
||||
#define SCLK_MAC 151
|
||||
#define SCLK_MACREF 152
|
||||
#define SCLK_SFC 160
|
||||
|
||||
/* aclk gates */
|
||||
#define ACLK_DMAC2 194
|
||||
#define ACLK_LCDC 197
|
||||
#define ACLK_VIO 203
|
||||
#define ACLK_VCODEC 208
|
||||
#define ACLK_CPU 209
|
||||
#define ACLK_PERI 210
|
||||
|
||||
/* pclk gates */
|
||||
#define PCLK_GPIO0 320
|
||||
#define PCLK_GPIO1 321
|
||||
#define PCLK_GPIO2 322
|
||||
#define PCLK_GRF 329
|
||||
#define PCLK_I2C0 332
|
||||
#define PCLK_I2C1 333
|
||||
#define PCLK_I2C2 334
|
||||
#define PCLK_SPI 338
|
||||
#define PCLK_UART0 341
|
||||
#define PCLK_UART1 342
|
||||
#define PCLK_UART2 343
|
||||
#define PCLK_PWM 350
|
||||
#define PCLK_TIMER 353
|
||||
#define PCLK_HDMI 360
|
||||
#define PCLK_CPU 362
|
||||
#define PCLK_PERI 363
|
||||
#define PCLK_DDRUPCTL 364
|
||||
#define PCLK_WDT 368
|
||||
#define PCLK_ACODEC 369
|
||||
|
||||
/* hclk gates */
|
||||
#define HCLK_OTG0 449
|
||||
#define HCLK_OTG1 450
|
||||
#define HCLK_NANDC 453
|
||||
#define HCLK_SDMMC 456
|
||||
#define HCLK_SDIO 457
|
||||
#define HCLK_EMMC 459
|
||||
#define HCLK_I2S 462
|
||||
#define HCLK_LCDC 465
|
||||
#define HCLK_ROM 467
|
||||
#define HCLK_VIO_BUS 472
|
||||
#define HCLK_VCODEC 476
|
||||
#define HCLK_CPU 477
|
||||
#define HCLK_PERI 478
|
||||
|
||||
#define CLK_NR_CLKS (HCLK_PERI + 1)
|
||||
|
||||
/* soft-reset indices */
|
||||
#define SRST_CORE0 0
|
||||
#define SRST_CORE1 1
|
||||
#define SRST_CORE0_DBG 4
|
||||
#define SRST_CORE1_DBG 5
|
||||
#define SRST_CORE0_POR 8
|
||||
#define SRST_CORE1_POR 9
|
||||
#define SRST_L2C 12
|
||||
#define SRST_TOPDBG 13
|
||||
#define SRST_STRC_SYS_A 14
|
||||
#define SRST_PD_CORE_NIU 15
|
||||
|
||||
#define SRST_TIMER2 16
|
||||
#define SRST_CPUSYS_H 17
|
||||
#define SRST_AHB2APB_H 19
|
||||
#define SRST_TIMER3 20
|
||||
#define SRST_INTMEM 21
|
||||
#define SRST_ROM 22
|
||||
#define SRST_PERI_NIU 23
|
||||
#define SRST_I2S 24
|
||||
#define SRST_DDR_PLL 25
|
||||
#define SRST_GPU_DLL 26
|
||||
#define SRST_TIMER0 27
|
||||
#define SRST_TIMER1 28
|
||||
#define SRST_CORE_DLL 29
|
||||
#define SRST_EFUSE_P 30
|
||||
#define SRST_ACODEC_P 31
|
||||
|
||||
#define SRST_GPIO0 32
|
||||
#define SRST_GPIO1 33
|
||||
#define SRST_GPIO2 34
|
||||
#define SRST_UART0 39
|
||||
#define SRST_UART1 40
|
||||
#define SRST_UART2 41
|
||||
#define SRST_I2C0 43
|
||||
#define SRST_I2C1 44
|
||||
#define SRST_I2C2 45
|
||||
#define SRST_SFC 47
|
||||
|
||||
#define SRST_PWM0 48
|
||||
#define SRST_DAP 51
|
||||
#define SRST_DAP_SYS 52
|
||||
#define SRST_GRF 55
|
||||
#define SRST_PERIPHSYS_A 57
|
||||
#define SRST_PERIPHSYS_H 58
|
||||
#define SRST_PERIPHSYS_P 59
|
||||
#define SRST_CPU_PERI 61
|
||||
#define SRST_EMEM_PERI 62
|
||||
#define SRST_USB_PERI 63
|
||||
|
||||
#define SRST_DMA2 64
|
||||
#define SRST_MAC 66
|
||||
#define SRST_NANDC 68
|
||||
#define SRST_USBOTG0 69
|
||||
#define SRST_OTGC0 71
|
||||
#define SRST_USBOTG1 72
|
||||
#define SRST_OTGC1 74
|
||||
#define SRST_DDRMSCH 79
|
||||
|
||||
#define SRST_MMC0 81
|
||||
#define SRST_SDIO 82
|
||||
#define SRST_EMMC 83
|
||||
#define SRST_SPI0 84
|
||||
#define SRST_WDT 86
|
||||
#define SRST_DDRPHY 88
|
||||
#define SRST_DDRPHY_P 89
|
||||
#define SRST_DDRCTRL 90
|
||||
#define SRST_DDRCTRL_P 91
|
||||
|
||||
#define SRST_HDMI_P 96
|
||||
#define SRST_VIO_BUS_H 99
|
||||
#define SRST_UTMI0 103
|
||||
#define SRST_UTMI1 104
|
||||
#define SRST_USBPOR 105
|
||||
|
||||
#define SRST_VCODEC_A 112
|
||||
#define SRST_VCODEC_H 113
|
||||
#define SRST_VIO1_A 114
|
||||
#define SRST_HEVC 115
|
||||
#define SRST_VCODEC_NIU_A 116
|
||||
#define SRST_LCDC1_A 117
|
||||
#define SRST_LCDC1_H 118
|
||||
#define SRST_LCDC1_D 119
|
||||
#define SRST_GPU 120
|
||||
#define SRST_GPU_NIU_A 122
|
||||
|
||||
#define SRST_DBG_P 131
|
||||
|
||||
#endif
|
||||
|
|
@ -86,6 +86,7 @@
|
|||
#define SCLK_USBPHY480M_SRC 122
|
||||
#define SCLK_PVTM_CORE 123
|
||||
#define SCLK_PVTM_GPU 124
|
||||
#define SCLK_CRYPTO 125
|
||||
|
||||
#define SCLK_MAC 151
|
||||
#define SCLK_MACREF_OUT 152
|
||||
|
|
|
|||
Загрузка…
Ссылка в новой задаче