iio: adc: ad7768-1: Add support for setting the sampling frequency
The AD7768-1 core ADC receives a master clock signal (MCLK). The MCLK frequency combined with the MCLK division and the digital filter decimation rates, determines the sampling frequency. Along with MCLK_DIV, the power mode is also configured according to datasheet recommendations. From user space, available sampling frequencies can be read. However, it is not required for an exact value to be entered, since the driver will look for the closest available match. When the device configuration changes (for example, if the filter decimation rate changes), a SYNC_IN pulse is required. Signed-off-by: Stefan Popa <stefan.popa@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
This commit is contained in:
Stefan Popa
Jonathan Cameron
Родитель
cbd5dd387a
Коммит
e9517dffd1
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@ -9,6 +9,7 @@
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/gpio/consumer.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/regulator/consumer.h>
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@ -59,6 +60,18 @@
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#define AD7768_REG_DIG_DIAG_STATUS 0x30
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#define AD7768_REG_MCLK_COUNTER 0x31
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/* AD7768_REG_POWER_CLOCK */
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#define AD7768_PWR_MCLK_DIV_MSK GENMASK(5, 4)
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#define AD7768_PWR_MCLK_DIV(x) FIELD_PREP(AD7768_PWR_MCLK_DIV_MSK, x)
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#define AD7768_PWR_PWRMODE_MSK GENMASK(1, 0)
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#define AD7768_PWR_PWRMODE(x) FIELD_PREP(AD7768_PWR_PWRMODE_MSK, x)
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/* AD7768_REG_DIGITAL_FILTER */
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#define AD7768_DIG_FIL_FIL_MSK GENMASK(6, 4)
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#define AD7768_DIG_FIL_FIL(x) FIELD_PREP(AD7768_DIG_FIL_FIL_MSK, x)
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#define AD7768_DIG_FIL_DEC_MSK GENMASK(2, 0)
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#define AD7768_DIG_FIL_DEC_RATE(x) FIELD_PREP(AD7768_DIG_FIL_DEC_MSK, x)
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/* AD7768_REG_CONVERSION */
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#define AD7768_CONV_MODE_MSK GENMASK(2, 0)
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#define AD7768_CONV_MODE(x) FIELD_PREP(AD7768_CONV_MODE_MSK, x)
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@ -80,11 +93,51 @@ enum ad7768_pwrmode {
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AD7768_FAST_MODE = 3
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};
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enum ad7768_mclk_div {
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AD7768_MCLK_DIV_16,
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AD7768_MCLK_DIV_8,
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AD7768_MCLK_DIV_4,
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AD7768_MCLK_DIV_2
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};
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enum ad7768_dec_rate {
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AD7768_DEC_RATE_32 = 0,
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AD7768_DEC_RATE_64 = 1,
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AD7768_DEC_RATE_128 = 2,
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AD7768_DEC_RATE_256 = 3,
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AD7768_DEC_RATE_512 = 4,
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AD7768_DEC_RATE_1024 = 5,
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AD7768_DEC_RATE_8 = 9,
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AD7768_DEC_RATE_16 = 10
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};
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struct ad7768_clk_configuration {
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enum ad7768_mclk_div mclk_div;
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enum ad7768_dec_rate dec_rate;
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unsigned int clk_div;
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enum ad7768_pwrmode pwrmode;
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};
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static const struct ad7768_clk_configuration ad7768_clk_config[] = {
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{ AD7768_MCLK_DIV_2, AD7768_DEC_RATE_8, 16, AD7768_FAST_MODE },
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{ AD7768_MCLK_DIV_2, AD7768_DEC_RATE_16, 32, AD7768_FAST_MODE },
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{ AD7768_MCLK_DIV_2, AD7768_DEC_RATE_32, 64, AD7768_FAST_MODE },
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{ AD7768_MCLK_DIV_2, AD7768_DEC_RATE_64, 128, AD7768_FAST_MODE },
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{ AD7768_MCLK_DIV_2, AD7768_DEC_RATE_128, 256, AD7768_FAST_MODE },
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{ AD7768_MCLK_DIV_4, AD7768_DEC_RATE_128, 512, AD7768_MED_MODE },
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{ AD7768_MCLK_DIV_4, AD7768_DEC_RATE_256, 1024, AD7768_MED_MODE },
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{ AD7768_MCLK_DIV_4, AD7768_DEC_RATE_512, 2048, AD7768_MED_MODE },
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{ AD7768_MCLK_DIV_4, AD7768_DEC_RATE_1024, 4096, AD7768_MED_MODE },
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{ AD7768_MCLK_DIV_8, AD7768_DEC_RATE_1024, 8192, AD7768_MED_MODE },
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{ AD7768_MCLK_DIV_16, AD7768_DEC_RATE_1024, 16384, AD7768_ECO_MODE },
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};
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static const struct iio_chan_spec ad7768_channels[] = {
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{
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.type = IIO_VOLTAGE,
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
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.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
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.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
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.indexed = 1,
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.channel = 0,
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.scan_index = 0,
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@ -102,8 +155,12 @@ struct ad7768_state {
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struct spi_device *spi;
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struct regulator *vref;
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struct mutex lock;
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struct clk *mclk;
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unsigned int mclk_freq;
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unsigned int samp_freq;
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struct completion completion;
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struct iio_trigger *trig;
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struct gpio_desc *gpio_sync_in;
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/*
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* DMA (thus cache coherency maintenance) requires the
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* transfer buffers to live in their own cache lines.
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@ -210,6 +267,90 @@ err_unlock:
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return ret;
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}
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static int ad7768_set_dig_fil(struct ad7768_state *st,
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enum ad7768_dec_rate dec_rate)
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{
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unsigned int mode;
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int ret;
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if (dec_rate == AD7768_DEC_RATE_8 || dec_rate == AD7768_DEC_RATE_16)
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mode = AD7768_DIG_FIL_FIL(dec_rate);
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else
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mode = AD7768_DIG_FIL_DEC_RATE(dec_rate);
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ret = ad7768_spi_reg_write(st, AD7768_REG_DIGITAL_FILTER, mode);
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if (ret < 0)
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return ret;
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/* A sync-in pulse is required every time the filter dec rate changes */
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gpiod_set_value(st->gpio_sync_in, 1);
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gpiod_set_value(st->gpio_sync_in, 0);
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return 0;
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}
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static int ad7768_set_freq(struct ad7768_state *st,
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unsigned int freq)
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{
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unsigned int diff_new, diff_old, pwr_mode, i, idx;
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int res, ret;
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diff_old = U32_MAX;
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idx = 0;
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res = DIV_ROUND_CLOSEST(st->mclk_freq, freq);
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/* Find the closest match for the desired sampling frequency */
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for (i = 0; i < ARRAY_SIZE(ad7768_clk_config); i++) {
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diff_new = abs(res - ad7768_clk_config[i].clk_div);
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if (diff_new < diff_old) {
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diff_old = diff_new;
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idx = i;
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}
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}
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/*
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* Set both the mclk_div and pwrmode with a single write to the
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* POWER_CLOCK register
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*/
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pwr_mode = AD7768_PWR_MCLK_DIV(ad7768_clk_config[idx].mclk_div) |
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AD7768_PWR_PWRMODE(ad7768_clk_config[idx].pwrmode);
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ret = ad7768_spi_reg_write(st, AD7768_REG_POWER_CLOCK, pwr_mode);
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if (ret < 0)
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return ret;
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ret = ad7768_set_dig_fil(st, ad7768_clk_config[idx].dec_rate);
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if (ret < 0)
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return ret;
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st->samp_freq = DIV_ROUND_CLOSEST(st->mclk_freq,
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ad7768_clk_config[idx].clk_div);
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return 0;
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}
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static ssize_t ad7768_sampling_freq_avail(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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struct iio_dev *indio_dev = dev_to_iio_dev(dev);
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struct ad7768_state *st = iio_priv(indio_dev);
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unsigned int freq;
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int i, len = 0;
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for (i = 0; i < ARRAY_SIZE(ad7768_clk_config); i++) {
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freq = DIV_ROUND_CLOSEST(st->mclk_freq,
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ad7768_clk_config[i].clk_div);
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len += scnprintf(buf + len, PAGE_SIZE - len, "%d ", freq);
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}
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buf[len - 1] = '\n';
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return len;
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}
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static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(ad7768_sampling_freq_avail);
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static int ad7768_read_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int *val, int *val2, long info)
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@ -242,13 +383,43 @@ static int ad7768_read_raw(struct iio_dev *indio_dev,
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*val2 = chan->scan_type.realbits;
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return IIO_VAL_FRACTIONAL_LOG2;
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case IIO_CHAN_INFO_SAMP_FREQ:
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*val = st->samp_freq;
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return IIO_VAL_INT;
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}
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return -EINVAL;
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}
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static int ad7768_write_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int val, int val2, long info)
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{
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struct ad7768_state *st = iio_priv(indio_dev);
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switch (info) {
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case IIO_CHAN_INFO_SAMP_FREQ:
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return ad7768_set_freq(st, val);
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default:
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return -EINVAL;
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}
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}
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static struct attribute *ad7768_attributes[] = {
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&iio_dev_attr_sampling_frequency_available.dev_attr.attr,
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NULL
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};
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static const struct attribute_group ad7768_group = {
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.attrs = ad7768_attributes,
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};
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static const struct iio_info ad7768_info = {
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.attrs = &ad7768_group,
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.read_raw = &ad7768_read_raw,
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.write_raw = &ad7768_write_raw,
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.debugfs_reg_access = &ad7768_reg_access,
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};
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@ -270,9 +441,13 @@ static int ad7768_setup(struct ad7768_state *st)
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if (ret)
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return ret;
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/* Set power mode to fast */
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return ad7768_spi_reg_write(st, AD7768_REG_POWER_CLOCK,
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AD7768_FAST_MODE);
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st->gpio_sync_in = devm_gpiod_get(&st->spi->dev, "adi,sync-in",
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GPIOD_OUT_LOW);
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if (IS_ERR(st->gpio_sync_in))
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return PTR_ERR(st->gpio_sync_in);
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/* Set the default sampling frequency to 32000 kSPS */
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return ad7768_set_freq(st, 32000);
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}
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static irqreturn_t ad7768_trigger_handler(int irq, void *p)
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@ -356,6 +531,13 @@ static void ad7768_regulator_disable(void *data)
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regulator_disable(st->vref);
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}
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static void ad7768_clk_disable(void *data)
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{
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struct ad7768_state *st = data;
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clk_disable_unprepare(st->mclk);
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}
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static int ad7768_probe(struct spi_device *spi)
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{
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struct ad7768_state *st;
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@ -383,6 +565,20 @@ static int ad7768_probe(struct spi_device *spi)
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if (ret)
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return ret;
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st->mclk = devm_clk_get(&spi->dev, "mclk");
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if (IS_ERR(st->mclk))
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return PTR_ERR(st->mclk);
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ret = clk_prepare_enable(st->mclk);
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if (ret < 0)
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return ret;
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ret = devm_add_action_or_reset(&spi->dev, ad7768_clk_disable, st);
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if (ret)
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return ret;
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st->mclk_freq = clk_get_rate(st->mclk);
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spi_set_drvdata(spi, indio_dev);
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mutex_init(&st->lock);
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