s390/pci: provide support for CPU directed interrupts
Up until now all interrupts on s390 have been floating. For MSI interrupts we've used a global summary bit vector (with a bit for each function) and a per-function interrupt bit vector (with a bit per MSI). This patch introduces a new IRQ delivery mode: CPU directed interrupts. In this new mode a per-CPU interrupt bit vector is used (with a bit per MSI per function). Further it is now possible to direct an IRQ to a specific CPU so we can finally support IRQ affinity. If an interrupt can't be delivered because the appointed CPU is occupied by a hypervisor the interrupt is delivered floating. For this a global summary bit vector is used (with a bit per CPU). Signed-off-by: Sebastian Ott <sebott@linux.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
This commit is contained in:
Sebastian Ott
Martin Schwidefsky
Родитель
414cbd1e3d
Коммит
e979ce7bce
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@ -115,6 +115,8 @@ struct zpci_dev {
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/* IRQ stuff */
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u64 msi_addr; /* MSI address */
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unsigned int max_msi; /* maximum number of MSI's */
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unsigned int msi_first_bit;
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unsigned int msi_nr_irqs;
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struct airq_iv *aibv; /* adapter interrupt bit vector */
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unsigned long aisb; /* number of the summary bit */
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@ -118,7 +118,11 @@ struct clp_rsp_query_pci_grp {
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u8 refresh : 1; /* TLB refresh mode */
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u16 reserved2;
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u16 mui;
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u64 reserved3;
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u16 : 16;
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u16 maxfaal;
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u16 : 4;
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u16 dnoi : 12;
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u16 maxcpu;
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u64 dasm; /* dma address space mask */
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u64 msia; /* MSI address */
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u64 reserved4;
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@ -38,6 +38,8 @@
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#define ZPCI_MOD_FC_RESET_ERROR 7
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#define ZPCI_MOD_FC_RESET_BLOCK 9
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#define ZPCI_MOD_FC_SET_MEASURE 10
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#define ZPCI_MOD_FC_REG_INT_D 16
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#define ZPCI_MOD_FC_DEREG_INT_D 17
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/* FIB function controls */
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#define ZPCI_FIB_FC_ENABLED 0x80
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@ -51,16 +53,7 @@
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#define ZPCI_FIB_FC_LS_BLOCKED 0x20
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#define ZPCI_FIB_FC_DMAAS_REG 0x10
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/* Function Information Block */
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struct zpci_fib {
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u32 fmt : 8; /* format */
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u32 : 24;
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u32 : 32;
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u8 fc; /* function controls */
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u64 : 56;
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u64 pba; /* PCI base address */
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u64 pal; /* PCI address limit */
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u64 iota; /* I/O Translation Anchor */
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struct zpci_fib_fmt0 {
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u32 : 1;
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u32 isc : 3; /* Interrupt subclass */
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u32 noi : 12; /* Number of interrupts */
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@ -72,16 +65,75 @@ struct zpci_fib {
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u32 : 32;
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u64 aibv; /* Adapter int bit vector address */
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u64 aisb; /* Adapter int summary bit address */
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};
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struct zpci_fib_fmt1 {
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u32 : 4;
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u32 noi : 12;
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u32 : 16;
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u32 dibvo : 16;
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u32 : 16;
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u64 : 64;
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u64 : 64;
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};
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/* Function Information Block */
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struct zpci_fib {
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u32 fmt : 8; /* format */
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u32 : 24;
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u32 : 32;
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u8 fc; /* function controls */
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u64 : 56;
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u64 pba; /* PCI base address */
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u64 pal; /* PCI address limit */
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u64 iota; /* I/O Translation Anchor */
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union {
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struct zpci_fib_fmt0 fmt0;
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struct zpci_fib_fmt1 fmt1;
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};
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u64 fmb_addr; /* Function measurement block address and key */
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u32 : 32;
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u32 gd;
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} __packed __aligned(8);
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/* directed interruption information block */
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struct zpci_diib {
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u32 : 1;
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u32 isc : 3;
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u32 : 28;
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u16 : 16;
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u16 nr_cpus;
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u64 disb_addr;
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u64 : 64;
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u64 : 64;
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} __packed __aligned(8);
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/* cpu directed interruption information block */
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struct zpci_cdiib {
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u64 : 64;
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u64 dibv_addr;
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u64 : 64;
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u64 : 64;
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u64 : 64;
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} __packed __aligned(8);
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union zpci_sic_iib {
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struct zpci_diib diib;
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struct zpci_cdiib cdiib;
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};
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u8 zpci_mod_fc(u64 req, struct zpci_fib *fib, u8 *status);
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int zpci_refresh_trans(u64 fn, u64 addr, u64 range);
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int zpci_load(u64 *data, u64 req, u64 offset);
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int zpci_store(u64 data, u64 req, u64 offset);
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int zpci_store_block(const u64 *data, u64 req, u64 offset);
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int zpci_set_irq_ctrl(u16 ctl, char *unused, u8 isc);
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int __zpci_set_irq_ctrl(u16 ctl, u8 isc, union zpci_sic_iib *iib);
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static inline int zpci_set_irq_ctrl(u16 ctl, u8 isc)
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{
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union zpci_sic_iib iib = {{0}};
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return __zpci_set_irq_ctrl(ctl, isc, &iib);
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}
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#endif
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@ -96,13 +96,15 @@ int zpci_refresh_trans(u64 fn, u64 addr, u64 range)
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}
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/* Set Interruption Controls */
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int zpci_set_irq_ctrl(u16 ctl, char *unused, u8 isc)
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int __zpci_set_irq_ctrl(u16 ctl, u8 isc, union zpci_sic_iib *iib)
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{
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if (!test_facility(72))
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return -EIO;
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asm volatile (
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" .insn rsy,0xeb00000000d1,%[ctl],%[isc],%[u]\n"
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: : [ctl] "d" (ctl), [isc] "d" (isc << 27), [u] "Q" (*unused));
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asm volatile(
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".insn rsy,0xeb00000000d1,%[ctl],%[isc],%[iib]\n"
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: : [ctl] "d" (ctl), [isc] "d" (isc << 27), [iib] "Q" (*iib));
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return 0;
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}
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@ -7,20 +7,31 @@
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#include <linux/kernel_stat.h>
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#include <linux/pci.h>
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#include <linux/msi.h>
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#include <linux/smp.h>
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#include <asm/isc.h>
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#include <asm/airq.h>
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static enum {FLOATING, DIRECTED} irq_delivery;
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#define SIC_IRQ_MODE_ALL 0
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#define SIC_IRQ_MODE_SINGLE 1
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#define SIC_IRQ_MODE_DIRECT 4
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#define SIC_IRQ_MODE_D_ALL 16
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#define SIC_IRQ_MODE_D_SINGLE 17
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#define SIC_IRQ_MODE_SET_CPU 18
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/*
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* summary bit vector - one summary bit per function
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* summary bit vector
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* FLOATING - summary bit per function
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* DIRECTED - summary bit per cpu (only used in fallback path)
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*/
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static struct airq_iv *zpci_sbv;
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/*
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* interrupt bit vectors - one vector per function
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* interrupt bit vectors
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* FLOATING - interrupt bit vector per function
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* DIRECTED - interrupt bit vector per cpu
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*/
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static struct airq_iv **zpci_ibv;
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@ -31,13 +42,13 @@ static int zpci_set_airq(struct zpci_dev *zdev)
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struct zpci_fib fib = {0};
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u8 status;
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fib.isc = PCI_ISC;
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fib.sum = 1; /* enable summary notifications */
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fib.noi = airq_iv_end(zdev->aibv);
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fib.aibv = (unsigned long) zdev->aibv->vector;
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fib.aibvo = 0; /* each zdev has its own interrupt vector */
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fib.aisb = (unsigned long) zpci_sbv->vector + (zdev->aisb/64)*8;
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fib.aisbo = zdev->aisb & 63;
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fib.fmt0.isc = PCI_ISC;
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fib.fmt0.sum = 1; /* enable summary notifications */
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fib.fmt0.noi = airq_iv_end(zdev->aibv);
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fib.fmt0.aibv = (unsigned long) zdev->aibv->vector;
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fib.fmt0.aibvo = 0; /* each zdev has its own interrupt vector */
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fib.fmt0.aisb = (unsigned long) zpci_sbv->vector + (zdev->aisb/64)*8;
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fib.fmt0.aisbo = zdev->aisb & 63;
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return zpci_mod_fc(req, &fib, &status) ? -EIO : 0;
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}
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@ -57,13 +68,134 @@ static int zpci_clear_airq(struct zpci_dev *zdev)
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return cc ? -EIO : 0;
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}
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/* Modify PCI: Register CPU directed interruptions */
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static int zpci_set_directed_irq(struct zpci_dev *zdev)
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{
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u64 req = ZPCI_CREATE_REQ(zdev->fh, 0, ZPCI_MOD_FC_REG_INT_D);
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struct zpci_fib fib = {0};
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u8 status;
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fib.fmt = 1;
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fib.fmt1.noi = zdev->msi_nr_irqs;
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fib.fmt1.dibvo = zdev->msi_first_bit;
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return zpci_mod_fc(req, &fib, &status) ? -EIO : 0;
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}
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/* Modify PCI: Unregister CPU directed interruptions */
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static int zpci_clear_directed_irq(struct zpci_dev *zdev)
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{
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u64 req = ZPCI_CREATE_REQ(zdev->fh, 0, ZPCI_MOD_FC_DEREG_INT_D);
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struct zpci_fib fib = {0};
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u8 cc, status;
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fib.fmt = 1;
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cc = zpci_mod_fc(req, &fib, &status);
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if (cc == 3 || (cc == 1 && status == 24))
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/* Function already gone or IRQs already deregistered. */
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cc = 0;
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return cc ? -EIO : 0;
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}
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static int zpci_set_irq_affinity(struct irq_data *data, const struct cpumask *dest,
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bool force)
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{
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struct msi_desc *entry = irq_get_msi_desc(data->irq);
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struct msi_msg msg = entry->msg;
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msg.address_lo &= 0xff0000ff;
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msg.address_lo |= (cpumask_first(dest) << 8);
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pci_write_msi_msg(data->irq, &msg);
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return IRQ_SET_MASK_OK;
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}
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static struct irq_chip zpci_irq_chip = {
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.name = "zPCI",
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.irq_unmask = pci_msi_unmask_irq,
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.irq_mask = pci_msi_mask_irq,
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.irq_set_affinity = zpci_set_irq_affinity,
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};
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static void zpci_irq_handler(struct airq_struct *airq, bool floating)
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static void zpci_handle_cpu_local_irq(bool rescan)
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{
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struct airq_iv *dibv = zpci_ibv[smp_processor_id()];
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unsigned long bit;
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int irqs_on = 0;
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for (bit = 0;;) {
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/* Scan the directed IRQ bit vector */
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bit = airq_iv_scan(dibv, bit, airq_iv_end(dibv));
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if (bit == -1UL) {
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if (!rescan || irqs_on++)
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/* End of second scan with interrupts on. */
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break;
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/* First scan complete, reenable interrupts. */
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if (zpci_set_irq_ctrl(SIC_IRQ_MODE_D_SINGLE, PCI_ISC))
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break;
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bit = 0;
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continue;
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}
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inc_irq_stat(IRQIO_MSI);
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generic_handle_irq(airq_iv_get_data(dibv, bit));
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}
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}
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struct cpu_irq_data {
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call_single_data_t csd;
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atomic_t scheduled;
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};
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static DEFINE_PER_CPU_SHARED_ALIGNED(struct cpu_irq_data, irq_data);
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static void zpci_handle_remote_irq(void *data)
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{
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atomic_t *scheduled = data;
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do {
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zpci_handle_cpu_local_irq(false);
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} while (atomic_dec_return(scheduled));
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}
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static void zpci_handle_fallback_irq(void)
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{
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struct cpu_irq_data *cpu_data;
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unsigned long cpu;
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int irqs_on = 0;
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for (cpu = 0;;) {
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cpu = airq_iv_scan(zpci_sbv, cpu, airq_iv_end(zpci_sbv));
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if (cpu == -1UL) {
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if (irqs_on++)
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/* End of second scan with interrupts on. */
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break;
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/* First scan complete, reenable interrupts. */
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if (zpci_set_irq_ctrl(SIC_IRQ_MODE_SINGLE, PCI_ISC))
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break;
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cpu = 0;
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continue;
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}
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cpu_data = &per_cpu(irq_data, cpu);
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if (atomic_inc_return(&cpu_data->scheduled) > 1)
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continue;
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cpu_data->csd.func = zpci_handle_remote_irq;
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cpu_data->csd.info = &cpu_data->scheduled;
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cpu_data->csd.flags = 0;
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smp_call_function_single_async(cpu, &cpu_data->csd);
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}
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}
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static void zpci_directed_irq_handler(struct airq_struct *airq, bool floating)
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{
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inc_irq_stat(IRQIO_PCI);
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if (floating)
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zpci_handle_fallback_irq();
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else
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zpci_handle_cpu_local_irq(true);
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}
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static void zpci_floating_irq_handler(struct airq_struct *airq, bool floating)
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{
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unsigned long si, ai;
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struct airq_iv *aibv;
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@ -78,7 +210,7 @@ static void zpci_irq_handler(struct airq_struct *airq, bool floating)
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/* End of second scan with interrupts on. */
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break;
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/* First scan complete, reenable interrupts. */
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if (zpci_set_irq_ctrl(SIC_IRQ_MODE_SINGLE, NULL, PCI_ISC))
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if (zpci_set_irq_ctrl(SIC_IRQ_MODE_SINGLE, PCI_ISC))
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break;
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si = 0;
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continue;
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@ -101,54 +233,79 @@ static void zpci_irq_handler(struct airq_struct *airq, bool floating)
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int arch_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
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{
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struct zpci_dev *zdev = to_zpci(pdev);
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unsigned int hwirq, msi_vecs;
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unsigned long aisb;
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unsigned int hwirq, msi_vecs, cpu;
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unsigned long bit;
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struct msi_desc *msi;
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struct msi_msg msg;
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int rc, irq;
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zdev->aisb = -1UL;
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zdev->msi_first_bit = -1U;
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if (type == PCI_CAP_ID_MSI && nvec > 1)
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return 1;
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msi_vecs = min_t(unsigned int, nvec, zdev->max_msi);
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/* Allocate adapter summary indicator bit */
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aisb = airq_iv_alloc_bit(zpci_sbv);
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if (aisb == -1UL)
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return -EIO;
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zdev->aisb = aisb;
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if (irq_delivery == DIRECTED) {
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/* Allocate cpu vector bits */
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bit = airq_iv_alloc(zpci_ibv[0], msi_vecs);
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if (bit == -1UL)
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return -EIO;
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} else {
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/* Allocate adapter summary indicator bit */
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bit = airq_iv_alloc_bit(zpci_sbv);
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if (bit == -1UL)
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return -EIO;
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zdev->aisb = bit;
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/* Create adapter interrupt vector */
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zdev->aibv = airq_iv_create(msi_vecs, AIRQ_IV_DATA | AIRQ_IV_BITLOCK);
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if (!zdev->aibv)
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return -ENOMEM;
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/* Create adapter interrupt vector */
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zdev->aibv = airq_iv_create(msi_vecs, AIRQ_IV_DATA | AIRQ_IV_BITLOCK);
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if (!zdev->aibv)
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return -ENOMEM;
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/* Wire up shortcut pointer */
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zpci_ibv[aisb] = zdev->aibv;
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/* Wire up shortcut pointer */
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zpci_ibv[bit] = zdev->aibv;
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/* Each function has its own interrupt vector */
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bit = 0;
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}
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/* Request MSI interrupts */
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hwirq = 0;
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hwirq = bit;
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for_each_pci_msi_entry(msi, pdev) {
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if (hwirq >= msi_vecs)
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rc = -EIO;
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if (hwirq - bit >= msi_vecs)
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break;
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irq = irq_alloc_desc(0); /* Alloc irq on node 0 */
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irq = __irq_alloc_descs(-1, 0, 1, 0, THIS_MODULE, msi->affinity);
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if (irq < 0)
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return -ENOMEM;
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rc = irq_set_msi_desc(irq, msi);
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if (rc)
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return rc;
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irq_set_chip_and_handler(irq, &zpci_irq_chip,
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handle_simple_irq);
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handle_percpu_irq);
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msg.data = hwirq;
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msg.address_lo = zdev->msi_addr & 0xffffffff;
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if (irq_delivery == DIRECTED) {
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msg.address_lo = zdev->msi_addr & 0xff0000ff;
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msg.address_lo |= msi->affinity ?
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(cpumask_first(&msi->affinity->mask) << 8) : 0;
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for_each_possible_cpu(cpu) {
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airq_iv_set_data(zpci_ibv[cpu], hwirq, irq);
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}
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} else {
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msg.address_lo = zdev->msi_addr & 0xffffffff;
|
||||
airq_iv_set_data(zdev->aibv, hwirq, irq);
|
||||
}
|
||||
msg.address_hi = zdev->msi_addr >> 32;
|
||||
pci_write_msi_msg(irq, &msg);
|
||||
airq_iv_set_data(zdev->aibv, hwirq, irq);
|
||||
hwirq++;
|
||||
}
|
||||
|
||||
/* Enable adapter interrupts */
|
||||
rc = zpci_set_airq(zdev);
|
||||
zdev->msi_first_bit = bit;
|
||||
zdev->msi_nr_irqs = msi_vecs;
|
||||
|
||||
if (irq_delivery == DIRECTED)
|
||||
rc = zpci_set_directed_irq(zdev);
|
||||
else
|
||||
rc = zpci_set_airq(zdev);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
|
|
@ -161,8 +318,11 @@ void arch_teardown_msi_irqs(struct pci_dev *pdev)
|
|||
struct msi_desc *msi;
|
||||
int rc;
|
||||
|
||||
/* Disable adapter interrupts */
|
||||
rc = zpci_clear_airq(zdev);
|
||||
/* Disable interrupts */
|
||||
if (irq_delivery == DIRECTED)
|
||||
rc = zpci_clear_directed_irq(zdev);
|
||||
else
|
||||
rc = zpci_clear_airq(zdev);
|
||||
if (rc)
|
||||
return;
|
||||
|
||||
|
|
@ -191,37 +351,114 @@ void arch_teardown_msi_irqs(struct pci_dev *pdev)
|
|||
airq_iv_release(zdev->aibv);
|
||||
zdev->aibv = NULL;
|
||||
}
|
||||
|
||||
if ((irq_delivery == DIRECTED) && zdev->msi_first_bit != -1U)
|
||||
airq_iv_free(zpci_ibv[0], zdev->msi_first_bit, zdev->msi_nr_irqs);
|
||||
}
|
||||
|
||||
static struct airq_struct zpci_airq = {
|
||||
.handler = zpci_irq_handler,
|
||||
.handler = zpci_floating_irq_handler,
|
||||
.isc = PCI_ISC,
|
||||
};
|
||||
|
||||
static void __init cpu_enable_directed_irq(void *unused)
|
||||
{
|
||||
union zpci_sic_iib iib = {{0}};
|
||||
|
||||
iib.cdiib.dibv_addr = (u64) zpci_ibv[smp_processor_id()]->vector;
|
||||
|
||||
__zpci_set_irq_ctrl(SIC_IRQ_MODE_SET_CPU, 0, &iib);
|
||||
zpci_set_irq_ctrl(SIC_IRQ_MODE_D_SINGLE, PCI_ISC);
|
||||
}
|
||||
|
||||
static int __init zpci_directed_irq_init(void)
|
||||
{
|
||||
union zpci_sic_iib iib = {{0}};
|
||||
unsigned int cpu;
|
||||
|
||||
zpci_sbv = airq_iv_create(num_possible_cpus(), 0);
|
||||
if (!zpci_sbv)
|
||||
return -ENOMEM;
|
||||
|
||||
iib.diib.isc = PCI_ISC;
|
||||
iib.diib.nr_cpus = num_possible_cpus();
|
||||
iib.diib.disb_addr = (u64) zpci_sbv->vector;
|
||||
__zpci_set_irq_ctrl(SIC_IRQ_MODE_DIRECT, 0, &iib);
|
||||
|
||||
zpci_ibv = kcalloc(num_possible_cpus(), sizeof(*zpci_ibv),
|
||||
GFP_KERNEL);
|
||||
if (!zpci_ibv)
|
||||
return -ENOMEM;
|
||||
|
||||
for_each_possible_cpu(cpu) {
|
||||
/*
|
||||
* Per CPU IRQ vectors look the same but bit-allocation
|
||||
* is only done on the first vector.
|
||||
*/
|
||||
zpci_ibv[cpu] = airq_iv_create(cache_line_size() * BITS_PER_BYTE,
|
||||
AIRQ_IV_DATA |
|
||||
AIRQ_IV_CACHELINE |
|
||||
(!cpu ? AIRQ_IV_ALLOC : 0));
|
||||
if (!zpci_ibv[cpu])
|
||||
return -ENOMEM;
|
||||
}
|
||||
on_each_cpu(cpu_enable_directed_irq, NULL, 1);
|
||||
|
||||
zpci_irq_chip.irq_set_affinity = zpci_set_irq_affinity;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init zpci_floating_irq_init(void)
|
||||
{
|
||||
zpci_ibv = kcalloc(ZPCI_NR_DEVICES, sizeof(*zpci_ibv), GFP_KERNEL);
|
||||
if (!zpci_ibv)
|
||||
return -ENOMEM;
|
||||
|
||||
zpci_sbv = airq_iv_create(ZPCI_NR_DEVICES, AIRQ_IV_ALLOC);
|
||||
if (!zpci_sbv)
|
||||
goto out_free;
|
||||
|
||||
return 0;
|
||||
|
||||
out_free:
|
||||
kfree(zpci_ibv);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
int __init zpci_irq_init(void)
|
||||
{
|
||||
int rc;
|
||||
|
||||
irq_delivery = sclp.has_dirq ? DIRECTED : FLOATING;
|
||||
if (irq_delivery == DIRECTED)
|
||||
zpci_airq.handler = zpci_directed_irq_handler;
|
||||
|
||||
rc = register_adapter_interrupt(&zpci_airq);
|
||||
if (rc)
|
||||
goto out;
|
||||
/* Set summary to 1 to be called every time for the ISC. */
|
||||
*zpci_airq.lsi_ptr = 1;
|
||||
|
||||
rc = -ENOMEM;
|
||||
zpci_ibv = kcalloc(ZPCI_NR_DEVICES, sizeof(*zpci_ibv), GFP_KERNEL);
|
||||
if (!zpci_ibv)
|
||||
switch (irq_delivery) {
|
||||
case FLOATING:
|
||||
rc = zpci_floating_irq_init();
|
||||
break;
|
||||
case DIRECTED:
|
||||
rc = zpci_directed_irq_init();
|
||||
break;
|
||||
}
|
||||
|
||||
if (rc)
|
||||
goto out_airq;
|
||||
|
||||
zpci_sbv = airq_iv_create(ZPCI_NR_DEVICES, AIRQ_IV_ALLOC);
|
||||
if (!zpci_sbv)
|
||||
goto out_free;
|
||||
/*
|
||||
* Enable floating IRQs (with suppression after one IRQ). When using
|
||||
* directed IRQs this enables the fallback path.
|
||||
*/
|
||||
zpci_set_irq_ctrl(SIC_IRQ_MODE_SINGLE, PCI_ISC);
|
||||
|
||||
zpci_set_irq_ctrl(SIC_IRQ_MODE_SINGLE, NULL, PCI_ISC);
|
||||
return 0;
|
||||
|
||||
out_free:
|
||||
kfree(zpci_ibv);
|
||||
out_airq:
|
||||
unregister_adapter_interrupt(&zpci_airq);
|
||||
out:
|
||||
|
|
@ -230,7 +467,15 @@ out:
|
|||
|
||||
void __init zpci_irq_exit(void)
|
||||
{
|
||||
airq_iv_release(zpci_sbv);
|
||||
unsigned int cpu;
|
||||
|
||||
if (irq_delivery == DIRECTED) {
|
||||
for_each_possible_cpu(cpu) {
|
||||
airq_iv_release(zpci_ibv[cpu]);
|
||||
}
|
||||
}
|
||||
kfree(zpci_ibv);
|
||||
if (zpci_sbv)
|
||||
airq_iv_release(zpci_sbv);
|
||||
unregister_adapter_interrupt(&zpci_airq);
|
||||
}
|
||||
|
|
|
|||
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