clk: sunxi-ng: Add divider
Add support for the various dividers (linear, table or pow-of-two based) found in the CCU. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20160629190535.11855-8-maxime.ripard@free-electrons.com
This commit is contained in:
Maxime Ripard
Michael Turquette
Родитель
6f9f7f876e
Коммит
e9b9321310
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@ -6,6 +6,10 @@ if SUNXI_CCU
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# Base clock types
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config SUNXI_CCU_DIV
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bool
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select SUNXI_CCU_MUX
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config SUNXI_CCU_FRAC
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bool
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@ -3,6 +3,7 @@ obj-$(CONFIG_SUNXI_CCU) += ccu_common.o
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obj-$(CONFIG_SUNXI_CCU) += ccu_reset.o
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# Base clock types
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obj-$(CONFIG_SUNXI_CCU_DIV) += ccu_div.o
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obj-$(CONFIG_SUNXI_CCU_FRAC) += ccu_frac.o
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obj-$(CONFIG_SUNXI_CCU_GATE) += ccu_gate.o
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obj-$(CONFIG_SUNXI_CCU_MUX) += ccu_mux.o
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@ -0,0 +1,136 @@
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/*
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* Copyright (C) 2016 Maxime Ripard
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#include <linux/clk-provider.h>
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#include "ccu_gate.h"
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#include "ccu_div.h"
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static unsigned long ccu_div_round_rate(struct ccu_mux_internal *mux,
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unsigned long parent_rate,
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unsigned long rate,
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void *data)
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{
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struct ccu_div *cd = data;
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unsigned long val;
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/*
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* We can't use divider_round_rate that assumes that there's
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* several parents, while we might be called to evaluate
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* several different parents.
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*/
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val = divider_get_val(rate, parent_rate, cd->div.table, cd->div.width,
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cd->div.flags);
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return divider_recalc_rate(&cd->common.hw, parent_rate, val,
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cd->div.table, cd->div.flags);
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}
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static void ccu_div_disable(struct clk_hw *hw)
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{
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struct ccu_div *cd = hw_to_ccu_div(hw);
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return ccu_gate_helper_disable(&cd->common, cd->enable);
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}
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static int ccu_div_enable(struct clk_hw *hw)
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{
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struct ccu_div *cd = hw_to_ccu_div(hw);
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return ccu_gate_helper_enable(&cd->common, cd->enable);
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}
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static int ccu_div_is_enabled(struct clk_hw *hw)
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{
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struct ccu_div *cd = hw_to_ccu_div(hw);
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return ccu_gate_helper_is_enabled(&cd->common, cd->enable);
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}
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static unsigned long ccu_div_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct ccu_div *cd = hw_to_ccu_div(hw);
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unsigned long val;
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u32 reg;
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reg = readl(cd->common.base + cd->common.reg);
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val = reg >> cd->div.shift;
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val &= (1 << cd->div.width) - 1;
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ccu_mux_helper_adjust_parent_for_prediv(&cd->common, &cd->mux, -1,
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&parent_rate);
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return divider_recalc_rate(hw, parent_rate, val, cd->div.table,
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cd->div.flags);
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}
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static int ccu_div_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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struct ccu_div *cd = hw_to_ccu_div(hw);
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return ccu_mux_helper_determine_rate(&cd->common, &cd->mux,
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req, ccu_div_round_rate, cd);
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}
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static int ccu_div_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct ccu_div *cd = hw_to_ccu_div(hw);
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unsigned long flags;
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unsigned long val;
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u32 reg;
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ccu_mux_helper_adjust_parent_for_prediv(&cd->common, &cd->mux, -1,
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&parent_rate);
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val = divider_get_val(rate, parent_rate, cd->div.table, cd->div.width,
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cd->div.flags);
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spin_lock_irqsave(cd->common.lock, flags);
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reg = readl(cd->common.base + cd->common.reg);
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reg &= ~GENMASK(cd->div.width + cd->div.shift - 1, cd->div.shift);
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writel(reg | (val << cd->div.shift),
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cd->common.base + cd->common.reg);
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spin_unlock_irqrestore(cd->common.lock, flags);
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return 0;
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}
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static u8 ccu_div_get_parent(struct clk_hw *hw)
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{
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struct ccu_div *cd = hw_to_ccu_div(hw);
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return ccu_mux_helper_get_parent(&cd->common, &cd->mux);
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}
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static int ccu_div_set_parent(struct clk_hw *hw, u8 index)
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{
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struct ccu_div *cd = hw_to_ccu_div(hw);
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return ccu_mux_helper_set_parent(&cd->common, &cd->mux, index);
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}
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const struct clk_ops ccu_div_ops = {
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.disable = ccu_div_disable,
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.enable = ccu_div_enable,
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.is_enabled = ccu_div_is_enabled,
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.get_parent = ccu_div_get_parent,
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.set_parent = ccu_div_set_parent,
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.determine_rate = ccu_div_determine_rate,
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.recalc_rate = ccu_div_recalc_rate,
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.set_rate = ccu_div_set_rate,
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};
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@ -0,0 +1,133 @@
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/*
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* Copyright (c) 2016 Maxime Ripard. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _CCU_DIV_H_
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#define _CCU_DIV_H_
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#include <linux/clk-provider.h>
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#include "ccu_common.h"
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#include "ccu_mux.h"
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struct _ccu_div {
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u8 shift;
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u8 width;
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u32 flags;
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struct clk_div_table *table;
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};
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#define _SUNXI_CCU_DIV_TABLE_FLAGS(_shift, _width, _table, _flags) \
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{ \
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.shift = _shift, \
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.width = _width, \
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.flags = _flags, \
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.table = _table, \
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}
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#define _SUNXI_CCU_DIV_FLAGS(_shift, _width, _flags) \
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_SUNXI_CCU_DIV_TABLE_FLAGS(_shift, _width, NULL, _flags)
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#define _SUNXI_CCU_DIV_TABLE(_shift, _width, _table) \
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_SUNXI_CCU_DIV_TABLE_FLAGS(_shift, _width, _table, 0)
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#define _SUNXI_CCU_DIV(_shift, _width) \
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_SUNXI_CCU_DIV_TABLE_FLAGS(_shift, _width, NULL, 0)
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struct ccu_div {
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u32 enable;
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struct _ccu_div div;
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struct ccu_mux_internal mux;
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struct ccu_common common;
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};
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#define SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \
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_shift, _width, \
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_table, _gate, _flags) \
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struct ccu_div _struct = { \
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.div = _SUNXI_CCU_DIV_TABLE(_shift, _width, \
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_table), \
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.enable = _gate, \
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.common = { \
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.reg = _reg, \
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.hw.init = CLK_HW_INIT(_name, \
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_parent, \
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&ccu_div_ops, \
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_flags), \
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} \
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}
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#define SUNXI_CCU_DIV_TABLE(_struct, _name, _parent, _reg, \
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_shift, _width, \
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_table, _flags) \
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SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \
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_shift, _width, _table, 0, \
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_flags)
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#define SUNXI_CCU_M_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
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_mshift, _mwidth, _muxshift, _muxwidth, \
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_gate, _flags) \
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struct ccu_div _struct = { \
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.enable = _gate, \
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.div = _SUNXI_CCU_DIV(_mshift, _mwidth), \
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.mux = SUNXI_CLK_MUX(_muxshift, _muxwidth), \
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.common = { \
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.reg = _reg, \
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.hw.init = CLK_HW_INIT_PARENTS(_name, \
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_parents, \
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&ccu_div_ops, \
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_flags), \
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}, \
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}
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#define SUNXI_CCU_M_WITH_MUX(_struct, _name, _parents, _reg, \
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_mshift, _mwidth, _muxshift, _muxwidth, \
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_flags) \
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SUNXI_CCU_M_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
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_mshift, _mwidth, _muxshift, _muxwidth, \
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0, _flags)
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#define SUNXI_CCU_M_WITH_GATE(_struct, _name, _parent, _reg, \
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_mshift, _mwidth, _gate, \
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_flags) \
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struct ccu_div _struct = { \
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.enable = _gate, \
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.div = _SUNXI_CCU_DIV(_mshift, _mwidth), \
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.common = { \
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.reg = _reg, \
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.hw.init = CLK_HW_INIT(_name, \
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_parent, \
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&ccu_div_ops, \
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_flags), \
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}, \
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}
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#define SUNXI_CCU_M(_struct, _name, _parent, _reg, _mshift, _mwidth, \
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_flags) \
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SUNXI_CCU_M_WITH_GATE(_struct, _name, _parent, _reg, \
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_mshift, _mwidth, 0, _flags)
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static inline struct ccu_div *hw_to_ccu_div(struct clk_hw *hw)
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{
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struct ccu_common *common = hw_to_ccu_common(hw);
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return container_of(common, struct ccu_div, common);
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}
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extern const struct clk_ops ccu_div_ops;
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#endif /* _CCU_DIV_H_ */
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