MIPS: perf: Add hardware perf events support for new Loongson-3
New Loongson-3 means Loongson-3A R2 (Loongson-3A2000) and newer CPUs. Loongson-3 processors have three types of PMU types (so there are three event maps): Loongson-3A1000/Loonngson-3B1000/Loongson-3B1500 is Type-1, Loongson-3A2000/Loongson-3A3000 is Type-2, Loongson-3A4000+ is Type-3. Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
Huacai Chen
Thomas Bogendoerfer
Родитель
44220fd84f
Коммит
e9dfbaaeef
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@ -48,5 +48,6 @@
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#define cpu_hwrena_impl_bits 0xc0000000
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#define cpu_has_mac2008_only 1
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#define cpu_has_mips_r2_exec_hazard 0
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#define cpu_has_perf_cntr_intr_bit 0
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#endif /* __ASM_MACH_LOONGSON64_CPU_FEATURE_OVERRIDES_H */
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@ -90,6 +90,7 @@ struct mips_pmu {
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unsigned int num_counters;
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};
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static int counter_bits;
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static struct mips_pmu mipspmu;
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#define M_PERFCTL_EVENT(event) (((event) << MIPS_PERFCTRL_EVENT_S) & \
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@ -118,6 +119,7 @@ static struct mips_pmu mipspmu;
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#define M_PERFCTL_CONFIG_MASK 0x1f
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#endif
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#define CNTR_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1))
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#ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
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static DEFINE_RWLOCK(pmuint_rwlock);
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@ -154,6 +156,31 @@ static void pause_local_counters(void);
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static irqreturn_t mipsxx_pmu_handle_irq(int, void *);
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static int mipsxx_pmu_handle_shared_irq(void);
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/* 0: Not Loongson-3
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* 1: Loongson-3A1000/3B1000/3B1500
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* 2: Loongson-3A2000/3A3000
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* 3: Loongson-3A4000+
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*/
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#define LOONGSON_PMU_TYPE0 0
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#define LOONGSON_PMU_TYPE1 1
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#define LOONGSON_PMU_TYPE2 2
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#define LOONGSON_PMU_TYPE3 3
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static inline int get_loongson3_pmu_type(void)
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{
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if (boot_cpu_type() != CPU_LOONGSON64)
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return LOONGSON_PMU_TYPE0;
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if ((boot_cpu_data.processor_id & PRID_COMP_MASK) == PRID_COMP_LEGACY)
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return LOONGSON_PMU_TYPE1;
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if ((boot_cpu_data.processor_id & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64C)
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return LOONGSON_PMU_TYPE2;
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if ((boot_cpu_data.processor_id & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64G)
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return LOONGSON_PMU_TYPE3;
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return LOONGSON_PMU_TYPE0;
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}
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static unsigned int mipsxx_pmu_swizzle_perf_idx(unsigned int idx)
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{
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if (vpe_id() == 1)
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@ -186,17 +213,18 @@ static u64 mipsxx_pmu_read_counter(unsigned int idx)
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static u64 mipsxx_pmu_read_counter_64(unsigned int idx)
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{
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u64 mask = CNTR_BIT_MASK(counter_bits);
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idx = mipsxx_pmu_swizzle_perf_idx(idx);
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switch (idx) {
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case 0:
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return read_c0_perfcntr0_64();
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return read_c0_perfcntr0_64() & mask;
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case 1:
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return read_c0_perfcntr1_64();
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return read_c0_perfcntr1_64() & mask;
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case 2:
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return read_c0_perfcntr2_64();
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return read_c0_perfcntr2_64() & mask;
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case 3:
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return read_c0_perfcntr3_64();
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return read_c0_perfcntr3_64() & mask;
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default:
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WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx);
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return 0;
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@ -225,6 +253,7 @@ static void mipsxx_pmu_write_counter(unsigned int idx, u64 val)
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static void mipsxx_pmu_write_counter_64(unsigned int idx, u64 val)
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{
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val &= CNTR_BIT_MASK(counter_bits);
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idx = mipsxx_pmu_swizzle_perf_idx(idx);
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switch (idx) {
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@ -286,12 +315,16 @@ static int mipsxx_pmu_alloc_counter(struct cpu_hw_events *cpuc,
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struct hw_perf_event *hwc)
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{
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int i;
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unsigned long cntr_mask;
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/*
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* We only need to care the counter mask. The range has been
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* checked definitely.
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*/
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unsigned long cntr_mask = (hwc->event_base >> 8) & 0xffff;
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if (get_loongson3_pmu_type() == LOONGSON_PMU_TYPE2)
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cntr_mask = (hwc->event_base >> 10) & 0xffff;
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else
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cntr_mask = (hwc->event_base >> 8) & 0xffff;
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for (i = mipspmu.num_counters - 1; i >= 0; i--) {
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/*
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@ -320,10 +353,16 @@ static void mipsxx_pmu_enable_event(struct hw_perf_event *evt, int idx)
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WARN_ON(idx < 0 || idx >= mipspmu.num_counters);
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cpuc->saved_ctrl[idx] = M_PERFCTL_EVENT(evt->event_base & 0xff) |
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(evt->config_base & M_PERFCTL_CONFIG_MASK) |
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/* Make sure interrupt enabled. */
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MIPS_PERFCTRL_IE;
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if (get_loongson3_pmu_type() == LOONGSON_PMU_TYPE2)
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cpuc->saved_ctrl[idx] = M_PERFCTL_EVENT(evt->event_base & 0x3ff) |
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(evt->config_base & M_PERFCTL_CONFIG_MASK) |
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/* Make sure interrupt enabled. */
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MIPS_PERFCTRL_IE;
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else
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cpuc->saved_ctrl[idx] = M_PERFCTL_EVENT(evt->event_base & 0xff) |
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(evt->config_base & M_PERFCTL_CONFIG_MASK) |
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/* Make sure interrupt enabled. */
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MIPS_PERFCTRL_IE;
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if (IS_ENABLED(CONFIG_CPU_BMIPS5000)) {
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/* enable the counter for the calling thread */
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@ -396,6 +435,10 @@ static int mipspmu_event_set_period(struct perf_event *event,
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local64_set(&hwc->prev_count, mipspmu.overflow - left);
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if (get_loongson3_pmu_type() == LOONGSON_PMU_TYPE2)
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mipsxx_pmu_write_control(idx,
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M_PERFCTL_EVENT(hwc->event_base & 0x3ff));
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mipspmu.write_counter(idx, mipspmu.overflow - left);
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perf_event_update_userpage(event);
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@ -667,8 +710,14 @@ static unsigned int mipspmu_perf_event_encode(const struct mips_perf_event *pev)
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(pev->event_id & 0xff);
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else
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#endif /* CONFIG_MIPS_MT_SMP */
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return ((pev->cntr_mask & 0xffff00) |
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(pev->event_id & 0xff));
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{
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if (get_loongson3_pmu_type() == LOONGSON_PMU_TYPE2)
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return (pev->cntr_mask & 0xfffc00) |
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(pev->event_id & 0x3ff);
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else
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return (pev->cntr_mask & 0xffff00) |
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(pev->event_id & 0xff);
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}
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}
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static const struct mips_perf_event *mipspmu_map_general_event(int idx)
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@ -783,26 +832,104 @@ static int n_counters(void)
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return counters;
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}
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static void reset_counters(void *arg)
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static void loongson3_reset_counters(void *arg)
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{
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int counters = (int)(long)arg;
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switch (counters) {
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case 4:
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mipsxx_pmu_write_control(3, 0);
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mipspmu.write_counter(3, 0);
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/* fall through */
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mipsxx_pmu_write_control(3, 127<<5);
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mipspmu.write_counter(3, 0);
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mipsxx_pmu_write_control(3, 191<<5);
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mipspmu.write_counter(3, 0);
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mipsxx_pmu_write_control(3, 255<<5);
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mipspmu.write_counter(3, 0);
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mipsxx_pmu_write_control(3, 319<<5);
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mipspmu.write_counter(3, 0);
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mipsxx_pmu_write_control(3, 383<<5);
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mipspmu.write_counter(3, 0);
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mipsxx_pmu_write_control(3, 575<<5);
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mipspmu.write_counter(3, 0);
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fallthrough;
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case 3:
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mipsxx_pmu_write_control(2, 0);
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mipspmu.write_counter(2, 0);
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/* fall through */
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mipsxx_pmu_write_control(2, 127<<5);
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mipspmu.write_counter(2, 0);
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mipsxx_pmu_write_control(2, 191<<5);
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mipspmu.write_counter(2, 0);
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mipsxx_pmu_write_control(2, 255<<5);
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mipspmu.write_counter(2, 0);
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mipsxx_pmu_write_control(2, 319<<5);
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mipspmu.write_counter(2, 0);
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mipsxx_pmu_write_control(2, 383<<5);
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mipspmu.write_counter(2, 0);
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mipsxx_pmu_write_control(2, 575<<5);
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mipspmu.write_counter(2, 0);
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fallthrough;
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case 2:
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mipsxx_pmu_write_control(1, 0);
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mipspmu.write_counter(1, 0);
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/* fall through */
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mipsxx_pmu_write_control(1, 127<<5);
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mipspmu.write_counter(1, 0);
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mipsxx_pmu_write_control(1, 191<<5);
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mipspmu.write_counter(1, 0);
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mipsxx_pmu_write_control(1, 255<<5);
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mipspmu.write_counter(1, 0);
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mipsxx_pmu_write_control(1, 319<<5);
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mipspmu.write_counter(1, 0);
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mipsxx_pmu_write_control(1, 383<<5);
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mipspmu.write_counter(1, 0);
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mipsxx_pmu_write_control(1, 575<<5);
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mipspmu.write_counter(1, 0);
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fallthrough;
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case 1:
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mipsxx_pmu_write_control(0, 0);
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mipspmu.write_counter(0, 0);
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/* fall through */
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mipsxx_pmu_write_control(0, 127<<5);
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mipspmu.write_counter(0, 0);
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mipsxx_pmu_write_control(0, 191<<5);
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mipspmu.write_counter(0, 0);
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mipsxx_pmu_write_control(0, 255<<5);
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mipspmu.write_counter(0, 0);
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mipsxx_pmu_write_control(0, 319<<5);
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mipspmu.write_counter(0, 0);
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mipsxx_pmu_write_control(0, 383<<5);
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mipspmu.write_counter(0, 0);
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mipsxx_pmu_write_control(0, 575<<5);
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mipspmu.write_counter(0, 0);
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fallthrough;
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}
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}
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static void reset_counters(void *arg)
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{
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int counters = (int)(long)arg;
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if (get_loongson3_pmu_type() == LOONGSON_PMU_TYPE2) {
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loongson3_reset_counters(arg);
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return;
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}
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switch (counters) {
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case 4:
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mipsxx_pmu_write_control(3, 0);
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mipspmu.write_counter(3, 0);
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fallthrough;
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case 3:
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mipsxx_pmu_write_control(2, 0);
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mipspmu.write_counter(2, 0);
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fallthrough;
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case 2:
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mipsxx_pmu_write_control(1, 0);
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mipspmu.write_counter(1, 0);
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fallthrough;
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case 1:
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mipsxx_pmu_write_control(0, 0);
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mipspmu.write_counter(0, 0);
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fallthrough;
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}
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}
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@ -834,13 +961,30 @@ static const struct mips_perf_event i6x00_event_map[PERF_COUNT_HW_MAX] = {
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[PERF_COUNT_HW_BRANCH_MISSES] = { 0x16, CNTR_EVEN | CNTR_ODD },
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};
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static const struct mips_perf_event loongson3_event_map[PERF_COUNT_HW_MAX] = {
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static const struct mips_perf_event loongson3_event_map1[PERF_COUNT_HW_MAX] = {
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[PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN },
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[PERF_COUNT_HW_INSTRUCTIONS] = { 0x00, CNTR_ODD },
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[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x01, CNTR_EVEN },
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[PERF_COUNT_HW_BRANCH_MISSES] = { 0x01, CNTR_ODD },
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};
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static const struct mips_perf_event loongson3_event_map2[PERF_COUNT_HW_MAX] = {
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[PERF_COUNT_HW_CPU_CYCLES] = { 0x80, CNTR_ALL },
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[PERF_COUNT_HW_INSTRUCTIONS] = { 0x81, CNTR_ALL },
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[PERF_COUNT_HW_CACHE_MISSES] = { 0x18, CNTR_ALL },
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[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x94, CNTR_ALL },
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[PERF_COUNT_HW_BRANCH_MISSES] = { 0x9c, CNTR_ALL },
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};
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static const struct mips_perf_event loongson3_event_map3[PERF_COUNT_HW_MAX] = {
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[PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_ALL },
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[PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_ALL },
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[PERF_COUNT_HW_CACHE_REFERENCES] = { 0x1c, CNTR_ALL },
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[PERF_COUNT_HW_CACHE_MISSES] = { 0x1d, CNTR_ALL },
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[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x02, CNTR_ALL },
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[PERF_COUNT_HW_BRANCH_MISSES] = { 0x08, CNTR_ALL },
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};
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static const struct mips_perf_event octeon_event_map[PERF_COUNT_HW_MAX] = {
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[PERF_COUNT_HW_CPU_CYCLES] = { 0x01, CNTR_ALL },
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[PERF_COUNT_HW_INSTRUCTIONS] = { 0x03, CNTR_ALL },
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@ -1064,7 +1208,7 @@ static const struct mips_perf_event i6x00_cache_map
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},
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};
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static const struct mips_perf_event loongson3_cache_map
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static const struct mips_perf_event loongson3_cache_map1
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[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
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@ -1109,12 +1253,127 @@ static const struct mips_perf_event loongson3_cache_map
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[C(BPU)] = {
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/* Using the same code for *HW_BRANCH* */
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN },
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[C(RESULT_MISS)] = { 0x02, CNTR_ODD },
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[C(RESULT_ACCESS)] = { 0x01, CNTR_EVEN },
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[C(RESULT_MISS)] = { 0x01, CNTR_ODD },
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN },
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[C(RESULT_MISS)] = { 0x02, CNTR_ODD },
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[C(RESULT_ACCESS)] = { 0x01, CNTR_EVEN },
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[C(RESULT_MISS)] = { 0x01, CNTR_ODD },
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},
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},
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};
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static const struct mips_perf_event loongson3_cache_map2
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[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
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[C(L1D)] = {
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/*
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* Like some other architectures (e.g. ARM), the performance
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* counters don't differentiate between read and write
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* accesses/misses, so this isn't strictly correct, but it's the
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* best we can do. Writes and reads get combined.
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*/
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = { 0x156, CNTR_ALL },
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = { 0x155, CNTR_ALL },
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[C(RESULT_MISS)] = { 0x153, CNTR_ALL },
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},
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},
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[C(L1I)] = {
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[C(OP_READ)] = {
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[C(RESULT_MISS)] = { 0x18, CNTR_ALL },
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},
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[C(OP_WRITE)] = {
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[C(RESULT_MISS)] = { 0x18, CNTR_ALL },
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},
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},
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[C(LL)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = { 0x1b6, CNTR_ALL },
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = { 0x1b7, CNTR_ALL },
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = { 0x1bf, CNTR_ALL },
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},
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},
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[C(DTLB)] = {
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[C(OP_READ)] = {
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[C(RESULT_MISS)] = { 0x92, CNTR_ALL },
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},
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[C(OP_WRITE)] = {
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[C(RESULT_MISS)] = { 0x92, CNTR_ALL },
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},
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},
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[C(ITLB)] = {
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[C(OP_READ)] = {
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[C(RESULT_MISS)] = { 0x1a, CNTR_ALL },
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},
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[C(OP_WRITE)] = {
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[C(RESULT_MISS)] = { 0x1a, CNTR_ALL },
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},
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},
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[C(BPU)] = {
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/* Using the same code for *HW_BRANCH* */
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = { 0x94, CNTR_ALL },
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[C(RESULT_MISS)] = { 0x9c, CNTR_ALL },
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static const struct mips_perf_event loongson3_cache_map3
|
||||
[PERF_COUNT_HW_CACHE_MAX]
|
||||
[PERF_COUNT_HW_CACHE_OP_MAX]
|
||||
[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
|
||||
[C(L1D)] = {
|
||||
/*
|
||||
* Like some other architectures (e.g. ARM), the performance
|
||||
* counters don't differentiate between read and write
|
||||
* accesses/misses, so this isn't strictly correct, but it's the
|
||||
* best we can do. Writes and reads get combined.
|
||||
*/
|
||||
[C(OP_READ)] = {
|
||||
[C(RESULT_ACCESS)] = { 0x1e, CNTR_ALL },
|
||||
[C(RESULT_MISS)] = { 0x1f, CNTR_ALL },
|
||||
},
|
||||
[C(OP_PREFETCH)] = {
|
||||
[C(RESULT_ACCESS)] = { 0xaa, CNTR_ALL },
|
||||
[C(RESULT_MISS)] = { 0xa9, CNTR_ALL },
|
||||
},
|
||||
},
|
||||
[C(L1I)] = {
|
||||
[C(OP_READ)] = {
|
||||
[C(RESULT_ACCESS)] = { 0x1c, CNTR_ALL },
|
||||
[C(RESULT_MISS)] = { 0x1d, CNTR_ALL },
|
||||
},
|
||||
},
|
||||
[C(LL)] = {
|
||||
[C(OP_READ)] = {
|
||||
[C(RESULT_ACCESS)] = { 0x2e, CNTR_ALL },
|
||||
[C(RESULT_MISS)] = { 0x2f, CNTR_ALL },
|
||||
},
|
||||
},
|
||||
[C(DTLB)] = {
|
||||
[C(OP_READ)] = {
|
||||
[C(RESULT_ACCESS)] = { 0x14, CNTR_ALL },
|
||||
[C(RESULT_MISS)] = { 0x1b, CNTR_ALL },
|
||||
},
|
||||
},
|
||||
[C(ITLB)] = {
|
||||
[C(OP_READ)] = {
|
||||
[C(RESULT_MISS)] = { 0x1a, CNTR_ALL },
|
||||
},
|
||||
},
|
||||
[C(BPU)] = {
|
||||
/* Using the same code for *HW_BRANCH* */
|
||||
[C(OP_READ)] = {
|
||||
[C(RESULT_ACCESS)] = { 0x02, CNTR_ALL },
|
||||
[C(RESULT_MISS)] = { 0x08, CNTR_ALL },
|
||||
},
|
||||
},
|
||||
};
|
||||
|
|
@ -1178,7 +1437,6 @@ static const struct mips_perf_event bmips5000_cache_map
|
|||
},
|
||||
};
|
||||
|
||||
|
||||
static const struct mips_perf_event octeon_cache_map
|
||||
[PERF_COUNT_HW_CACHE_MAX]
|
||||
[PERF_COUNT_HW_CACHE_OP_MAX]
|
||||
|
|
@ -1512,6 +1770,7 @@ static irqreturn_t mipsxx_pmu_handle_irq(int irq, void *dev)
|
|||
static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
|
||||
{
|
||||
/* currently most cores have 7-bit event numbers */
|
||||
int pmu_type;
|
||||
unsigned int raw_id = config & 0xff;
|
||||
unsigned int base_id = raw_id & 0x7f;
|
||||
|
||||
|
|
@ -1624,8 +1883,33 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
|
|||
raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
|
||||
break;
|
||||
case CPU_LOONGSON64:
|
||||
raw_event.cntr_mask = raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
|
||||
break;
|
||||
pmu_type = get_loongson3_pmu_type();
|
||||
|
||||
switch (pmu_type) {
|
||||
case LOONGSON_PMU_TYPE1:
|
||||
raw_event.cntr_mask =
|
||||
raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
|
||||
break;
|
||||
case LOONGSON_PMU_TYPE2:
|
||||
base_id = config & 0x3ff;
|
||||
raw_event.cntr_mask = CNTR_ALL;
|
||||
|
||||
if ((base_id >= 1 && base_id < 28) ||
|
||||
(base_id >= 64 && base_id < 90) ||
|
||||
(base_id >= 128 && base_id < 164) ||
|
||||
(base_id >= 192 && base_id < 200) ||
|
||||
(base_id >= 256 && base_id < 274) ||
|
||||
(base_id >= 320 && base_id < 358) ||
|
||||
(base_id >= 384 && base_id < 574))
|
||||
break;
|
||||
|
||||
return ERR_PTR(-EOPNOTSUPP);
|
||||
case LOONGSON_PMU_TYPE3:
|
||||
base_id = raw_id;
|
||||
raw_event.cntr_mask = CNTR_ALL;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
raw_event.event_id = base_id;
|
||||
|
|
@ -1683,8 +1967,7 @@ static const struct mips_perf_event *xlp_pmu_map_raw_event(u64 config)
|
|||
static int __init
|
||||
init_hw_perf_events(void)
|
||||
{
|
||||
int counters, irq;
|
||||
int counter_bits;
|
||||
int counters, irq, pmu_type;
|
||||
|
||||
pr_info("Performance counters: ");
|
||||
|
||||
|
|
@ -1771,8 +2054,25 @@ init_hw_perf_events(void)
|
|||
break;
|
||||
case CPU_LOONGSON64:
|
||||
mipspmu.name = "mips/loongson3";
|
||||
mipspmu.general_event_map = &loongson3_event_map;
|
||||
mipspmu.cache_event_map = &loongson3_cache_map;
|
||||
pmu_type = get_loongson3_pmu_type();
|
||||
|
||||
switch (pmu_type) {
|
||||
case LOONGSON_PMU_TYPE1:
|
||||
counters = 2;
|
||||
mipspmu.general_event_map = &loongson3_event_map1;
|
||||
mipspmu.cache_event_map = &loongson3_cache_map1;
|
||||
break;
|
||||
case LOONGSON_PMU_TYPE2:
|
||||
counters = 4;
|
||||
mipspmu.general_event_map = &loongson3_event_map2;
|
||||
mipspmu.cache_event_map = &loongson3_cache_map2;
|
||||
break;
|
||||
case LOONGSON_PMU_TYPE3:
|
||||
counters = 4;
|
||||
mipspmu.general_event_map = &loongson3_event_map3;
|
||||
mipspmu.cache_event_map = &loongson3_cache_map3;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case CPU_CAVIUM_OCTEON:
|
||||
case CPU_CAVIUM_OCTEON_PLUS:
|
||||
|
|
@ -1803,19 +2103,26 @@ init_hw_perf_events(void)
|
|||
mipspmu.irq = irq;
|
||||
|
||||
if (read_c0_perfctrl0() & MIPS_PERFCTRL_W) {
|
||||
mipspmu.max_period = (1ULL << 63) - 1;
|
||||
mipspmu.valid_count = (1ULL << 63) - 1;
|
||||
mipspmu.overflow = 1ULL << 63;
|
||||
if (get_loongson3_pmu_type() == LOONGSON_PMU_TYPE2) {
|
||||
counter_bits = 48;
|
||||
mipspmu.max_period = (1ULL << 47) - 1;
|
||||
mipspmu.valid_count = (1ULL << 47) - 1;
|
||||
mipspmu.overflow = 1ULL << 47;
|
||||
} else {
|
||||
counter_bits = 64;
|
||||
mipspmu.max_period = (1ULL << 63) - 1;
|
||||
mipspmu.valid_count = (1ULL << 63) - 1;
|
||||
mipspmu.overflow = 1ULL << 63;
|
||||
}
|
||||
mipspmu.read_counter = mipsxx_pmu_read_counter_64;
|
||||
mipspmu.write_counter = mipsxx_pmu_write_counter_64;
|
||||
counter_bits = 64;
|
||||
} else {
|
||||
counter_bits = 32;
|
||||
mipspmu.max_period = (1ULL << 31) - 1;
|
||||
mipspmu.valid_count = (1ULL << 31) - 1;
|
||||
mipspmu.overflow = 1ULL << 31;
|
||||
mipspmu.read_counter = mipsxx_pmu_read_counter;
|
||||
mipspmu.write_counter = mipsxx_pmu_write_counter;
|
||||
counter_bits = 32;
|
||||
}
|
||||
|
||||
on_each_cpu(reset_counters, (void *)(long)counters, 1);
|
||||
|
|
|
|||
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