net: atlantic: loopback tests via private flags
Here we add a number of ethtool private flags to allow enabling various loopbacks on HW. Thats useful for verification and bringup works. Signed-off-by: Igor Russkikh <irusskikh@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Igor Russkikh
David S. Miller
Родитель
dc12f75afc
Коммит
ea4b4d7fc1
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@ -325,6 +325,31 @@ Supported ethtool options
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Example:
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ethtool -N eth0 flow-type udp4 action 0 loc 32
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Private flags (testing)
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---------------------------------
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Atlantic driver supports private flags for hardware custom features:
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$ ethtool --show-priv-flags ethX
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Private flags for ethX:
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DMASystemLoopback : off
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PKTSystemLoopback : off
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DMANetworkLoopback : off
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PHYInternalLoopback: off
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PHYExternalLoopback: off
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Example:
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$ ethtool --set-priv-flags ethX DMASystemLoopback on
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DMASystemLoopback: DMA Host loopback.
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PKTSystemLoopback: Packet buffer host loopback.
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DMANetworkLoopback: Network side loopback on DMA block.
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PHYInternalLoopback: Internal loopback on Phy.
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PHYExternalLoopback: External loopback on Phy (with loopback ethernet cable).
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Command Line Parameters
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=======================
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The following command line parameters are available on atlantic driver:
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@ -92,6 +92,14 @@ static const char aq_ethtool_queue_stat_names[][ETH_GSTRING_LEN] = {
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"Queue[%d] InErrors",
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};
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static const char aq_ethtool_priv_flag_names[][ETH_GSTRING_LEN] = {
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"DMASystemLoopback",
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"PKTSystemLoopback",
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"DMANetworkLoopback",
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"PHYInternalLoopback",
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"PHYExternalLoopback",
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};
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static void aq_ethtool_stats(struct net_device *ndev,
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struct ethtool_stats *stats, u64 *data)
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{
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@ -137,7 +145,8 @@ static void aq_ethtool_get_strings(struct net_device *ndev,
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struct aq_nic_cfg_s *cfg = aq_nic_get_cfg(aq_nic);
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u8 *p = data;
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if (stringset == ETH_SS_STATS) {
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switch (stringset) {
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case ETH_SS_STATS:
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memcpy(p, aq_ethtool_stat_names,
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sizeof(aq_ethtool_stat_names));
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p = p + sizeof(aq_ethtool_stat_names);
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@ -150,6 +159,11 @@ static void aq_ethtool_get_strings(struct net_device *ndev,
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p += ETH_GSTRING_LEN;
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}
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}
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break;
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case ETH_SS_PRIV_FLAGS:
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memcpy(p, aq_ethtool_priv_flag_names,
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sizeof(aq_ethtool_priv_flag_names));
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break;
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}
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}
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@ -193,6 +207,9 @@ static int aq_ethtool_get_sset_count(struct net_device *ndev, int stringset)
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ret = ARRAY_SIZE(aq_ethtool_stat_names) +
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cfg->vecs * ARRAY_SIZE(aq_ethtool_queue_stat_names);
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break;
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case ETH_SS_PRIV_FLAGS:
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ret = ARRAY_SIZE(aq_ethtool_priv_flag_names);
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break;
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default:
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ret = -EOPNOTSUPP;
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}
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@ -650,6 +667,40 @@ static void aq_set_msg_level(struct net_device *ndev, u32 data)
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aq_nic->msg_enable = data;
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}
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u32 aq_ethtool_get_priv_flags(struct net_device *ndev)
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{
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struct aq_nic_s *aq_nic = netdev_priv(ndev);
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return aq_nic->aq_nic_cfg.priv_flags;
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}
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int aq_ethtool_set_priv_flags(struct net_device *ndev, u32 flags)
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{
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struct aq_nic_s *aq_nic = netdev_priv(ndev);
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struct aq_nic_cfg_s *cfg;
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u32 priv_flags;
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cfg = aq_nic_get_cfg(aq_nic);
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priv_flags = cfg->priv_flags;
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if (flags & ~AQ_PRIV_FLAGS_MASK)
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return -EOPNOTSUPP;
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cfg->priv_flags = flags;
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if ((priv_flags ^ flags) & BIT(AQ_HW_LOOPBACK_DMA_NET)) {
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if (netif_running(ndev)) {
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dev_close(ndev);
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dev_open(ndev, NULL);
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}
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} else if ((priv_flags ^ flags) & AQ_HW_LOOPBACK_MASK) {
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aq_nic_set_loopback(aq_nic);
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}
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return 0;
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}
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const struct ethtool_ops aq_ethtool_ops = {
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.get_link = aq_ethtool_get_link,
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.get_regs_len = aq_ethtool_get_regs_len,
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@ -676,6 +727,8 @@ const struct ethtool_ops aq_ethtool_ops = {
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.set_msglevel = aq_set_msg_level,
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.get_sset_count = aq_ethtool_get_sset_count,
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.get_ethtool_stats = aq_ethtool_stats,
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.get_priv_flags = aq_ethtool_get_priv_flags,
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.set_priv_flags = aq_ethtool_set_priv_flags,
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.get_link_ksettings = aq_ethtool_get_link_ksettings,
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.set_link_ksettings = aq_ethtool_set_link_ksettings,
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.get_coalesce = aq_ethtool_get_coalesce,
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@ -12,5 +12,6 @@
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#include "aq_common.h"
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extern const struct ethtool_ops aq_ethtool_ops;
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#define AQ_PRIV_FLAGS_MASK (AQ_HW_LOOPBACK_MASK)
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#endif /* AQ_ETHTOOL_H */
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@ -122,6 +122,20 @@ struct aq_stats_s {
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#define AQ_HW_LED_BLINK 0x2U
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#define AQ_HW_LED_DEFAULT 0x0U
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enum aq_priv_flags {
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AQ_HW_LOOPBACK_DMA_SYS,
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AQ_HW_LOOPBACK_PKT_SYS,
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AQ_HW_LOOPBACK_DMA_NET,
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AQ_HW_LOOPBACK_PHYINT_SYS,
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AQ_HW_LOOPBACK_PHYEXT_SYS,
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};
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#define AQ_HW_LOOPBACK_MASK (BIT(AQ_HW_LOOPBACK_DMA_SYS) |\
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BIT(AQ_HW_LOOPBACK_PKT_SYS) |\
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BIT(AQ_HW_LOOPBACK_DMA_NET) |\
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BIT(AQ_HW_LOOPBACK_PHYINT_SYS) |\
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BIT(AQ_HW_LOOPBACK_PHYEXT_SYS))
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struct aq_hw_s {
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atomic_t flags;
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u8 rbl_enabled:1;
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@ -280,6 +294,8 @@ struct aq_hw_ops {
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u64 *timestamp);
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int (*hw_set_fc)(struct aq_hw_s *self, u32 fc, u32 tc);
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int (*hw_set_loopback)(struct aq_hw_s *self, u32 mode, bool enable);
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};
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struct aq_fw_ops {
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@ -310,6 +326,8 @@ struct aq_fw_ops {
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int (*led_control)(struct aq_hw_s *self, u32 mode);
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int (*set_phyloopback)(struct aq_hw_s *self, u32 mode, bool enable);
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int (*set_power)(struct aq_hw_s *self, unsigned int power_state,
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u8 *mac);
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@ -406,6 +406,8 @@ int aq_nic_start(struct aq_nic_s *self)
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INIT_WORK(&self->service_task, aq_nic_service_task);
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aq_nic_set_loopback(self);
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timer_setup(&self->service_timer, aq_nic_service_timer_cb, 0);
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aq_nic_service_timer_cb(&self->service_timer);
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@ -625,6 +627,11 @@ int aq_nic_xmit(struct aq_nic_s *self, struct sk_buff *skb)
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aq_ring_update_queue_state(ring);
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if (self->aq_nic_cfg.priv_flags & BIT(AQ_HW_LOOPBACK_DMA_NET)) {
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err = NETDEV_TX_BUSY;
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goto err_exit;
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}
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/* Above status update may stop the queue. Check this. */
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if (__netif_subqueue_stopped(self->ndev, ring->idx)) {
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err = NETDEV_TX_BUSY;
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@ -973,6 +980,44 @@ u32 aq_nic_get_fw_version(struct aq_nic_s *self)
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return fw_version;
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}
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int aq_nic_set_loopback(struct aq_nic_s *self)
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{
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struct aq_nic_cfg_s *cfg = &self->aq_nic_cfg;
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if (!self->aq_hw_ops->hw_set_loopback ||
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!self->aq_fw_ops->set_phyloopback)
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return -ENOTSUPP;
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mutex_lock(&self->fwreq_mutex);
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self->aq_hw_ops->hw_set_loopback(self->aq_hw,
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AQ_HW_LOOPBACK_DMA_SYS,
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!!(cfg->priv_flags &
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BIT(AQ_HW_LOOPBACK_DMA_SYS)));
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self->aq_hw_ops->hw_set_loopback(self->aq_hw,
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AQ_HW_LOOPBACK_PKT_SYS,
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!!(cfg->priv_flags &
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BIT(AQ_HW_LOOPBACK_PKT_SYS)));
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self->aq_hw_ops->hw_set_loopback(self->aq_hw,
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AQ_HW_LOOPBACK_DMA_NET,
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!!(cfg->priv_flags &
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BIT(AQ_HW_LOOPBACK_DMA_NET)));
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self->aq_fw_ops->set_phyloopback(self->aq_hw,
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AQ_HW_LOOPBACK_PHYINT_SYS,
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!!(cfg->priv_flags &
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BIT(AQ_HW_LOOPBACK_PHYINT_SYS)));
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self->aq_fw_ops->set_phyloopback(self->aq_hw,
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AQ_HW_LOOPBACK_PHYEXT_SYS,
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!!(cfg->priv_flags &
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BIT(AQ_HW_LOOPBACK_PHYEXT_SYS)));
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mutex_unlock(&self->fwreq_mutex);
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return 0;
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}
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int aq_nic_stop(struct aq_nic_s *self)
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{
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struct aq_vec_s *aq_vec = NULL;
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@ -46,6 +46,7 @@ struct aq_nic_cfg_s {
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bool is_polling;
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bool is_rss;
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bool is_lro;
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u32 priv_flags;
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u8 tcs;
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struct aq_rss_parameters aq_rss;
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u32 eee_speeds;
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@ -158,6 +159,7 @@ int aq_nic_set_link_ksettings(struct aq_nic_s *self,
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const struct ethtool_link_ksettings *cmd);
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struct aq_nic_cfg_s *aq_nic_get_cfg(struct aq_nic_s *self);
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u32 aq_nic_get_fw_version(struct aq_nic_s *self);
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int aq_nic_set_loopback(struct aq_nic_s *self);
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int aq_nic_update_interrupt_moderation_settings(struct aq_nic_s *self);
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void aq_nic_shutdown(struct aq_nic_s *self);
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u8 aq_nic_reserve_filter(struct aq_nic_s *self, enum aq_rx_filter_type type);
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@ -1427,6 +1427,30 @@ static int hw_atl_b0_hw_vlan_ctrl(struct aq_hw_s *self, bool enable)
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return aq_hw_err_from_flags(self);
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}
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static int hw_atl_b0_set_loopback(struct aq_hw_s *self, u32 mode, bool enable)
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{
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switch (mode) {
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case AQ_HW_LOOPBACK_DMA_SYS:
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hw_atl_tpb_tx_dma_sys_lbk_en_set(self, enable);
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hw_atl_rpb_dma_sys_lbk_set(self, enable);
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break;
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case AQ_HW_LOOPBACK_PKT_SYS:
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hw_atl_tpo_tx_pkt_sys_lbk_en_set(self, enable);
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hw_atl_rpf_tpo_to_rpf_sys_lbk_set(self, enable);
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break;
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case AQ_HW_LOOPBACK_DMA_NET:
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hw_atl_rpf_vlan_prom_mode_en_set(self, enable);
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hw_atl_rpfl2promiscuous_mode_en_set(self, enable);
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hw_atl_tpb_tx_tx_clk_gate_en_set(self, !enable);
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hw_atl_tpb_tx_dma_net_lbk_en_set(self, enable);
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hw_atl_rpb_dma_net_lbk_set(self, enable);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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const struct aq_hw_ops hw_atl_ops_b0 = {
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.hw_set_mac_address = hw_atl_b0_hw_mac_addr_set,
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.hw_init = hw_atl_b0_hw_init,
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@ -1481,5 +1505,9 @@ const struct aq_hw_ops hw_atl_ops_b0 = {
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.rx_extract_ts = hw_atl_b0_rx_extract_ts,
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.extract_hwts = hw_atl_b0_extract_hwts,
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.hw_set_offload = hw_atl_b0_hw_offload_set,
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.hw_set_fc = hw_atl_b0_set_fc,
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.hw_get_hw_stats = hw_atl_utils_get_hw_stats,
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.hw_get_fw_version = hw_atl_utils_get_fw_version,
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.hw_set_offload = hw_atl_b0_hw_offload_set,
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.hw_set_loopback = hw_atl_b0_set_loopback,
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.hw_set_fc = hw_atl_b0_set_fc,
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};
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@ -563,6 +563,13 @@ void hw_atl_rpb_dma_sys_lbk_set(struct aq_hw_s *aq_hw, u32 dma_sys_lbk)
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HW_ATL_RPB_DMA_SYS_LBK_SHIFT, dma_sys_lbk);
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}
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void hw_atl_rpb_dma_net_lbk_set(struct aq_hw_s *aq_hw, u32 dma_net_lbk)
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{
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aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_DMA_NET_LBK_ADR,
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HW_ATL_RPB_DMA_NET_LBK_MSK,
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HW_ATL_RPB_DMA_NET_LBK_SHIFT, dma_net_lbk);
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}
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void hw_atl_rpb_rpf_rx_traf_class_mode_set(struct aq_hw_s *aq_hw,
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u32 rx_traf_class_mode)
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{
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@ -1341,7 +1348,26 @@ void hw_atl_tpb_tx_dma_sys_lbk_en_set(struct aq_hw_s *aq_hw, u32 tx_dma_sys_lbk_
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tx_dma_sys_lbk_en);
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}
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void hw_atl_tpb_tx_dma_net_lbk_en_set(struct aq_hw_s *aq_hw,
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u32 tx_dma_net_lbk_en)
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{
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aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_DMA_NET_LBK_ADR,
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HW_ATL_TPB_DMA_NET_LBK_MSK,
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HW_ATL_TPB_DMA_NET_LBK_SHIFT,
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tx_dma_net_lbk_en);
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}
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void hw_atl_tpb_tx_tx_clk_gate_en_set(struct aq_hw_s *aq_hw,
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u32 tx_clk_gate_en)
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{
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aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TX_CLK_GATE_EN_ADR,
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HW_ATL_TPB_TX_CLK_GATE_EN_MSK,
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HW_ATL_TPB_TX_CLK_GATE_EN_SHIFT,
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tx_clk_gate_en);
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}
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void hw_atl_tpb_tx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw,
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u32 tx_pkt_buff_size_per_tc, u32 buffer)
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{
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aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TXBBUF_SIZE_ADR(buffer),
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@ -288,6 +288,9 @@ void hw_atl_reg_glb_cpu_scratch_scp_set(struct aq_hw_s *aq_hw,
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/* set dma system loopback */
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void hw_atl_rpb_dma_sys_lbk_set(struct aq_hw_s *aq_hw, u32 dma_sys_lbk);
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/* set dma network loopback */
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void hw_atl_rpb_dma_net_lbk_set(struct aq_hw_s *aq_hw, u32 dma_net_lbk);
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/* set rx traffic class mode */
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void hw_atl_rpb_rpf_rx_traf_class_mode_set(struct aq_hw_s *aq_hw,
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u32 rx_traf_class_mode);
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@ -629,6 +632,14 @@ void hw_atl_tpb_tx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw,
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/* set tx dma system loopback enable */
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void hw_atl_tpb_tx_dma_sys_lbk_en_set(struct aq_hw_s *aq_hw, u32 tx_dma_sys_lbk_en);
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/* set tx dma network loopback enable */
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void hw_atl_tpb_tx_dma_net_lbk_en_set(struct aq_hw_s *aq_hw,
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u32 tx_dma_net_lbk_en);
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/* set tx clock gating enable */
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void hw_atl_tpb_tx_tx_clk_gate_en_set(struct aq_hw_s *aq_hw,
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u32 tx_clk_gate_en);
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/* set tx packet buffer size (per tc) */
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void hw_atl_tpb_tx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw,
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u32 tx_pkt_buff_size_per_tc,
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@ -554,6 +554,24 @@
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/* default value of bitfield dma_sys_loopback */
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#define HW_ATL_RPB_DMA_SYS_LBK_DEFAULT 0x0
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/* rx dma_net_loopback bitfield definitions
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* preprocessor definitions for the bitfield "dma_net_loopback".
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* port="pif_rpb_dma_net_lbk_i"
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*/
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/* register address for bitfield dma_net_loopback */
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||||
#define HW_ATL_RPB_DMA_NET_LBK_ADR 0x00005000
|
||||
/* bitmask for bitfield dma_net_loopback */
|
||||
#define HW_ATL_RPB_DMA_NET_LBK_MSK 0x00000010
|
||||
/* inverted bitmask for bitfield dma_net_loopback */
|
||||
#define HW_ATL_RPB_DMA_NET_LBK_MSKN 0xffffffef
|
||||
/* lower bit position of bitfield dma_net_loopback */
|
||||
#define HW_ATL_RPB_DMA_NET_LBK_SHIFT 4
|
||||
/* width of bitfield dma_net_loopback */
|
||||
#define HW_ATL_RPB_DMA_NET_LBK_WIDTH 1
|
||||
/* default value of bitfield dma_net_loopback */
|
||||
#define HW_ATL_RPB_DMA_NET_LBK_DEFAULT 0x0
|
||||
|
||||
/* rx rx_tc_mode bitfield definitions
|
||||
* preprocessor definitions for the bitfield "rx_tc_mode".
|
||||
* port="pif_rpb_rx_tc_mode_i,pif_rpf_rx_tc_mode_i"
|
||||
|
|
@ -2107,6 +2125,24 @@
|
|||
/* default value of bitfield dma_sys_loopback */
|
||||
#define HW_ATL_TPB_DMA_SYS_LBK_DEFAULT 0x0
|
||||
|
||||
/* tx dma_net_loopback bitfield definitions
|
||||
* preprocessor definitions for the bitfield "dma_net_loopback".
|
||||
* port="pif_tpb_dma_net_lbk_i"
|
||||
*/
|
||||
|
||||
/* register address for bitfield dma_net_loopback */
|
||||
#define HW_ATL_TPB_DMA_NET_LBK_ADR 0x00007000
|
||||
/* bitmask for bitfield dma_net_loopback */
|
||||
#define HW_ATL_TPB_DMA_NET_LBK_MSK 0x00000010
|
||||
/* inverted bitmask for bitfield dma_net_loopback */
|
||||
#define HW_ATL_TPB_DMA_NET_LBK_MSKN 0xffffffef
|
||||
/* lower bit position of bitfield dma_net_loopback */
|
||||
#define HW_ATL_TPB_DMA_NET_LBK_SHIFT 4
|
||||
/* width of bitfield dma_net_loopback */
|
||||
#define HW_ATL_TPB_DMA_NET_LBK_WIDTH 1
|
||||
/* default value of bitfield dma_net_loopback */
|
||||
#define HW_ATL_TPB_DMA_NET_LBK_DEFAULT 0x0
|
||||
|
||||
/* tx tx{b}_buf_size[7:0] bitfield definitions
|
||||
* preprocessor definitions for the bitfield "tx{b}_buf_size[7:0]".
|
||||
* parameter: buffer {b} | stride size 0x10 | range [0, 7]
|
||||
|
|
@ -2144,6 +2180,24 @@
|
|||
/* default value of bitfield tx_scp_ins_en */
|
||||
#define HW_ATL_TPB_TX_SCP_INS_EN_DEFAULT 0x0
|
||||
|
||||
/* tx tx_clk_gate_en bitfield definitions
|
||||
* preprocessor definitions for the bitfield "tx_clk_gate_en".
|
||||
* port="pif_tpb_clk_gate_en_i"
|
||||
*/
|
||||
|
||||
/* register address for bitfield tx_clk_gate_en */
|
||||
#define HW_ATL_TPB_TX_CLK_GATE_EN_ADR 0x00007900
|
||||
/* bitmask for bitfield tx_clk_gate_en */
|
||||
#define HW_ATL_TPB_TX_CLK_GATE_EN_MSK 0x00000010
|
||||
/* inverted bitmask for bitfield tx_clk_gate_en */
|
||||
#define HW_ATL_TPB_TX_CLK_GATE_EN_MSKN 0xffffffef
|
||||
/* lower bit position of bitfield tx_clk_gate_en */
|
||||
#define HW_ATL_TPB_TX_CLK_GATE_EN_SHIFT 4
|
||||
/* width of bitfield tx_clk_gate_en */
|
||||
#define HW_ATL_TPB_TX_CLK_GATE_EN_WIDTH 1
|
||||
/* default value of bitfield tx_clk_gate_en */
|
||||
#define HW_ATL_TPB_TX_CLK_GATE_EN_DEFAULT 0x1
|
||||
|
||||
/* tx ipv4_chk_en bitfield definitions
|
||||
* preprocessor definitions for the bitfield "ipv4_chk_en".
|
||||
* port="pif_tpo_ipv4_chk_en_i"
|
||||
|
|
|
|||
|
|
@ -42,6 +42,9 @@
|
|||
#define HW_ATL_FW2X_CTRL_PAUSE BIT(CTRL_PAUSE)
|
||||
#define HW_ATL_FW2X_CTRL_TEMPERATURE BIT(CTRL_TEMPERATURE)
|
||||
#define HW_ATL_FW2X_CTRL_ASYMMETRIC_PAUSE BIT(CTRL_ASYMMETRIC_PAUSE)
|
||||
#define HW_ATL_FW2X_CTRL_INT_LOOPBACK BIT(CTRL_INT_LOOPBACK)
|
||||
#define HW_ATL_FW2X_CTRL_EXT_LOOPBACK BIT(CTRL_EXT_LOOPBACK)
|
||||
#define HW_ATL_FW2X_CTRL_DOWNSHIFT BIT(CTRL_DOWNSHIFT)
|
||||
#define HW_ATL_FW2X_CTRL_FORCE_RECONNECT BIT(CTRL_FORCE_RECONNECT)
|
||||
|
||||
#define HW_ATL_FW2X_CAP_EEE_1G_MASK BIT(CAPS_HI_1000BASET_FD_EEE)
|
||||
|
|
@ -53,6 +56,7 @@
|
|||
#define HAL_ATLANTIC_UTILS_FW2X_MSG_WOL 0x0E
|
||||
|
||||
#define HW_ATL_FW_VER_LED 0x03010026U
|
||||
#define HW_ATL_FW_VER_MEDIA_CONTROL 0x0301005aU
|
||||
|
||||
struct __packed fw2x_msg_wol_pattern {
|
||||
u8 mask[16];
|
||||
|
|
@ -539,6 +543,33 @@ static u32 aq_fw2x_get_flow_control(struct aq_hw_s *self, u32 *fcmode)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int aq_fw2x_set_phyloopback(struct aq_hw_s *self, u32 mode, bool enable)
|
||||
{
|
||||
u32 mpi_opts;
|
||||
|
||||
switch (mode) {
|
||||
case AQ_HW_LOOPBACK_PHYINT_SYS:
|
||||
mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
|
||||
if (enable)
|
||||
mpi_opts |= HW_ATL_FW2X_CTRL_INT_LOOPBACK;
|
||||
else
|
||||
mpi_opts &= ~HW_ATL_FW2X_CTRL_INT_LOOPBACK;
|
||||
aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
|
||||
break;
|
||||
case AQ_HW_LOOPBACK_PHYEXT_SYS:
|
||||
mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
|
||||
if (enable)
|
||||
mpi_opts |= HW_ATL_FW2X_CTRL_EXT_LOOPBACK;
|
||||
else
|
||||
mpi_opts &= ~HW_ATL_FW2X_CTRL_EXT_LOOPBACK;
|
||||
aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static u32 aq_fw2x_mbox_get(struct aq_hw_s *self)
|
||||
{
|
||||
return aq_hw_read_reg(self, HW_ATL_FW2X_MPI_MBOX_ADDR);
|
||||
|
|
@ -586,4 +617,5 @@ const struct aq_fw_ops aq_fw_2x_ops = {
|
|||
.send_fw_request = aq_fw2x_send_fw_request,
|
||||
.enable_ptp = aq_fw3x_enable_ptp,
|
||||
.led_control = aq_fw2x_led_control,
|
||||
.set_phyloopback = aq_fw2x_set_phyloopback,
|
||||
};
|
||||
|
|
|
|||
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