[MIPS] Dyntick support for SMTC:
The kernel currently only supports broadcasting of the timer interrupt from a single timer, not multicasting into two multicast groups of processors. So the implemented mechanism for SMTC works by broadcasting the cp0 compare interrupt on VPE 0 and ignoring it on any additional VPEs. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle
Родитель
7bcf7717b6
Коммит
ea5804015c
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@ -1368,6 +1368,7 @@ config MIPS_MT_SMTC
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depends on CPU_MIPS32_R2
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#depends on CPU_MIPS64_R2 # once there is hardware ...
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depends on SYS_SUPPORTS_MULTITHREADING
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select GENERIC_CLOCKEVENTS_BROADCAST
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select CPU_MIPSR2_IRQ_VI
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select CPU_MIPSR2_IRQ_EI
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select CPU_MIPSR2_SRS
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@ -1537,6 +1538,9 @@ config CPU_HAS_SYNC
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depends on !CPU_R3000
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default y
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config GENERIC_CLOCKEVENTS_BROADCAST
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bool
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#
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# Use the generic interrupt handling code in kernel/irq/:
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#
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@ -1,5 +1,6 @@
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/* Copyright (C) 2004 Mips Technologies, Inc */
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#include <linux/clockchips.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/cpumask.h>
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@ -62,7 +63,7 @@ asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS];
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* Clock interrupt "latch" buffers, per "CPU"
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*/
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unsigned int ipi_timer_latch[NR_CPUS];
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static atomic_t ipi_timer_latch[NR_CPUS];
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/*
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* Number of InterProcessor Interupt (IPI) message buffers to allocate
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@ -296,8 +297,10 @@ int __init mipsmt_build_cpu_map(int start_cpu_slot)
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__cpu_number_map[i] = i;
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__cpu_logical_map[i] = i;
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}
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#ifdef CONFIG_MIPS_MT_FPAFF
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/* Initialize map of CPUs with FPUs */
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cpus_clear(mt_fpu_cpumask);
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#endif
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/* One of those TC's is the one booting, and not a secondary... */
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printk("%i available secondary CPU TC(s)\n", i - 1);
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@ -359,7 +362,7 @@ void mipsmt_prepare_cpus(void)
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IPIQ[i].head = IPIQ[i].tail = NULL;
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spin_lock_init(&IPIQ[i].lock);
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IPIQ[i].depth = 0;
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ipi_timer_latch[i] = 0;
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atomic_set(&ipi_timer_latch[i], 0);
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}
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/* cpu_data index starts at zero */
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@ -482,10 +485,12 @@ void mipsmt_prepare_cpus(void)
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/* Set up coprocessor affinity CPU mask(s) */
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#ifdef CONFIG_MIPS_MT_FPAFF
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for (tc = 0; tc < ntc; tc++) {
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if (cpu_data[tc].options & MIPS_CPU_FPU)
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cpu_set(tc, mt_fpu_cpumask);
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}
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#endif
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/* set up ipi interrupts... */
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@ -702,7 +707,7 @@ static void smtc_ipi_qdump(void)
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* be done with the atomic.h primitives). And since this is
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* MIPS MT, we can assume that we have LL/SC.
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*/
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static __inline__ int atomic_postincrement(unsigned int *pv)
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static inline int atomic_postincrement(atomic_t *v)
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{
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unsigned long result;
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@ -714,8 +719,8 @@ static __inline__ int atomic_postincrement(unsigned int *pv)
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" sc %1, %2 \n"
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" beqz %1, 1b \n"
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__WEAK_LLSC_MB
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: "=&r" (result), "=&r" (temp), "=m" (*pv)
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: "m" (*pv)
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: "=&r" (result), "=&r" (temp), "=m" (v->counter)
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: "m" (v->counter)
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: "memory");
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return result;
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@ -743,6 +748,8 @@ void smtc_send_ipi(int cpu, int type, unsigned int action)
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pipi->arg = (void *)action;
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pipi->dest = cpu;
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if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) {
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if (type == SMTC_CLOCK_TICK)
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atomic_inc(&ipi_timer_latch[cpu]);
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/* If not on same VPE, enqueue and send cross-VPE interupt */
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smtc_ipi_nq(&IPIQ[cpu], pipi);
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LOCK_CORE_PRA();
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@ -784,6 +791,8 @@ void smtc_send_ipi(int cpu, int type, unsigned int action)
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}
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smtc_ipi_nq(&IPIQ[cpu], pipi);
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} else {
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if (type == SMTC_CLOCK_TICK)
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atomic_inc(&ipi_timer_latch[cpu]);
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post_direct_ipi(cpu, pipi);
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write_tc_c0_tchalt(0);
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UNLOCK_CORE_PRA();
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@ -801,6 +810,7 @@ static void post_direct_ipi(int cpu, struct smtc_ipi *pipi)
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unsigned long tcrestart;
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extern u32 kernelsp[NR_CPUS];
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extern void __smtc_ipi_vector(void);
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//printk("%s: on %d for %d\n", __func__, smp_processor_id(), cpu);
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/* Extract Status, EPC from halted TC */
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tcstatus = read_tc_c0_tcstatus();
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@ -851,25 +861,31 @@ static void ipi_call_interrupt(void)
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smp_call_function_interrupt();
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}
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DECLARE_PER_CPU(struct clock_event_device, smtc_dummy_clockevent_device);
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void ipi_decode(struct smtc_ipi *pipi)
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{
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unsigned int cpu = smp_processor_id();
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struct clock_event_device *cd;
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void *arg_copy = pipi->arg;
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int type_copy = pipi->type;
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int dest_copy = pipi->dest;
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int ticks;
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smtc_ipi_nq(&freeIPIq, pipi);
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switch (type_copy) {
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case SMTC_CLOCK_TICK:
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irq_enter();
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kstat_this_cpu.irqs[MIPS_CPU_IRQ_BASE + cp0_compare_irq]++;
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/* Invoke Clock "Interrupt" */
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ipi_timer_latch[dest_copy] = 0;
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#ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG
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clock_hang_reported[dest_copy] = 0;
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#endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */
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local_timer_interrupt(0, NULL);
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kstat_this_cpu.irqs[MIPS_CPU_IRQ_BASE + 1]++;
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cd = &per_cpu(smtc_dummy_clockevent_device, cpu);
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ticks = atomic_read(&ipi_timer_latch[cpu]);
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atomic_sub(ticks, &ipi_timer_latch[cpu]);
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while (ticks) {
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cd->event_handler(cd);
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ticks--;
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}
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irq_exit();
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break;
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case LINUX_SMP_IPI:
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switch ((int)arg_copy) {
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case SMP_RESCHEDULE_YOURSELF:
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@ -920,25 +936,6 @@ void deferred_smtc_ipi(void)
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}
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}
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/*
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* Send clock tick to all TCs except the one executing the funtion
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*/
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void smtc_timer_broadcast(void)
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{
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int cpu;
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int myTC = cpu_data[smp_processor_id()].tc_id;
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int myVPE = cpu_data[smp_processor_id()].vpe_id;
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smtc_cpu_stats[smp_processor_id()].timerints++;
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for_each_online_cpu(cpu) {
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if (cpu_data[cpu].vpe_id == myVPE &&
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cpu_data[cpu].tc_id != myTC)
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smtc_send_ipi(cpu, SMTC_CLOCK_TICK, 0);
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}
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}
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/*
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* Cross-VPE interrupts in the SMTC prototype use "software interrupts"
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* set via cross-VPE MTTR manipulation of the Cause register. It would be
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@ -1180,11 +1177,11 @@ void smtc_idle_loop_hook(void)
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for (tc = 0; tc < NR_CPUS; tc++) {
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/* Don't check ourself - we'll dequeue IPIs just below */
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if ((tc != smp_processor_id()) &&
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ipi_timer_latch[tc] > timerq_limit) {
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atomic_read(&ipi_timer_latch[tc]) > timerq_limit) {
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if (clock_hang_reported[tc] == 0) {
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pdb_msg += sprintf(pdb_msg,
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"TC %d looks hung with timer latch at %d\n",
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tc, ipi_timer_latch[tc]);
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tc, atomic_read(&ipi_timer_latch[tc]));
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clock_hang_reported[tc]++;
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}
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}
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@ -1225,7 +1222,7 @@ void smtc_soft_dump(void)
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smtc_ipi_qdump();
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printk("Timer IPI Backlogs:\n");
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for (i=0; i < NR_CPUS; i++) {
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printk("%d: %d\n", i, ipi_timer_latch[i]);
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printk("%d: %d\n", i, atomic_read(&ipi_timer_latch[i]));
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}
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printk("%d Recoveries of \"stolen\" FPU\n",
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atomic_read(&smtc_fpu_recoveries));
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@ -25,6 +25,7 @@
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/kallsyms.h>
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#include <asm/bootinfo.h>
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#include <asm/cache.h>
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@ -33,6 +34,7 @@
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#include <asm/cpu-features.h>
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#include <asm/div64.h>
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#include <asm/sections.h>
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#include <asm/smtc_ipi.h>
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#include <asm/time.h>
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#include <irq.h>
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@ -230,12 +232,24 @@ static int mips_next_event(unsigned long delta,
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struct clock_event_device *evt)
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{
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unsigned int cnt;
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int res;
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#ifdef CONFIG_MIPS_MT_SMTC
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{
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unsigned long flags, vpflags;
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local_irq_save(flags);
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vpflags = dvpe();
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#endif
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cnt = read_c0_count();
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cnt += delta;
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write_c0_compare(cnt);
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return ((long)(read_c0_count() - cnt ) > 0) ? -ETIME : 0;
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res = ((long)(read_c0_count() - cnt ) > 0) ? -ETIME : 0;
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#ifdef CONFIG_MIPS_MT_SMTC
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evpe(vpflags);
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local_irq_restore(flags);
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}
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#endif
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return res;
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}
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static void mips_set_mode(enum clock_event_mode mode,
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@ -244,9 +258,7 @@ static void mips_set_mode(enum clock_event_mode mode,
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/* Nothing to do ... */
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}
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struct clock_event_device mips_clockevent;
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static struct clock_event_device *global_cd[NR_CPUS];
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static DEFINE_PER_CPU(struct clock_event_device, mips_clockevent_device);
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static int cp0_timer_irq_installed;
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static irqreturn_t timer_interrupt(int irq, void *dev_id)
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@ -271,7 +283,12 @@ static irqreturn_t timer_interrupt(int irq, void *dev_id)
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*/
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if (!r2 || (read_c0_cause() & (1 << 30))) {
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c0_timer_ack();
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cd = global_cd[cpu];
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#ifdef CONFIG_MIPS_MT_SMTC
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if (cpu_data[cpu].vpe_id)
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goto out;
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cpu = 0;
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#endif
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cd = &per_cpu(mips_clockevent_device, cpu);
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cd->event_handler(cd);
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}
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@ -281,7 +298,11 @@ out:
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static struct irqaction timer_irqaction = {
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.handler = timer_interrupt,
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#ifdef CONFIG_MIPS_MT_SMTC
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.flags = IRQF_DISABLED,
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#else
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.flags = IRQF_DISABLED | IRQF_PERCPU,
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#endif
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.name = "timer",
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};
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@ -316,6 +337,60 @@ void __init __weak plat_timer_setup(struct irqaction *irq)
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{
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}
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#ifdef CONFIG_MIPS_MT_SMTC
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DEFINE_PER_CPU(struct clock_event_device, smtc_dummy_clockevent_device);
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static void smtc_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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}
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int dummycnt[NR_CPUS];
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static void mips_broadcast(cpumask_t mask)
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{
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unsigned int cpu;
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for_each_cpu_mask(cpu, mask)
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smtc_send_ipi(cpu, SMTC_CLOCK_TICK, 0);
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}
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static void setup_smtc_dummy_clockevent_device(void)
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{
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//uint64_t mips_freq = mips_hpt_^frequency;
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unsigned int cpu = smp_processor_id();
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struct clock_event_device *cd;
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cd = &per_cpu(smtc_dummy_clockevent_device, cpu);
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cd->name = "SMTC";
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cd->features = CLOCK_EVT_FEAT_DUMMY;
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/* Calculate the min / max delta */
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cd->mult = 0; //div_sc((unsigned long) mips_freq, NSEC_PER_SEC, 32);
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cd->shift = 0; //32;
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cd->max_delta_ns = 0; //clockevent_delta2ns(0x7fffffff, cd);
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cd->min_delta_ns = 0; //clockevent_delta2ns(0x30, cd);
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cd->rating = 200;
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cd->irq = 17; //-1;
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// if (cpu)
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// cd->cpumask = CPU_MASK_ALL; // cpumask_of_cpu(cpu);
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// else
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cd->cpumask = cpumask_of_cpu(cpu);
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cd->set_mode = smtc_set_mode;
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cd->broadcast = mips_broadcast;
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clockevents_register_device(cd);
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}
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#endif
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static void mips_event_handler(struct clock_event_device *dev)
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{
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}
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void __cpuinit mips_clockevent_init(void)
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{
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uint64_t mips_freq = mips_hpt_frequency;
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@ -326,12 +401,18 @@ void __cpuinit mips_clockevent_init(void)
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if (!cpu_has_counter)
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return;
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if (cpu == 0)
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cd = &mips_clockevent;
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else
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cd = kzalloc(sizeof(*cd), GFP_ATOMIC);
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if (!cd)
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return; /* We're probably roadkill ... */
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#ifdef CONFIG_MIPS_MT_SMTC
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setup_smtc_dummy_clockevent_device();
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/*
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* On SMTC we only register VPE0's compare interrupt as clockevent
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* device.
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*/
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if (cpu)
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return;
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#endif
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cd = &per_cpu(mips_clockevent_device, cpu);
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cd->name = "MIPS";
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cd->features = CLOCK_EVT_FEAT_ONESHOT;
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@ -344,11 +425,15 @@ void __cpuinit mips_clockevent_init(void)
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cd->rating = 300;
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cd->irq = irq;
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#ifdef CONFIG_MIPS_MT_SMTC
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cd->cpumask = CPU_MASK_ALL;
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#else
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cd->cpumask = cpumask_of_cpu(cpu);
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#endif
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cd->set_next_event = mips_next_event;
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cd->set_mode = mips_set_mode;
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cd->event_handler = mips_event_handler;
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global_cd[cpu] = cd;
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clockevents_register_device(cd);
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if (!cp0_timer_irq_installed) {
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@ -55,7 +55,6 @@ unsigned long cpu_khz;
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static int mips_cpu_timer_irq;
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extern int cp0_perfcount_irq;
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extern void smtc_timer_broadcast(void);
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static void mips_timer_dispatch(void)
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{
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