pinctrl: cygnus: Remove GPIO to Pinctrl pin mapping from driver
Remove gpio to pinctrl pin mapping code from driver and address this through standard property "gpio-ranges". Signed-off-by: Pramod Kumar <pramodku@broadcom.com> Reviewed-by: Ray Jui <rjui@broadcom.com> Reviewed-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Pramod Kumar
Linus Walleij
Родитель
03e09bc185
Коммит
ea92211c08
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@ -29,7 +29,6 @@
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinmux.h>
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#include <linux/pinctrl/pinconf.h>
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#include <linux/pinctrl/pinconf-generic.h>
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@ -596,127 +595,6 @@ static const struct pinconf_ops cygnus_pconf_ops = {
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.pin_config_set = cygnus_pin_config_set,
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};
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/*
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* Map a GPIO in the local gpio_chip pin space to a pin in the Cygnus IOMUX
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* pinctrl pin space
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*/
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struct cygnus_gpio_pin_range {
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unsigned offset;
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unsigned pin_base;
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unsigned num_pins;
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};
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#define CYGNUS_PINRANGE(o, p, n) { .offset = o, .pin_base = p, .num_pins = n }
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/*
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* Pin mapping table for mapping local GPIO pins to Cygnus IOMUX pinctrl pins
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*/
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static const struct cygnus_gpio_pin_range cygnus_gpio_pintable[] = {
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CYGNUS_PINRANGE(0, 42, 1),
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CYGNUS_PINRANGE(1, 44, 3),
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CYGNUS_PINRANGE(4, 48, 1),
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CYGNUS_PINRANGE(5, 50, 3),
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CYGNUS_PINRANGE(8, 126, 1),
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CYGNUS_PINRANGE(9, 155, 1),
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CYGNUS_PINRANGE(10, 152, 1),
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CYGNUS_PINRANGE(11, 154, 1),
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CYGNUS_PINRANGE(12, 153, 1),
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CYGNUS_PINRANGE(13, 127, 3),
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CYGNUS_PINRANGE(16, 140, 1),
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CYGNUS_PINRANGE(17, 145, 7),
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CYGNUS_PINRANGE(24, 130, 10),
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CYGNUS_PINRANGE(34, 141, 4),
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CYGNUS_PINRANGE(38, 54, 1),
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CYGNUS_PINRANGE(39, 56, 3),
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CYGNUS_PINRANGE(42, 60, 3),
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CYGNUS_PINRANGE(45, 64, 3),
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CYGNUS_PINRANGE(48, 68, 2),
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CYGNUS_PINRANGE(50, 84, 6),
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CYGNUS_PINRANGE(56, 94, 6),
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CYGNUS_PINRANGE(62, 72, 1),
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CYGNUS_PINRANGE(63, 70, 1),
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CYGNUS_PINRANGE(64, 80, 1),
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CYGNUS_PINRANGE(65, 74, 3),
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CYGNUS_PINRANGE(68, 78, 1),
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CYGNUS_PINRANGE(69, 82, 1),
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CYGNUS_PINRANGE(70, 156, 17),
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CYGNUS_PINRANGE(87, 104, 12),
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CYGNUS_PINRANGE(99, 102, 2),
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CYGNUS_PINRANGE(101, 90, 4),
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CYGNUS_PINRANGE(105, 116, 6),
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CYGNUS_PINRANGE(111, 100, 2),
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CYGNUS_PINRANGE(113, 122, 4),
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CYGNUS_PINRANGE(123, 11, 1),
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CYGNUS_PINRANGE(124, 38, 4),
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CYGNUS_PINRANGE(128, 43, 1),
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CYGNUS_PINRANGE(129, 47, 1),
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CYGNUS_PINRANGE(130, 49, 1),
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CYGNUS_PINRANGE(131, 53, 1),
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CYGNUS_PINRANGE(132, 55, 1),
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CYGNUS_PINRANGE(133, 59, 1),
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CYGNUS_PINRANGE(134, 63, 1),
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CYGNUS_PINRANGE(135, 67, 1),
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CYGNUS_PINRANGE(136, 71, 1),
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CYGNUS_PINRANGE(137, 73, 1),
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CYGNUS_PINRANGE(138, 77, 1),
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CYGNUS_PINRANGE(139, 79, 1),
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CYGNUS_PINRANGE(140, 81, 1),
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CYGNUS_PINRANGE(141, 83, 1),
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CYGNUS_PINRANGE(142, 10, 1)
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};
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/*
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* The Cygnus IOMUX controller mainly supports group based mux configuration,
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* but certain pins can be muxed to GPIO individually. Only the ASIU GPIO
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* controller can support this, so it's an optional configuration
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*
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* Return -ENODEV means no support and that's fine
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*/
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static int cygnus_gpio_pinmux_add_range(struct cygnus_gpio *chip)
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{
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struct device_node *node = chip->dev->of_node;
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struct device_node *pinmux_node;
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struct platform_device *pinmux_pdev;
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struct gpio_chip *gc = &chip->gc;
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int i, ret = 0;
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/* parse DT to find the phandle to the pinmux controller */
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pinmux_node = of_parse_phandle(node, "pinmux", 0);
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if (!pinmux_node)
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return -ENODEV;
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pinmux_pdev = of_find_device_by_node(pinmux_node);
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/* no longer need the pinmux node */
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of_node_put(pinmux_node);
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if (!pinmux_pdev) {
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dev_err(chip->dev, "failed to get pinmux device\n");
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return -EINVAL;
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}
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/* now need to create the mapping between local GPIO and PINMUX pins */
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for (i = 0; i < ARRAY_SIZE(cygnus_gpio_pintable); i++) {
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ret = gpiochip_add_pin_range(gc, dev_name(&pinmux_pdev->dev),
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cygnus_gpio_pintable[i].offset,
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cygnus_gpio_pintable[i].pin_base,
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cygnus_gpio_pintable[i].num_pins);
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if (ret) {
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dev_err(chip->dev, "unable to add GPIO pin range\n");
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goto err_put_device;
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}
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}
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chip->pinmux_is_supported = true;
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/* no need for pinmux_pdev device reference anymore */
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put_device(&pinmux_pdev->dev);
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return 0;
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err_put_device:
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put_device(&pinmux_pdev->dev);
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gpiochip_remove_pin_ranges(gc);
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return ret;
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}
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/*
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* Cygnus GPIO controller supports some PINCONF related configurations such as
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* pull up, pull down, and drive strength, when the pin is configured to GPIO
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@ -851,18 +729,15 @@ static int cygnus_gpio_probe(struct platform_device *pdev)
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gc->set = cygnus_gpio_set;
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gc->get = cygnus_gpio_get;
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chip->pinmux_is_supported = of_property_read_bool(dev->of_node,
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"gpio-ranges");
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ret = gpiochip_add(gc);
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if (ret < 0) {
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dev_err(dev, "unable to add GPIO chip\n");
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return ret;
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}
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ret = cygnus_gpio_pinmux_add_range(chip);
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if (ret && ret != -ENODEV) {
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dev_err(dev, "unable to add GPIO pin range\n");
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goto err_rm_gpiochip;
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}
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ret = cygnus_gpio_register_pinconf(chip);
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if (ret) {
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dev_err(dev, "unable to register pinconf\n");
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