[ARM] 3952/1: AT91: Hardware headers for SAM9 perhipherals
This patch adds definitions for the new peripherals integrated in the AT91SAM9260 and AT91SAM9261 processors: ECC, LCD, RSTC, RTT, SHDWC, WDT, MATRIX, SDRAMC, SMC. Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Andrew Victor
Russell King
Родитель
55d8baee4a
Коммит
eaa595cb88
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/*
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* include/asm-arm/arch-at91rm9200/at91_ecc.h
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*
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* Error Corrected Code Controller (ECC) - System peripherals regsters.
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* Based on AT91SAM9260 datasheet revision B.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef AT91_ECC_H
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#define AT91_ECC_H
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#define AT91_ECC_CR (AT91_ECC + 0x00) /* Control register */
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#define AT91_ECC_RST (1 << 0) /* Reset parity */
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#define AT91_ECC_MR (AT91_ECC + 0x04) /* Mode register */
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#define AT91_ECC_PAGESIZE (3 << 0) /* Page Size */
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#define AT91_ECC_PAGESIZE_528 (0)
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#define AT91_ECC_PAGESIZE_1056 (1)
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#define AT91_ECC_PAGESIZE_2112 (2)
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#define AT91_ECC_PAGESIZE_4224 (3)
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#define AT91_ECC_SR (AT91_ECC + 0x08) /* Status register */
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#define AT91_ECC_RECERR (1 << 0) /* Recoverable Error */
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#define AT91_ECC_ECCERR (1 << 1) /* ECC Single Bit Error */
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#define AT91_ECC_MULERR (1 << 2) /* Multiple Errors */
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#define AT91_ECC_PR (AT91_ECC + 0x0c) /* Parity register */
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#define AT91_ECC_BITADDR (0xf << 0) /* Bit Error Address */
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#define AT91_ECC_WORDADDR (0xfff << 4) /* Word Error Address */
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#define AT91_ECC_NPR (AT91_ECC + 0x10) /* NParity register */
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#define AT91_ECC_NPARITY (0xffff << 0) /* NParity */
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#endif
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/*
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* include/asm-arm/arch-at91rm9200/at91_lcdc.h
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*
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* LCD Controller (LCDC).
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* Based on AT91SAM9261 datasheet revision E.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef AT91_LCDC_H
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#define AT91_LCDC_H
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#define AT91_LCDC_DMABADDR1 0x00 /* DMA Base Address Register 1 */
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#define AT91_LCDC_DMABADDR2 0x04 /* DMA Base Address Register 2 */
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#define AT91_LCDC_DMAFRMPT1 0x08 /* DMA Frame Pointer Register 1 */
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#define AT91_LCDC_DMAFRMPT2 0x0c /* DMA Frame Pointer Register 2 */
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#define AT91_LCDC_DMAFRMADD1 0x10 /* DMA Frame Address Register 1 */
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#define AT91_LCDC_DMAFRMADD2 0x14 /* DMA Frame Address Register 2 */
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#define AT91_LCDC_DMAFRMCFG 0x18 /* DMA Frame Configuration Register */
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#define AT91_LCDC_FRSIZE (0x7fffff << 0) /* Frame Size */
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#define AT91_LCDC_BLENGTH (0x7f << 24) /* Burst Length */
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#define AT91_LCDC_DMACON 0x1c /* DMA Control Register */
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#define AT91_LCDC_DMAEN (0x1 << 0) /* DMA Enable */
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#define AT91_LCDC_DMARST (0x1 << 1) /* DMA Reset */
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#define AT91_LCDC_DMABUSY (0x1 << 2) /* DMA Busy */
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#define AT91_LCDC_LCDCON1 0x0800 /* LCD Control Register 1 */
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#define AT91_LCDC_BYPASS (1 << 0) /* Bypass lcd_dotck divider */
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#define AT91_LCDC_CLKVAL (0x1ff << 12) /* Clock Divider */
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#define AT91_LCDC_LINCNT (0x7ff << 21) /* Line Counter */
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#define AT91_LCDC_LCDCON2 0x0804 /* LCD Control Register 2 */
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#define AT91_LCDC_DISTYPE (3 << 0) /* Display Type */
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#define AT91_LCDC_DISTYPE_STNMONO (0 << 0)
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#define AT91_LCDC_DISTYPE_STNCOLOR (1 << 0)
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#define AT91_LCDC_DISTYPE_TFT (2 << 0)
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#define AT91_LCDC_SCANMOD (1 << 2) /* Scan Mode */
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#define AT91_LCDC_SCANMOD_SINGLE (0 << 2)
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#define AT91_LCDC_SCANMOD_DUAL (1 << 2)
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#define AT91_LCDC_IFWIDTH (3 << 3) /*Interface Width */
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#define AT91_LCDC_IFWIDTH_4 (0 << 3)
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#define AT91_LCDC_IFWIDTH_8 (1 << 3)
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#define AT91_LCDC_IFWIDTH_16 (2 << 3)
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#define AT91_LCDC_PIXELSIZE (7 << 5) /* Bits per pixel */
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#define AT91_LCDC_PIXELSIZE_1 (0 << 5)
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#define AT91_LCDC_PIXELSIZE_2 (1 << 5)
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#define AT91_LCDC_PIXELSIZE_4 (2 << 5)
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#define AT91_LCDC_PIXELSIZE_8 (3 << 5)
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#define AT91_LCDC_PIXELSIZE_16 (4 << 5)
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#define AT91_LCDC_PIXELSIZE_24 (5 << 5)
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#define AT91_LCDC_INVVD (1 << 8) /* LCD Data polarity */
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#define AT91_LCDC_INVVD_NORMAL (0 << 8)
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#define AT91_LCDC_INVVD_INVERTED (1 << 8)
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#define AT91_LCDC_INVFRAME (1 << 9 ) /* LCD VSync polarity */
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#define AT91_LCDC_INVFRAME_NORMAL (0 << 9)
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#define AT91_LCDC_INVFRAME_INVERTED (1 << 9)
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#define AT91_LCDC_INVLINE (1 << 10) /* LCD HSync polarity */
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#define AT91_LCDC_INVLINE_NORMAL (0 << 10)
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#define AT91_LCDC_INVLINE_INVERTED (1 << 10)
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#define AT91_LCDC_INVCLK (1 << 11) /* LCD dotclk polarity */
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#define AT91_LCDC_INVCLK_NORMAL (0 << 11)
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#define AT91_LCDC_INVCLK_INVERTED (1 << 11)
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#define AT91_LCDC_INVDVAL (1 << 12) /* LCD dval polarity */
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#define AT91_LCDC_INVDVAL_NORMAL (0 << 12)
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#define AT91_LCDC_INVDVAL_INVERTED (1 << 12)
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#define AT91_LCDC_CLKMOD (1 << 15) /* LCD dotclk mode */
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#define AT91_LCDC_CLKMOD_ACTIVEDISPLAY (0 << 15)
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#define AT91_LCDC_CLKMOD_ALWAYSACTIVE (1 << 15)
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#define AT91_LCDC_MEMOR (1 << 31) /* Memory Ordering Format */
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#define AT91_LCDC_MEMOR_BIG (0 << 31)
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#define AT91_LCDC_MEMOR_LITTLE (1 << 31)
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#define AT91_LCDC_TIM1 0x0808 /* LCD Timing Register 1 */
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#define AT91_LCDC_VFP (0xff << 0) /* Vertical Front Porch */
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#define AT91_LCDC_VBP (0xff << 8) /* Vertical Back Porch */
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#define AT91_LCDC_VPW (0x3f << 16) /* Vertical Synchronization Pulse Width */
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#define AT91_LCDC_VHDLY (0xf << 24) /* Vertical to Horizontal Delay */
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#define AT91_LCDC_TIM2 0x080c /* LCD Timing Register 2 */
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#define AT91_LCDC_HBP (0xff << 0) /* Horizontal Back Porch */
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#define AT91_LCDC_HPW (0x3f << 8) /* Horizontal Synchronization Pulse Width */
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#define AT91_LCDC_HFP (0x7ff << 21) /* Horizontal Front Porch */
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#define AT91_LCDC_LCDFRMCFG 0x0810 /* LCD Frame Configuration Register */
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#define AT91_LCDC_LINEVAL (0x7ff << 0) /* Vertical Size of LCD Module */
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#define AT91_LCDC_HOZVAL (0x7ff << 21) /* Horizontal Size of LCD Module */
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#define AT91_LCDC_FIFO 0x0814 /* LCD FIFO Register */
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#define AT91_LCDC_FIFOTH (0xffff) /* FIFO Threshold */
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#define AT91_LCDC_DP1_2 0x081c /* Dithering Pattern DP1_2 Register */
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#define AT91_LCDC_DP4_7 0x0820 /* Dithering Pattern DP4_7 Register */
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#define AT91_LCDC_DP3_5 0x0824 /* Dithering Pattern DP3_5 Register */
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#define AT91_LCDC_DP2_3 0x0828 /* Dithering Pattern DP2_3 Register */
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#define AT91_LCDC_DP5_7 0x082c /* Dithering Pattern DP5_7 Register */
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#define AT91_LCDC_DP3_4 0x0830 /* Dithering Pattern DP3_4 Register */
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#define AT91_LCDC_DP4_5 0x0834 /* Dithering Pattern DP4_5 Register */
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#define AT91_LCDC_DP6_7 0x0838 /* Dithering Pattern DP6_7 Register */
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#define AT91_LCDC_DP1_2_VAL (0xff)
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#define AT91_LCDC_DP4_7_VAL (0xfffffff)
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#define AT91_LCDC_DP3_5_VAL (0xfffff)
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#define AT91_LCDC_DP2_3_VAL (0xfff)
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#define AT91_LCDC_DP5_7_VAL (0xfffffff)
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#define AT91_LCDC_DP3_4_VAL (0xffff)
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#define AT91_LCDC_DP4_5_VAL (0xfffff)
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#define AT91_LCDC_DP6_7_VAL (0xfffffff)
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#define AT91_LCDC_PWRCON 0x083c /* Power Control Register */
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#define AT91_LCDC_PWR (1 << 0) /* LCD Module Power Control */
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#define AT91_LCDC_GUARDT (0x7f << 1) /* Delay in Frame Period */
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#define AT91_LCDC_BUSY (1 << 31) /* LCD Busy */
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#define AT91_LCDC_CONTRAST_CTR 0x0840 /* Contrast Control Register */
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#define AT91_LCDC_PS (3 << 0) /* Contrast Counter Prescaler */
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#define AT91_LCDC_PS_DIV1 (0 << 0)
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#define AT91_LCDC_PS_DIV2 (1 << 0)
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#define AT91_LCDC_PS_DIV4 (2 << 0)
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#define AT91_LCDC_PS_DIV8 (3 << 0)
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#define AT91_LCDC_POL (1 << 2) /* Polarity of output Pulse */
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#define AT91_LCDC_POL_NEGATIVE (0 << 2)
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#define AT91_LCDC_POL_POSITIVE (1 << 2)
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#define AT91_LCDC_ENA (1 << 3) /* PWM generator Control */
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#define AT91_LCDC_ENA_PWMDISABLE (0 << 3)
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#define AT91_LCDC_ENA_PWMENABLE (1 << 3)
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#define AT91_LCDC_CONTRAST_VAL 0x0844 /* Contrast Value Register */
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#define AT91_LCDC_CVAL (0xff) /* PWM compare value */
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#define AT91_LCDC_IER 0x0848 /* Interrupt Enable Register */
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#define AT91_LCDC_IDR 0x084c /* Interrupt Disable Register */
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#define AT91_LCDC_IMR 0x0850 /* Interrupt Mask Register */
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#define AT91_LCDC_ISR 0x0854 /* Interrupt Enable Register */
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#define AT91_LCDC_ICR 0x0858 /* Interrupt Clear Register */
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#define AT91_LCDC_LNI (1 << 0) /* Line Interrupt */
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#define AT91_LCDC_LSTLNI (1 << 1) /* Last Line Interrupt */
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#define AT91_LCDC_EOFI (1 << 2) /* DMA End Of Frame Interrupt */
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#define AT91_LCDC_UFLWI (1 << 4) /* FIFO Underflow Interrupt */
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#define AT91_LCDC_OWRI (1 << 5) /* FIFO Overwrite Interrupt */
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#define AT91_LCDC_MERI (1 << 6) /* DMA Memory Error Interrupt */
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#define AT91_LCDC_LUT_(n) (0x0c00 + ((n)*4)) /* Palette Entry 0..255 */
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#endif
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/*
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* include/asm-arm/arch-at91rm9200/at91_rstc.h
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*
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* Reset Controller (RSTC) - System peripherals regsters.
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* Based on AT91SAM9261 datasheet revision D.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef AT91_RSTC_H
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#define AT91_RSTC_H
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#define AT91_RSTC_CR (AT91_RSTC + 0x00) /* Reset Controller Control Register */
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#define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */
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#define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */
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#define AT91_RSTC_EXTRST (1 << 3) /* External Reset */
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#define AT01_RSTC_KEY (0xff << 24) /* KEY Password */
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#define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */
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#define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */
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#define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */
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#define AT91_RSTC_RSTTYP_GENERAL (0 << 8)
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#define AT91_RSTC_RSTTYP_WAKEUP (1 << 8)
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#define AT91_RSTC_RSTTYP_WATCHDOG (2 << 8)
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#define AT91_RSTC_RSTTYP_SOFTWARE (3 << 8)
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#define AT91_RSTC_RSTTYP_USER (4 << 8)
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#define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */
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#define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */
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#define AT91_RSTC_MR (AT91_RSTC + 0x08) /* Reset Controller Mode Register */
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#define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */
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#define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */
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#define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */
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#define AT91_RSTC_KEY (0xff << 24) /* KEY Password */
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#endif
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/*
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* include/asm-arm/arch-at91rm9200/at91_rtt.h
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*
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* Real-time Timer (RTT) - System peripherals regsters.
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* Based on AT91SAM9261 datasheet revision D.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef AT91_RTT_H
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#define AT91_RTT_H
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#define AT91_RTT_MR (AT91_RTT + 0x00) /* Real-time Mode Register */
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#define AT91_RTT_RTPRES (0xffff << 0) /* Real-time Timer Prescaler Value */
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#define AT91_RTT_ALMIEN (1 << 16) /* Alarm Interrupt Enable */
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#define AT91_RTT_RTTINCIEN (1 << 17) /* Real Time Timer Increment Interrupt Enable */
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#define AT91_RTT_RTTRST (1 << 18) /* Real Time Timer Restart */
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#define AT91_RTT_AR (AT91_RTT + 0x04) /* Real-time Alarm Register */
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#define AT91_RTT_ALMV (0xffffffff) /* Alarm Value */
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#define AT91_RTT_VR (AT91_RTT + 0x08) /* Real-time Value Register */
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#define AT91_RTT_CRTV (0xffffffff) /* Current Real-time Value */
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#define AT91_RTT_SR (AT91_RTT + 0x0c) /* Real-time Status Register */
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#define AT91_RTT_ALMS (1 << 0) /* Real-time Alarm Status */
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#define AT91_RTT_RTTINC (1 << 1) /* Real-time Timer Increment */
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#endif
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@ -0,0 +1,33 @@
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/*
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* include/asm-arm/arch-at91rm9200/at91_shdwc.h
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*
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* Shutdown Controller (SHDWC) - System peripherals regsters.
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* Based on AT91SAM9261 datasheet revision D.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef AT91_SHDWC_H
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#define AT91_SHDWC_H
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#define AT91_SHDW_CR (AT91_SHDWC + 0x00) /* Shut Down Control Register */
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#define AT91_SHDW_SHDW (1 << 0) /* Processor Reset */
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#define AT91_SHDW_KEY (0xff << 24) /* KEY Password */
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#define AT91_SHDW_MR (AT91_SHDWC + 0x04) /* Shut Down Mode Register */
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#define AT91_SHDW_WKMODE0 (3 << 0) /* Wake-up 0 Mode Selection */
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#define AT91_SHDW_WKMODE0_NONE 0
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#define AT91_SHDW_WKMODE0_HIGH 1
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#define AT91_SHDW_WKMODE0_LOW 2
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#define AT91_SHDW_WKMODE0_ANYLEVEL 3
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#define AT91_SHDW_CPTWK0 (0xf << 4) /* Counter On Wake Up 0 */
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#define AT91_SHDW_RTTWKEN (1 << 16) /* Real Time Timer Wake-up Enable */
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#define AT91_SHDW_SR (AT91_SHDWC + 0x08) /* Shut Down Status Register */
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#define AT91_SHDW_WAKEUP0 (1 << 0) /* Wake-up 0 Status */
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#define AT91_SHDW_RTTWK (1 << 16) /* Real-time Timer Wake-up */
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#endif
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@ -0,0 +1,34 @@
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/*
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* include/asm-arm/arch-at91rm9200/at91_wdt.h
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*
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* Watchdog Timer (WDT) - System peripherals regsters.
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* Based on AT91SAM9261 datasheet revision D.
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*
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* This program is free software; you can redistribute it and/or modify
|
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* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
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*/
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#ifndef AT91_WDT_H
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#define AT91_WDT_H
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#define AT91_WDT_CR (AT91_WDT + 0x00) /* Watchdog Control Register */
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#define AT91_WDT_WDRSTT (1 << 0) /* Restart */
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#define AT91_WDT_KEY (0xff << 24) /* KEY Password */
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#define AT91_WDT_MR (AT91_WDT + 0x04) /* Watchdog Mode Register */
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#define AT91_WDT_WDV (0xfff << 0) /* Counter Value */
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#define AT91_WDT_WDFIEN (1 << 12) /* Fault Interrupt Enable */
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#define AT91_WDT_WDRSTEN (1 << 13) /* Reset Processor */
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#define AT91_WDT_WDRPROC (1 << 14) /* Timer Restart */
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#define AT91_WDT_WDDIS (1 << 15) /* Watchdog Disable */
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#define AT91_WDT_WDD (0xfff << 16) /* Delta Value */
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#define AT91_WDT_WDDBGHLT (1 << 28) /* Debug Halt */
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#define AT91_WDT_WDIDLEHLT (1 << 29) /* Idle Halt */
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#define AT91_WDT_SR (AT91_WDT + 0x08) /* Watchdog Status Register */
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#define AT91_WDT_WDUNF (1 << 0) /* Watchdog Underflow */
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#define AT91_WDT_WDERR (1 << 1) /* Watchdog Error */
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#endif
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@ -0,0 +1,78 @@
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/*
|
||||
* include/asm-arm/arch-at91rm9200/at91sam9260_matrix.h
|
||||
*
|
||||
* Memory Controllers (MATRIX, EBI) - System peripherals registers.
|
||||
* Based on AT91SAM9260 datasheet revision B.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef AT91SAM9260_MATRIX_H
|
||||
#define AT91SAM9260_MATRIX_H
|
||||
|
||||
#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
|
||||
#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
|
||||
#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
|
||||
#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
|
||||
#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
|
||||
#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x04) /* Master Configuration Register 5 */
|
||||
#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
|
||||
#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
|
||||
#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
|
||||
#define AT91_MATRIX_ULBT_FOUR (2 << 0)
|
||||
#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
|
||||
#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
|
||||
|
||||
#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
|
||||
#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
|
||||
#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
|
||||
#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
|
||||
#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
|
||||
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
|
||||
#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
|
||||
#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
|
||||
#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
|
||||
#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
|
||||
|
||||
#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
|
||||
#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
|
||||
#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
|
||||
#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
|
||||
#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
|
||||
#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
|
||||
#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
|
||||
#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
|
||||
#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
|
||||
#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
|
||||
#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
|
||||
|
||||
#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
|
||||
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
|
||||
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
|
||||
|
||||
#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x11C) /* EBI Chip Select Assignment Register */
|
||||
#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
|
||||
#define AT91_MATRIX_CS1A_SMC (0 << 1)
|
||||
#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
|
||||
#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
|
||||
#define AT91_MATRIX_CS3A_SMC (0 << 3)
|
||||
#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
|
||||
#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
|
||||
#define AT91_MATRIX_CS4A_SMC (0 << 4)
|
||||
#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
|
||||
#define AT91_MATRIX_CS5A (1 << 5 ) /* Chip Select 5 Assignment */
|
||||
#define AT91_MATRIX_CS5A_SMC (0 << 5)
|
||||
#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
|
||||
#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
|
||||
#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */
|
||||
#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16)
|
||||
#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16)
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,62 @@
|
|||
/*
|
||||
* include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h
|
||||
*
|
||||
* Memory Controllers (MATRIX, EBI) - System peripherals registers.
|
||||
* Based on AT91SAM9261 datasheet revision D.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef AT91SAM9261_MATRIX_H
|
||||
#define AT91SAM9261_MATRIX_H
|
||||
|
||||
#define AT91_MATRIX_MCFG (AT91_MATRIX + 0x00) /* Master Configuration Register */
|
||||
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
|
||||
#define AT01_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
|
||||
|
||||
#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x04) /* Slave Configuration Register 0 */
|
||||
#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x08) /* Slave Configuration Register 1 */
|
||||
#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x0C) /* Slave Configuration Register 2 */
|
||||
#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x10) /* Slave Configuration Register 3 */
|
||||
#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x14) /* Slave Configuration Register 4 */
|
||||
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
|
||||
#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
|
||||
|
||||
#define AT91_MATRIX_TCR (AT91_MATRIX + 0x24) /* TCM Configuration Register */
|
||||
#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
|
||||
#define AT91_MATRIX_ITCM_0 (0 << 0)
|
||||
#define AT91_MATRIX_ITCM_16 (5 << 0)
|
||||
#define AT91_MATRIX_ITCM_32 (6 << 0)
|
||||
#define AT91_MATRIX_ITCM_64 (7 << 0)
|
||||
#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
|
||||
#define AT91_MATRIX_DTCM_0 (0 << 4)
|
||||
#define AT91_MATRIX_DTCM_16 (5 << 4)
|
||||
#define AT91_MATRIX_DTCM_32 (6 << 4)
|
||||
#define AT91_MATRIX_DTCM_64 (7 << 4)
|
||||
|
||||
#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x30) /* EBI Chip Select Assignment Register */
|
||||
#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
|
||||
#define AT91_MATRIX_CS1A_SMC (0 << 1)
|
||||
#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
|
||||
#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
|
||||
#define AT91_MATRIX_CS3A_SMC (0 << 3)
|
||||
#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
|
||||
#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
|
||||
#define AT91_MATRIX_CS4A_SMC (0 << 4)
|
||||
#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
|
||||
#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
|
||||
#define AT91_MATRIX_CS5A_SMC (0 << 5)
|
||||
#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
|
||||
#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
|
||||
|
||||
#define AT91_MATRIX_USBPUCR (AT91_MATRIX + 0x34) /* USB Pad Pull-Up Control Register */
|
||||
#define AT91_MATRIX_USBPUCR_PUON (1 << 30) /* USB Device PAD Pull-up Enable */
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,134 @@
|
|||
/*
|
||||
* include/asm-arm/arch-at91rm9200/at91sam926x_mc.h
|
||||
*
|
||||
* Memory Controllers (SMC, SDRAMC) - System peripherals registers.
|
||||
* Based on AT91SAM9261 datasheet revision D.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef AT91SAM926x_MC_H
|
||||
#define AT91SAM926x_MC_H
|
||||
|
||||
/* SDRAM Controller (SDRAMC) registers */
|
||||
#define AT91_SDRAMC_MR (AT91_SDRAMC + 0x00) /* SDRAM Controller Mode Register */
|
||||
#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */
|
||||
#define AT91_SDRAMC_MODE_NORMAL 0
|
||||
#define AT91_SDRAMC_MODE_NOP 1
|
||||
#define AT91_SDRAMC_MODE_PRECHARGE 2
|
||||
#define AT91_SDRAMC_MODE_LMR 3
|
||||
#define AT91_SDRAMC_MODE_REFRESH 4
|
||||
#define AT91_SDRAMC_MODE_EXT_LMR 5
|
||||
#define AT91_SDRAMC_MODE_DEEP 6
|
||||
|
||||
#define AT91_SDRAMC_TR (AT91_SDRAMC + 0x04) /* SDRAM Controller Refresh Timer Register */
|
||||
#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */
|
||||
|
||||
#define AT91_SDRAMC_CR (AT91_SDRAMC + 0x08) /* SDRAM Controller Configuration Register */
|
||||
#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */
|
||||
#define AT91_SDRAMC_NC_8 (0 << 0)
|
||||
#define AT91_SDRAMC_NC_9 (1 << 0)
|
||||
#define AT91_SDRAMC_NC_10 (2 << 0)
|
||||
#define AT91_SDRAMC_NC_11 (3 << 0)
|
||||
#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */
|
||||
#define AT91_SDRAMC_NR_11 (0 << 2)
|
||||
#define AT91_SDRAMC_NR_12 (1 << 2)
|
||||
#define AT91_SDRAMC_NR_13 (2 << 2)
|
||||
#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */
|
||||
#define AT91_SDRAMC_NB_2 (0 << 4)
|
||||
#define AT91_SDRAMC_NB_4 (1 << 4)
|
||||
#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */
|
||||
#define AT91_SDRAMC_CAS_1 (1 << 5)
|
||||
#define AT91_SDRAMC_CAS_2 (2 << 5)
|
||||
#define AT91_SDRAMC_CAS_3 (3 << 5)
|
||||
#define AT91_SDRAMC_DBW (1 << 7) /* Data Bus Width */
|
||||
#define AT91_SDRAMC_DBW_32 (0 << 7)
|
||||
#define AT91_SDRAMC_DBW_16 (1 << 7)
|
||||
#define AT91_SDRAMC_TWR (0xf << 8) /* Write Recovery Delay */
|
||||
#define AT91_SDRAMC_TRC (0xf << 12) /* Row Cycle Delay */
|
||||
#define AT91_SDRAMC_TRP (0xf << 16) /* Row Precharge Delay */
|
||||
#define AT91_SDRAMC_TRCD (0xf << 20) /* Row to Column Delay */
|
||||
#define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */
|
||||
#define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */
|
||||
|
||||
#define AT91_SDRAMC_LPR (AT91_SDRAMC + 0x10) /* SDRAM Controller Low Power Register */
|
||||
#define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */
|
||||
#define AT91_SDRAMC_LPCB_DISABLE 0
|
||||
#define AT91_SDRAMC_LPCB_SELF_REFRESH 1
|
||||
#define AT91_SDRAMC_LPCB_POWER_DOWN 2
|
||||
#define AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3
|
||||
#define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */
|
||||
#define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
|
||||
#define AT91_SDRAMC_DS (3 << 10) /* Drive Strenght */
|
||||
#define AT91_SDRAMC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */
|
||||
#define AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES (0 << 12)
|
||||
#define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12)
|
||||
#define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12)
|
||||
|
||||
#define AT91_SDRAMC_IER (AT91_SDRAMC + 0x14) /* SDRAM Controller Interrupt Enable Register */
|
||||
#define AT91_SDRAMC_IDR (AT91_SDRAMC + 0x18) /* SDRAM Controller Interrupt Disable Register */
|
||||
#define AT91_SDRAMC_IMR (AT91_SDRAMC + 0x1C) /* SDRAM Controller Interrupt Mask Register */
|
||||
#define AT91_SDRAMC_ISR (AT91_SDRAMC + 0x20) /* SDRAM Controller Interrupt Status Register */
|
||||
#define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */
|
||||
|
||||
#define AT91_SDRAMC_MDR (AT91_SDRAMC + 0x24) /* SDRAM Memory Device Register */
|
||||
#define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */
|
||||
#define AT91_SDRAMC_MD_SDRAM 0
|
||||
#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1
|
||||
|
||||
|
||||
/* Static Memory Controller (SMC) registers */
|
||||
#define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
|
||||
#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */
|
||||
#define AT91_SMC_NWESETUP_(x) ((x) << 0)
|
||||
#define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */
|
||||
#define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8)
|
||||
#define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */
|
||||
#define AT91_SMC_NRDSETUP_(x) ((x) << 16)
|
||||
#define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */
|
||||
#define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24)
|
||||
|
||||
#define AT91_SMC_PULSE(n) (AT91_SMC + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
|
||||
#define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */
|
||||
#define AT91_SMC_NWEPULSE_(x) ((x) << 0)
|
||||
#define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */
|
||||
#define AT91_SMC_NCS_WRPULSE_(x)((x) << 8)
|
||||
#define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */
|
||||
#define AT91_SMC_NRDPULSE_(x) ((x) << 16)
|
||||
#define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */
|
||||
#define AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
|
||||
|
||||
#define AT91_SMC_CYCLE(n) (AT91_SMC + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
|
||||
#define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */
|
||||
#define AT91_SMC_NWECYCLE_(x) ((x) << 0)
|
||||
#define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */
|
||||
#define AT91_SMC_NRDCYCLE_(x) ((x) << 16)
|
||||
|
||||
#define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
|
||||
#define AT91_SMC_READMODE (1 << 0) /* Read Mode */
|
||||
#define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */
|
||||
#define AT91_SMC_EXNWMODE (3 << 5) /* NWAIT Mode */
|
||||
#define AT91_SMC_EXNWMODE_DISABLE (0 << 5)
|
||||
#define AT91_SMC_EXNWMODE_FROZEN (2 << 5)
|
||||
#define AT91_SMC_EXNWMODE_READY (3 << 5)
|
||||
#define AT91_SMC_BAT (1 << 8) /* Byte Access Type */
|
||||
#define AT91_SMC_BAT_SELECT (0 << 8)
|
||||
#define AT91_SMC_BAT_WRITE (1 << 8)
|
||||
#define AT91_SMC_DBW (3 << 12) /* Data Bus Width */
|
||||
#define AT91_SMC_DBW_8 (0 << 12)
|
||||
#define AT91_SMC_DBW_16 (1 << 12)
|
||||
#define AT91_SMC_DBW_32 (2 << 12)
|
||||
#define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */
|
||||
#define AT91_SMC_TDF_(x) ((x) << 16)
|
||||
#define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */
|
||||
#define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */
|
||||
#define AT91_SMC_PS (3 << 28) /* Page Size */
|
||||
#define AT91_SMC_PS_4 (0 << 28)
|
||||
#define AT91_SMC_PS_8 (1 << 28)
|
||||
#define AT91_SMC_PS_16 (2 << 28)
|
||||
#define AT91_SMC_PS_32 (3 << 28)
|
||||
|
||||
#endif
|
||||
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