PCI: altera: Add Altera PCIe host controller driver
Add the Altera PCIe host controller driver. [bhelgaas: whitespace, fold in DT and maintainer updates, OF_PCI dependency from Arnd] Signed-off-by: Ley Foon Tan <lftan@altera.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Rob Herring <robh@kernel.org> (DT binding)
This commit is contained in:
Ley Foon Tan
Bjorn Helgaas
Родитель
0ab089c254
Коммит
eaa6111b70
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@ -0,0 +1,49 @@
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* Altera PCIe controller
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Required properties:
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- compatible : should contain "altr,pcie-root-port-1.0"
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- reg: a list of physical base address and length for TXS and CRA.
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- reg-names: must include the following entries:
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"Txs": TX slave port region
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"Cra": Control register access region
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- interrupt-parent: interrupt source phandle.
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- interrupts: specifies the interrupt source of the parent interrupt controller.
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The format of the interrupt specifier depends on the parent interrupt
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controller.
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- device_type: must be "pci"
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- #address-cells: set to <3>
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- #size-cells: set to <2>
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- #interrupt-cells: set to <1>
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- ranges: describes the translation of addresses for root ports and standard
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PCI regions.
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- interrupt-map-mask and interrupt-map: standard PCI properties to define the
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mapping of the PCIe interface to interrupt numbers.
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Optional properties:
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- msi-parent: Link to the hardware entity that serves as the MSI controller for this PCIe
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controller.
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- bus-range: PCI bus numbers covered
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Example
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pcie_0: pcie@0xc00000000 {
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compatible = "altr,pcie-root-port-1.0";
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reg = <0xc0000000 0x20000000>,
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<0xff220000 0x00004000>;
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reg-names = "Txs", "Cra";
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interrupt-parent = <&hps_0_arm_gic_0>;
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interrupts = <0 40 4>;
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interrupt-controller;
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#interrupt-cells = <1>;
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bus-range = <0x0 0xFF>;
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device_type = "pci";
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msi-parent = <&msi_to_gic_gen_0>;
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#address-cells = <3>;
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#size-cells = <2>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_0 1>,
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<0 0 0 2 &pcie_0 2>,
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<0 0 0 3 &pcie_0 3>,
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<0 0 0 4 &pcie_0 4>;
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ranges = <0x82000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x10000000
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0x82000000 0x00000000 0x10000000 0xd0000000 0x00000000 0x10000000>;
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};
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@ -7938,6 +7938,14 @@ F: include/linux/pci*
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F: arch/x86/pci/
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F: arch/x86/kernel/quirks.c
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PCI DRIVER FOR ALTERA PCIE IP
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M: Ley Foon Tan <lftan@altera.com>
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L: rfi@lists.rocketboards.org (moderated for non-subscribers)
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L: linux-pci@vger.kernel.org
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S: Supported
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F: Documentation/devicetree/bindings/pci/altera-pcie.txt
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F: drivers/pci/host/pcie-altera.c
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PCI DRIVER FOR ARM VERSATILE PLATFORM
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M: Rob Herring <robh@kernel.org>
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L: linux-pci@vger.kernel.org
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@ -145,4 +145,13 @@ config PCIE_IPROC_BCMA
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Say Y here if you want to use the Broadcom iProc PCIe controller
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through the BCMA bus interface
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config PCIE_ALTERA
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bool "Altera PCIe controller"
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depends on ARM || NIOS2
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depends on OF_PCI
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select PCI_DOMAINS
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help
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Say Y here if you want to enable PCIe controller support on Altera
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FPGA.
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endmenu
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@ -17,3 +17,4 @@ obj-$(CONFIG_PCI_VERSATILE) += pci-versatile.o
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obj-$(CONFIG_PCIE_IPROC) += pcie-iproc.o
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obj-$(CONFIG_PCIE_IPROC_PLATFORM) += pcie-iproc-platform.o
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obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
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obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
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@ -0,0 +1,579 @@
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/*
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* Copyright Altera Corporation (C) 2013-2015. All rights reserved
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_pci.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#define RP_TX_REG0 0x2000
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#define RP_TX_REG1 0x2004
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#define RP_TX_CNTRL 0x2008
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#define RP_TX_EOP 0x2
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#define RP_TX_SOP 0x1
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#define RP_RXCPL_STATUS 0x2010
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#define RP_RXCPL_EOP 0x2
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#define RP_RXCPL_SOP 0x1
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#define RP_RXCPL_REG0 0x2014
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#define RP_RXCPL_REG1 0x2018
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#define P2A_INT_STATUS 0x3060
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#define P2A_INT_STS_ALL 0xf
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#define P2A_INT_ENABLE 0x3070
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#define P2A_INT_ENA_ALL 0xf
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#define RP_LTSSM 0x3c64
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#define LTSSM_L0 0xf
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/* TLP configuration type 0 and 1 */
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#define TLP_FMTTYPE_CFGRD0 0x04 /* Configuration Read Type 0 */
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#define TLP_FMTTYPE_CFGWR0 0x44 /* Configuration Write Type 0 */
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#define TLP_FMTTYPE_CFGRD1 0x05 /* Configuration Read Type 1 */
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#define TLP_FMTTYPE_CFGWR1 0x45 /* Configuration Write Type 1 */
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#define TLP_PAYLOAD_SIZE 0x01
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#define TLP_READ_TAG 0x1d
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#define TLP_WRITE_TAG 0x10
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#define TLP_CFG_DW0(fmttype) (((fmttype) << 24) | TLP_PAYLOAD_SIZE)
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#define TLP_CFG_DW1(reqid, tag, be) (((reqid) << 16) | (tag << 8) | (be))
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#define TLP_CFG_DW2(bus, devfn, offset) \
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(((bus) << 24) | ((devfn) << 16) | (offset))
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#define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn))
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#define TLP_HDR_SIZE 3
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#define TLP_LOOP 500
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#define INTX_NUM 4
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#define DWORD_MASK 3
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struct altera_pcie {
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struct platform_device *pdev;
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void __iomem *cra_base;
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int irq;
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u8 root_bus_nr;
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struct irq_domain *irq_domain;
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struct resource bus_range;
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struct list_head resources;
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};
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struct tlp_rp_regpair_t {
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u32 ctrl;
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u32 reg0;
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u32 reg1;
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};
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static void altera_pcie_retrain(struct pci_dev *dev)
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{
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u16 linkcap, linkstat;
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/*
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* Set the retrain bit if the PCIe rootport support > 2.5GB/s, but
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* current speed is 2.5 GB/s.
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*/
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pcie_capability_read_word(dev, PCI_EXP_LNKCAP, &linkcap);
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if ((linkcap & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB)
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return;
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pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &linkstat);
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if ((linkstat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB)
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pcie_capability_set_word(dev, PCI_EXP_LNKCTL,
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PCI_EXP_LNKCTL_RL);
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}
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DECLARE_PCI_FIXUP_EARLY(0x1172, PCI_ANY_ID, altera_pcie_retrain);
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/*
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* Altera PCIe port uses BAR0 of RC's configuration space as the translation
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* from PCI bus to native BUS. Entire DDR region is mapped into PCIe space
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* using these registers, so it can be reached by DMA from EP devices.
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* This BAR0 will also access to MSI vector when receiving MSI/MSIX interrupt
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* from EP devices, eventually trigger interrupt to GIC. The BAR0 of bridge
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* should be hidden during enumeration to avoid the sizing and resource
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* allocation by PCIe core.
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*/
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static bool altera_pcie_hide_rc_bar(struct pci_bus *bus, unsigned int devfn,
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int offset)
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{
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if (pci_is_root_bus(bus) && (devfn == 0) &&
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(offset == PCI_BASE_ADDRESS_0))
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return true;
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return false;
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}
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static inline void cra_writel(struct altera_pcie *pcie, const u32 value,
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const u32 reg)
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{
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writel_relaxed(value, pcie->cra_base + reg);
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}
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static inline u32 cra_readl(struct altera_pcie *pcie, const u32 reg)
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{
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return readl_relaxed(pcie->cra_base + reg);
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}
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static void tlp_write_tx(struct altera_pcie *pcie,
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struct tlp_rp_regpair_t *tlp_rp_regdata)
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{
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cra_writel(pcie, tlp_rp_regdata->reg0, RP_TX_REG0);
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cra_writel(pcie, tlp_rp_regdata->reg1, RP_TX_REG1);
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cra_writel(pcie, tlp_rp_regdata->ctrl, RP_TX_CNTRL);
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}
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static bool altera_pcie_link_is_up(struct altera_pcie *pcie)
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{
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return !!(cra_readl(pcie, RP_LTSSM) & LTSSM_L0);
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}
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static bool altera_pcie_valid_config(struct altera_pcie *pcie,
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struct pci_bus *bus, int dev)
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{
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/* If there is no link, then there is no device */
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if (bus->number != pcie->root_bus_nr) {
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if (!altera_pcie_link_is_up(pcie))
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return false;
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}
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/* access only one slot on each root port */
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if (bus->number == pcie->root_bus_nr && dev > 0)
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return false;
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/*
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* Do not read more than one device on the bus directly attached
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* to root port, root port can only attach to one downstream port.
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*/
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if (bus->primary == pcie->root_bus_nr && dev > 0)
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return false;
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return true;
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}
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static int tlp_read_packet(struct altera_pcie *pcie, u32 *value)
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{
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u8 loop;
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bool sop = 0;
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u32 ctrl;
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u32 reg0, reg1;
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/*
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* Minimum 2 loops to read TLP headers and 1 loop to read data
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* payload.
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*/
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for (loop = 0; loop < TLP_LOOP; loop++) {
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ctrl = cra_readl(pcie, RP_RXCPL_STATUS);
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if ((ctrl & RP_RXCPL_SOP) || (ctrl & RP_RXCPL_EOP) || sop) {
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reg0 = cra_readl(pcie, RP_RXCPL_REG0);
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reg1 = cra_readl(pcie, RP_RXCPL_REG1);
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if (ctrl & RP_RXCPL_SOP)
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sop = true;
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if (ctrl & RP_RXCPL_EOP) {
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if (value)
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*value = reg0;
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return PCIBIOS_SUCCESSFUL;
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}
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}
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udelay(5);
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}
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return -ENOENT;
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}
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static void tlp_write_packet(struct altera_pcie *pcie, u32 *headers,
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u32 data, bool align)
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{
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struct tlp_rp_regpair_t tlp_rp_regdata;
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tlp_rp_regdata.reg0 = headers[0];
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tlp_rp_regdata.reg1 = headers[1];
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tlp_rp_regdata.ctrl = RP_TX_SOP;
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tlp_write_tx(pcie, &tlp_rp_regdata);
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if (align) {
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tlp_rp_regdata.reg0 = headers[2];
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tlp_rp_regdata.reg1 = 0;
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tlp_rp_regdata.ctrl = 0;
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tlp_write_tx(pcie, &tlp_rp_regdata);
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tlp_rp_regdata.reg0 = data;
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tlp_rp_regdata.reg1 = 0;
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} else {
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tlp_rp_regdata.reg0 = headers[2];
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tlp_rp_regdata.reg1 = data;
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}
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tlp_rp_regdata.ctrl = RP_TX_EOP;
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tlp_write_tx(pcie, &tlp_rp_regdata);
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}
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static int tlp_cfg_dword_read(struct altera_pcie *pcie, u8 bus, u32 devfn,
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int where, u8 byte_en, u32 *value)
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{
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u32 headers[TLP_HDR_SIZE];
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if (bus == pcie->root_bus_nr)
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headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGRD0);
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else
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headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGRD1);
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headers[1] = TLP_CFG_DW1(TLP_REQ_ID(pcie->root_bus_nr, devfn),
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TLP_READ_TAG, byte_en);
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headers[2] = TLP_CFG_DW2(bus, devfn, where);
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tlp_write_packet(pcie, headers, 0, false);
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return tlp_read_packet(pcie, value);
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}
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static int tlp_cfg_dword_write(struct altera_pcie *pcie, u8 bus, u32 devfn,
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int where, u8 byte_en, u32 value)
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{
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u32 headers[TLP_HDR_SIZE];
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int ret;
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if (bus == pcie->root_bus_nr)
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headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGWR0);
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else
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headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGWR1);
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headers[1] = TLP_CFG_DW1(TLP_REQ_ID(pcie->root_bus_nr, devfn),
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TLP_WRITE_TAG, byte_en);
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headers[2] = TLP_CFG_DW2(bus, devfn, where);
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/* check alignment to Qword */
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if ((where & 0x7) == 0)
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tlp_write_packet(pcie, headers, value, true);
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else
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tlp_write_packet(pcie, headers, value, false);
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ret = tlp_read_packet(pcie, NULL);
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if (ret != PCIBIOS_SUCCESSFUL)
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return ret;
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/*
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* Monitor changes to PCI_PRIMARY_BUS register on root port
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* and update local copy of root bus number accordingly.
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*/
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if ((bus == pcie->root_bus_nr) && (where == PCI_PRIMARY_BUS))
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pcie->root_bus_nr = (u8)(value);
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return PCIBIOS_SUCCESSFUL;
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}
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static int altera_pcie_cfg_read(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *value)
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{
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struct altera_pcie *pcie = bus->sysdata;
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int ret;
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u32 data;
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u8 byte_en;
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if (altera_pcie_hide_rc_bar(bus, devfn, where))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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if (!altera_pcie_valid_config(pcie, bus, PCI_SLOT(devfn))) {
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*value = 0xffffffff;
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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switch (size) {
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case 1:
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byte_en = 1 << (where & 3);
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break;
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case 2:
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byte_en = 3 << (where & 3);
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break;
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default:
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byte_en = 0xf;
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break;
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}
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ret = tlp_cfg_dword_read(pcie, bus->number, devfn,
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(where & ~DWORD_MASK), byte_en, &data);
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if (ret != PCIBIOS_SUCCESSFUL)
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return ret;
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switch (size) {
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case 1:
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*value = (data >> (8 * (where & 0x3))) & 0xff;
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break;
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case 2:
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*value = (data >> (8 * (where & 0x2))) & 0xffff;
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break;
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default:
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*value = data;
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static int altera_pcie_cfg_write(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 value)
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{
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struct altera_pcie *pcie = bus->sysdata;
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u32 data32;
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u32 shift = 8 * (where & 3);
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u8 byte_en;
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if (altera_pcie_hide_rc_bar(bus, devfn, where))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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if (!altera_pcie_valid_config(pcie, bus, PCI_SLOT(devfn)))
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return PCIBIOS_DEVICE_NOT_FOUND;
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switch (size) {
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case 1:
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data32 = (value & 0xff) << shift;
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byte_en = 1 << (where & 3);
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break;
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case 2:
|
||||
data32 = (value & 0xffff) << shift;
|
||||
byte_en = 3 << (where & 3);
|
||||
break;
|
||||
default:
|
||||
data32 = value;
|
||||
byte_en = 0xf;
|
||||
break;
|
||||
}
|
||||
|
||||
return tlp_cfg_dword_write(pcie, bus->number, devfn,
|
||||
(where & ~DWORD_MASK), byte_en, data32);
|
||||
}
|
||||
|
||||
static struct pci_ops altera_pcie_ops = {
|
||||
.read = altera_pcie_cfg_read,
|
||||
.write = altera_pcie_cfg_write,
|
||||
};
|
||||
|
||||
static int altera_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
|
||||
irq_hw_number_t hwirq)
|
||||
{
|
||||
irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
|
||||
irq_set_chip_data(irq, domain->host_data);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct irq_domain_ops intx_domain_ops = {
|
||||
.map = altera_pcie_intx_map,
|
||||
};
|
||||
|
||||
static void altera_pcie_isr(struct irq_desc *desc)
|
||||
{
|
||||
struct irq_chip *chip = irq_desc_get_chip(desc);
|
||||
struct altera_pcie *pcie;
|
||||
unsigned long status;
|
||||
u32 bit;
|
||||
u32 virq;
|
||||
|
||||
chained_irq_enter(chip, desc);
|
||||
pcie = irq_desc_get_handler_data(desc);
|
||||
|
||||
while ((status = cra_readl(pcie, P2A_INT_STATUS)
|
||||
& P2A_INT_STS_ALL) != 0) {
|
||||
for_each_set_bit(bit, &status, INTX_NUM) {
|
||||
/* clear interrupts */
|
||||
cra_writel(pcie, 1 << bit, P2A_INT_STATUS);
|
||||
|
||||
virq = irq_find_mapping(pcie->irq_domain, bit + 1);
|
||||
if (virq)
|
||||
generic_handle_irq(virq);
|
||||
else
|
||||
dev_err(&pcie->pdev->dev,
|
||||
"unexpected IRQ, INT%d\n", bit);
|
||||
}
|
||||
}
|
||||
|
||||
chained_irq_exit(chip, desc);
|
||||
}
|
||||
|
||||
static void altera_pcie_release_of_pci_ranges(struct altera_pcie *pcie)
|
||||
{
|
||||
pci_free_resource_list(&pcie->resources);
|
||||
}
|
||||
|
||||
static int altera_pcie_parse_request_of_pci_ranges(struct altera_pcie *pcie)
|
||||
{
|
||||
int err, res_valid = 0;
|
||||
struct device *dev = &pcie->pdev->dev;
|
||||
struct device_node *np = dev->of_node;
|
||||
struct resource_entry *win;
|
||||
|
||||
err = of_pci_get_host_bridge_resources(np, 0, 0xff, &pcie->resources,
|
||||
NULL);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
resource_list_for_each_entry(win, &pcie->resources) {
|
||||
struct resource *parent, *res = win->res;
|
||||
|
||||
switch (resource_type(res)) {
|
||||
case IORESOURCE_MEM:
|
||||
parent = &iomem_resource;
|
||||
res_valid |= !(res->flags & IORESOURCE_PREFETCH);
|
||||
break;
|
||||
default:
|
||||
continue;
|
||||
}
|
||||
|
||||
err = devm_request_resource(dev, parent, res);
|
||||
if (err)
|
||||
goto out_release_res;
|
||||
}
|
||||
|
||||
if (!res_valid) {
|
||||
dev_err(dev, "non-prefetchable memory resource required\n");
|
||||
err = -EINVAL;
|
||||
goto out_release_res;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
out_release_res:
|
||||
altera_pcie_release_of_pci_ranges(pcie);
|
||||
return err;
|
||||
}
|
||||
|
||||
static int altera_pcie_init_irq_domain(struct altera_pcie *pcie)
|
||||
{
|
||||
struct device *dev = &pcie->pdev->dev;
|
||||
struct device_node *node = dev->of_node;
|
||||
|
||||
/* Setup INTx */
|
||||
pcie->irq_domain = irq_domain_add_linear(node, INTX_NUM,
|
||||
&intx_domain_ops, pcie);
|
||||
if (!pcie->irq_domain) {
|
||||
dev_err(dev, "Failed to get a INTx IRQ domain\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int altera_pcie_parse_dt(struct altera_pcie *pcie)
|
||||
{
|
||||
struct resource *cra;
|
||||
struct platform_device *pdev = pcie->pdev;
|
||||
|
||||
cra = platform_get_resource_byname(pdev, IORESOURCE_MEM, "Cra");
|
||||
if (!cra) {
|
||||
dev_err(&pdev->dev, "no Cra memory resource defined\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
pcie->cra_base = devm_ioremap_resource(&pdev->dev, cra);
|
||||
if (IS_ERR(pcie->cra_base)) {
|
||||
dev_err(&pdev->dev, "failed to map cra memory\n");
|
||||
return PTR_ERR(pcie->cra_base);
|
||||
}
|
||||
|
||||
/* setup IRQ */
|
||||
pcie->irq = platform_get_irq(pdev, 0);
|
||||
if (pcie->irq <= 0) {
|
||||
dev_err(&pdev->dev, "failed to get IRQ: %d\n", pcie->irq);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
irq_set_chained_handler_and_data(pcie->irq, altera_pcie_isr, pcie);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int altera_pcie_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct altera_pcie *pcie;
|
||||
struct pci_bus *bus;
|
||||
struct pci_bus *child;
|
||||
int ret;
|
||||
|
||||
pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
|
||||
if (!pcie)
|
||||
return -ENOMEM;
|
||||
|
||||
pcie->pdev = pdev;
|
||||
|
||||
ret = altera_pcie_parse_dt(pcie);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Parsing DT failed\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
INIT_LIST_HEAD(&pcie->resources);
|
||||
|
||||
ret = altera_pcie_parse_request_of_pci_ranges(pcie);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Failed add resources\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = altera_pcie_init_irq_domain(pcie);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Failed creating IRQ Domain\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* clear all interrupts */
|
||||
cra_writel(pcie, P2A_INT_STS_ALL, P2A_INT_STATUS);
|
||||
/* enable all interrupts */
|
||||
cra_writel(pcie, P2A_INT_ENA_ALL, P2A_INT_ENABLE);
|
||||
|
||||
bus = pci_scan_root_bus(&pdev->dev, pcie->root_bus_nr, &altera_pcie_ops,
|
||||
pcie, &pcie->resources);
|
||||
if (!bus)
|
||||
return -ENOMEM;
|
||||
|
||||
pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
|
||||
pci_assign_unassigned_bus_resources(bus);
|
||||
|
||||
/* Configure PCI Express setting. */
|
||||
list_for_each_entry(child, &bus->children, node)
|
||||
pcie_bus_configure_settings(child);
|
||||
|
||||
pci_bus_add_devices(bus);
|
||||
|
||||
platform_set_drvdata(pdev, pcie);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct of_device_id altera_pcie_of_match[] = {
|
||||
{ .compatible = "altr,pcie-root-port-1.0", },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, altera_pcie_of_match);
|
||||
|
||||
static struct platform_driver altera_pcie_driver = {
|
||||
.probe = altera_pcie_probe,
|
||||
.driver = {
|
||||
.name = "altera-pcie",
|
||||
.of_match_table = altera_pcie_of_match,
|
||||
.suppress_bind_attrs = true,
|
||||
},
|
||||
};
|
||||
|
||||
static int altera_pcie_init(void)
|
||||
{
|
||||
return platform_driver_register(&altera_pcie_driver);
|
||||
}
|
||||
module_init(altera_pcie_init);
|
||||
|
||||
MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>");
|
||||
MODULE_DESCRIPTION("Altera PCIe host controller driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
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