Merge tag 'v4.5-rockchip-clk1_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next
Rockchip clock changes for 4.5 containing - a new pll-type used on rk3036 and other Cortex-A7 socs - new clock-trees for rk3036 and rk3228 - switch rk3288 plls to slow mode on reboot - a bunch of new clock ids - some more critical clocks - wrong register offsets for the rk3368 cpuclks - allowing more than 2 parents for the cpuclk
This commit is contained in:
Michael Turquette
Коммит
eaaa6fb53f
|
|
@ -0,0 +1,56 @@
|
|||
* Rockchip RK3036 Clock and Reset Unit
|
||||
|
||||
The RK3036 clock controller generates and supplies clock to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be "rockchip,rk3036-cru"
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- #clock-cells: should be 1.
|
||||
- #reset-cells: should be 1.
|
||||
|
||||
Optional Properties:
|
||||
|
||||
- rockchip,grf: phandle to the syscon managing the "general register files"
|
||||
If missing pll rates are not changeable, due to the missing pll lock status.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk3036-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
|
||||
External clocks:
|
||||
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required,
|
||||
- "ext_i2s" - external I2S clock - optional,
|
||||
- "ext_gmac" - external GMAC clock - optional
|
||||
|
||||
Example: Clock controller node:
|
||||
|
||||
cru: cru@20000000 {
|
||||
compatible = "rockchip,rk3036-cru";
|
||||
reg = <0x20000000 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
Example: UART controller node that consumes the clock generated by the clock
|
||||
controller:
|
||||
|
||||
uart0: serial@20060000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x20060000 0x100>;
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&cru SCLK_UART0>;
|
||||
};
|
||||
|
|
@ -0,0 +1,58 @@
|
|||
* Rockchip RK3228 Clock and Reset Unit
|
||||
|
||||
The RK3228 clock controller generates and supplies clock to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be "rockchip,rk3228-cru"
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- #clock-cells: should be 1.
|
||||
- #reset-cells: should be 1.
|
||||
|
||||
Optional Properties:
|
||||
|
||||
- rockchip,grf: phandle to the syscon managing the "general register files"
|
||||
If missing pll rates are not changeable, due to the missing pll lock status.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk3228-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
|
||||
External clocks:
|
||||
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required,
|
||||
- "ext_i2s" - external I2S clock - optional,
|
||||
- "ext_gmac" - external GMAC clock - optional
|
||||
- "ext_hsadc" - external HSADC clock - optional
|
||||
- "phy_50m_out" - output clock of the pll in the mac phy
|
||||
|
||||
Example: Clock controller node:
|
||||
|
||||
cru: cru@20000000 {
|
||||
compatible = "rockchip,rk3228-cru";
|
||||
reg = <0x20000000 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
Example: UART controller node that consumes the clock generated by the clock
|
||||
controller:
|
||||
|
||||
uart0: serial@10110000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x10110000 0x100>;
|
||||
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&cru SCLK_UART0>;
|
||||
};
|
||||
|
|
@ -10,6 +10,8 @@ obj-y += clk-inverter.o
|
|||
obj-y += clk-mmc-phase.o
|
||||
obj-$(CONFIG_RESET_CONTROLLER) += softrst.o
|
||||
|
||||
obj-y += clk-rk3036.o
|
||||
obj-y += clk-rk3188.o
|
||||
obj-y += clk-rk3228.o
|
||||
obj-y += clk-rk3288.o
|
||||
obj-y += clk-rk3368.o
|
||||
|
|
|
|||
|
|
@ -242,8 +242,8 @@ struct clk *rockchip_clk_register_cpuclk(const char *name,
|
|||
struct clk *clk, *cclk;
|
||||
int ret;
|
||||
|
||||
if (num_parents != 2) {
|
||||
pr_err("%s: needs two parent clocks\n", __func__);
|
||||
if (num_parents < 2) {
|
||||
pr_err("%s: needs at least two parent clocks\n", __func__);
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -2,6 +2,9 @@
|
|||
* Copyright (c) 2014 MundoReader S.L.
|
||||
* Author: Heiko Stuebner <heiko@sntech.de>
|
||||
*
|
||||
* Copyright (c) 2015 Rockchip Electronics Co. Ltd.
|
||||
* Author: Xing Zheng <zhengxing@rock-chips.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
|
|
@ -19,6 +22,7 @@
|
|||
#include <linux/delay.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/clk.h>
|
||||
#include "clk.h"
|
||||
|
||||
#define PLL_MODE_MASK 0x3
|
||||
|
|
@ -107,6 +111,252 @@ static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll)
|
|||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
/**
|
||||
* PLL used in RK3036
|
||||
*/
|
||||
|
||||
#define RK3036_PLLCON(i) (i * 0x4)
|
||||
#define RK3036_PLLCON0_FBDIV_MASK 0xfff
|
||||
#define RK3036_PLLCON0_FBDIV_SHIFT 0
|
||||
#define RK3036_PLLCON0_POSTDIV1_MASK 0x7
|
||||
#define RK3036_PLLCON0_POSTDIV1_SHIFT 12
|
||||
#define RK3036_PLLCON1_REFDIV_MASK 0x3f
|
||||
#define RK3036_PLLCON1_REFDIV_SHIFT 0
|
||||
#define RK3036_PLLCON1_POSTDIV2_MASK 0x7
|
||||
#define RK3036_PLLCON1_POSTDIV2_SHIFT 6
|
||||
#define RK3036_PLLCON1_DSMPD_MASK 0x1
|
||||
#define RK3036_PLLCON1_DSMPD_SHIFT 12
|
||||
#define RK3036_PLLCON2_FRAC_MASK 0xffffff
|
||||
#define RK3036_PLLCON2_FRAC_SHIFT 0
|
||||
|
||||
#define RK3036_PLLCON1_PWRDOWN (1 << 13)
|
||||
|
||||
static void rockchip_rk3036_pll_get_params(struct rockchip_clk_pll *pll,
|
||||
struct rockchip_pll_rate_table *rate)
|
||||
{
|
||||
u32 pllcon;
|
||||
|
||||
pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(0));
|
||||
rate->fbdiv = ((pllcon >> RK3036_PLLCON0_FBDIV_SHIFT)
|
||||
& RK3036_PLLCON0_FBDIV_MASK);
|
||||
rate->postdiv1 = ((pllcon >> RK3036_PLLCON0_POSTDIV1_SHIFT)
|
||||
& RK3036_PLLCON0_POSTDIV1_MASK);
|
||||
|
||||
pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(1));
|
||||
rate->refdiv = ((pllcon >> RK3036_PLLCON1_REFDIV_SHIFT)
|
||||
& RK3036_PLLCON1_REFDIV_MASK);
|
||||
rate->postdiv2 = ((pllcon >> RK3036_PLLCON1_POSTDIV2_SHIFT)
|
||||
& RK3036_PLLCON1_POSTDIV2_MASK);
|
||||
rate->dsmpd = ((pllcon >> RK3036_PLLCON1_DSMPD_SHIFT)
|
||||
& RK3036_PLLCON1_DSMPD_MASK);
|
||||
|
||||
pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2));
|
||||
rate->frac = ((pllcon >> RK3036_PLLCON2_FRAC_SHIFT)
|
||||
& RK3036_PLLCON2_FRAC_MASK);
|
||||
}
|
||||
|
||||
static unsigned long rockchip_rk3036_pll_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long prate)
|
||||
{
|
||||
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
|
||||
struct rockchip_pll_rate_table cur;
|
||||
u64 rate64 = prate;
|
||||
|
||||
rockchip_rk3036_pll_get_params(pll, &cur);
|
||||
|
||||
rate64 *= cur.fbdiv;
|
||||
do_div(rate64, cur.refdiv);
|
||||
|
||||
if (cur.dsmpd == 0) {
|
||||
/* fractional mode */
|
||||
u64 frac_rate64 = prate * cur.frac;
|
||||
|
||||
do_div(frac_rate64, cur.refdiv);
|
||||
rate64 += frac_rate64 >> 24;
|
||||
}
|
||||
|
||||
do_div(rate64, cur.postdiv1);
|
||||
do_div(rate64, cur.postdiv2);
|
||||
|
||||
return (unsigned long)rate64;
|
||||
}
|
||||
|
||||
static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll,
|
||||
const struct rockchip_pll_rate_table *rate)
|
||||
{
|
||||
const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
|
||||
struct clk_mux *pll_mux = &pll->pll_mux;
|
||||
struct rockchip_pll_rate_table cur;
|
||||
u32 pllcon;
|
||||
int rate_change_remuxed = 0;
|
||||
int cur_parent;
|
||||
int ret;
|
||||
|
||||
pr_debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
|
||||
__func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv,
|
||||
rate->postdiv2, rate->dsmpd, rate->frac);
|
||||
|
||||
rockchip_rk3036_pll_get_params(pll, &cur);
|
||||
cur.rate = 0;
|
||||
|
||||
cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
|
||||
if (cur_parent == PLL_MODE_NORM) {
|
||||
pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
|
||||
rate_change_remuxed = 1;
|
||||
}
|
||||
|
||||
/* update pll values */
|
||||
writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3036_PLLCON0_FBDIV_MASK,
|
||||
RK3036_PLLCON0_FBDIV_SHIFT) |
|
||||
HIWORD_UPDATE(rate->postdiv1, RK3036_PLLCON0_POSTDIV1_MASK,
|
||||
RK3036_PLLCON0_POSTDIV1_SHIFT),
|
||||
pll->reg_base + RK3036_PLLCON(0));
|
||||
|
||||
writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3036_PLLCON1_REFDIV_MASK,
|
||||
RK3036_PLLCON1_REFDIV_SHIFT) |
|
||||
HIWORD_UPDATE(rate->postdiv2, RK3036_PLLCON1_POSTDIV2_MASK,
|
||||
RK3036_PLLCON1_POSTDIV2_SHIFT) |
|
||||
HIWORD_UPDATE(rate->dsmpd, RK3036_PLLCON1_DSMPD_MASK,
|
||||
RK3036_PLLCON1_DSMPD_SHIFT),
|
||||
pll->reg_base + RK3036_PLLCON(1));
|
||||
|
||||
/* GPLL CON2 is not HIWORD_MASK */
|
||||
pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2));
|
||||
pllcon &= ~(RK3036_PLLCON2_FRAC_MASK << RK3036_PLLCON2_FRAC_SHIFT);
|
||||
pllcon |= rate->frac << RK3036_PLLCON2_FRAC_SHIFT;
|
||||
writel_relaxed(pllcon, pll->reg_base + RK3036_PLLCON(2));
|
||||
|
||||
/* wait for the pll to lock */
|
||||
ret = rockchip_pll_wait_lock(pll);
|
||||
if (ret) {
|
||||
pr_warn("%s: pll update unsucessful, trying to restore old params\n",
|
||||
__func__);
|
||||
rockchip_rk3036_pll_set_params(pll, &cur);
|
||||
}
|
||||
|
||||
if (rate_change_remuxed)
|
||||
pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int rockchip_rk3036_pll_set_rate(struct clk_hw *hw, unsigned long drate,
|
||||
unsigned long prate)
|
||||
{
|
||||
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
|
||||
const struct rockchip_pll_rate_table *rate;
|
||||
unsigned long old_rate = rockchip_rk3036_pll_recalc_rate(hw, prate);
|
||||
struct regmap *grf = rockchip_clk_get_grf();
|
||||
|
||||
if (IS_ERR(grf)) {
|
||||
pr_debug("%s: grf regmap not available, aborting rate change\n",
|
||||
__func__);
|
||||
return PTR_ERR(grf);
|
||||
}
|
||||
|
||||
pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu\n",
|
||||
__func__, __clk_get_name(hw->clk), old_rate, drate, prate);
|
||||
|
||||
/* Get required rate settings from table */
|
||||
rate = rockchip_get_pll_settings(pll, drate);
|
||||
if (!rate) {
|
||||
pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
|
||||
drate, __clk_get_name(hw->clk));
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return rockchip_rk3036_pll_set_params(pll, rate);
|
||||
}
|
||||
|
||||
static int rockchip_rk3036_pll_enable(struct clk_hw *hw)
|
||||
{
|
||||
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
|
||||
|
||||
writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 0),
|
||||
pll->reg_base + RK3036_PLLCON(1));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void rockchip_rk3036_pll_disable(struct clk_hw *hw)
|
||||
{
|
||||
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
|
||||
|
||||
writel(HIWORD_UPDATE(RK3036_PLLCON1_PWRDOWN,
|
||||
RK3036_PLLCON1_PWRDOWN, 0),
|
||||
pll->reg_base + RK3036_PLLCON(1));
|
||||
}
|
||||
|
||||
static int rockchip_rk3036_pll_is_enabled(struct clk_hw *hw)
|
||||
{
|
||||
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
|
||||
u32 pllcon = readl(pll->reg_base + RK3036_PLLCON(1));
|
||||
|
||||
return !(pllcon & RK3036_PLLCON1_PWRDOWN);
|
||||
}
|
||||
|
||||
static void rockchip_rk3036_pll_init(struct clk_hw *hw)
|
||||
{
|
||||
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
|
||||
const struct rockchip_pll_rate_table *rate;
|
||||
struct rockchip_pll_rate_table cur;
|
||||
unsigned long drate;
|
||||
|
||||
if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))
|
||||
return;
|
||||
|
||||
drate = clk_hw_get_rate(hw);
|
||||
rate = rockchip_get_pll_settings(pll, drate);
|
||||
|
||||
/* when no rate setting for the current rate, rely on clk_set_rate */
|
||||
if (!rate)
|
||||
return;
|
||||
|
||||
rockchip_rk3036_pll_get_params(pll, &cur);
|
||||
|
||||
pr_debug("%s: pll %s@%lu: Hz\n", __func__, __clk_get_name(hw->clk),
|
||||
drate);
|
||||
pr_debug("old - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
|
||||
cur.fbdiv, cur.postdiv1, cur.refdiv, cur.postdiv2,
|
||||
cur.dsmpd, cur.frac);
|
||||
pr_debug("new - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
|
||||
rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2,
|
||||
rate->dsmpd, rate->frac);
|
||||
|
||||
if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 ||
|
||||
rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 ||
|
||||
rate->dsmpd != cur.dsmpd || rate->frac != cur.frac) {
|
||||
struct clk *parent = clk_get_parent(hw->clk);
|
||||
|
||||
if (!parent) {
|
||||
pr_warn("%s: parent of %s not available\n",
|
||||
__func__, __clk_get_name(hw->clk));
|
||||
return;
|
||||
}
|
||||
|
||||
pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n",
|
||||
__func__, __clk_get_name(hw->clk));
|
||||
rockchip_rk3036_pll_set_params(pll, rate);
|
||||
}
|
||||
}
|
||||
|
||||
static const struct clk_ops rockchip_rk3036_pll_clk_norate_ops = {
|
||||
.recalc_rate = rockchip_rk3036_pll_recalc_rate,
|
||||
.enable = rockchip_rk3036_pll_enable,
|
||||
.disable = rockchip_rk3036_pll_disable,
|
||||
.is_enabled = rockchip_rk3036_pll_is_enabled,
|
||||
};
|
||||
|
||||
static const struct clk_ops rockchip_rk3036_pll_clk_ops = {
|
||||
.recalc_rate = rockchip_rk3036_pll_recalc_rate,
|
||||
.round_rate = rockchip_pll_round_rate,
|
||||
.set_rate = rockchip_rk3036_pll_set_rate,
|
||||
.enable = rockchip_rk3036_pll_enable,
|
||||
.disable = rockchip_rk3036_pll_disable,
|
||||
.is_enabled = rockchip_rk3036_pll_is_enabled,
|
||||
.init = rockchip_rk3036_pll_init,
|
||||
};
|
||||
|
||||
/**
|
||||
* PLL used in RK3066, RK3188 and RK3288
|
||||
*/
|
||||
|
|
@ -376,7 +626,7 @@ struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type,
|
|||
pll_mux->lock = lock;
|
||||
pll_mux->hw.init = &init;
|
||||
|
||||
if (pll_type == pll_rk3066)
|
||||
if (pll_type == pll_rk3036 || pll_type == pll_rk3066)
|
||||
pll_mux->flags |= CLK_MUX_HIWORD_MASK;
|
||||
|
||||
/* the actual muxing is xin24m, pll-output, xin32k */
|
||||
|
|
@ -421,6 +671,12 @@ struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type,
|
|||
}
|
||||
|
||||
switch (pll_type) {
|
||||
case pll_rk3036:
|
||||
if (!pll->rate_table)
|
||||
init.ops = &rockchip_rk3036_pll_clk_norate_ops;
|
||||
else
|
||||
init.ops = &rockchip_rk3036_pll_clk_ops;
|
||||
break;
|
||||
case pll_rk3066:
|
||||
if (!pll->rate_table)
|
||||
init.ops = &rockchip_rk3066_pll_clk_norate_ops;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,478 @@
|
|||
/*
|
||||
* Copyright (c) 2014 MundoReader S.L.
|
||||
* Author: Heiko Stuebner <heiko@sntech.de>
|
||||
*
|
||||
* Copyright (c) 2015 Rockchip Electronics Co. Ltd.
|
||||
* Author: Xing Zheng <zhengxing@rock-chips.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/syscore_ops.h>
|
||||
#include <dt-bindings/clock/rk3036-cru.h>
|
||||
#include "clk.h"
|
||||
|
||||
#define RK3036_GRF_SOC_STATUS0 0x14c
|
||||
|
||||
enum rk3036_plls {
|
||||
apll, dpll, gpll,
|
||||
};
|
||||
|
||||
static struct rockchip_pll_rate_table rk3036_pll_rates[] = {
|
||||
/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
|
||||
RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
|
||||
RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0),
|
||||
RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0),
|
||||
RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0),
|
||||
RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0),
|
||||
RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0),
|
||||
RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0),
|
||||
RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0),
|
||||
RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0),
|
||||
RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0),
|
||||
RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0),
|
||||
RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0),
|
||||
RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0),
|
||||
RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0),
|
||||
RK3036_PLL_RATE( 594000000, 2, 99, 2, 1, 1, 0),
|
||||
RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0),
|
||||
RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0),
|
||||
RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0),
|
||||
RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0),
|
||||
RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0),
|
||||
RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0),
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
#define RK3036_DIV_CPU_MASK 0x1f
|
||||
#define RK3036_DIV_CPU_SHIFT 8
|
||||
|
||||
#define RK3036_DIV_PERI_MASK 0xf
|
||||
#define RK3036_DIV_PERI_SHIFT 0
|
||||
#define RK3036_DIV_ACLK_MASK 0x7
|
||||
#define RK3036_DIV_ACLK_SHIFT 4
|
||||
#define RK3036_DIV_HCLK_MASK 0x3
|
||||
#define RK3036_DIV_HCLK_SHIFT 8
|
||||
#define RK3036_DIV_PCLK_MASK 0x7
|
||||
#define RK3036_DIV_PCLK_SHIFT 12
|
||||
|
||||
#define RK3036_CLKSEL1(_core_periph_div) \
|
||||
{ \
|
||||
.reg = RK2928_CLKSEL_CON(1), \
|
||||
.val = HIWORD_UPDATE(_core_periph_div, RK3036_DIV_PERI_MASK, \
|
||||
RK3036_DIV_PERI_SHIFT) \
|
||||
}
|
||||
|
||||
#define RK3036_CPUCLK_RATE(_prate, _core_periph_div) \
|
||||
{ \
|
||||
.prate = _prate, \
|
||||
.divs = { \
|
||||
RK3036_CLKSEL1(_core_periph_div), \
|
||||
}, \
|
||||
}
|
||||
|
||||
static struct rockchip_cpuclk_rate_table rk3036_cpuclk_rates[] __initdata = {
|
||||
RK3036_CPUCLK_RATE(816000000, 4),
|
||||
RK3036_CPUCLK_RATE(600000000, 4),
|
||||
RK3036_CPUCLK_RATE(312000000, 4),
|
||||
};
|
||||
|
||||
static const struct rockchip_cpuclk_reg_data rk3036_cpuclk_data = {
|
||||
.core_reg = RK2928_CLKSEL_CON(0),
|
||||
.div_core_shift = 0,
|
||||
.div_core_mask = 0x1f,
|
||||
.mux_core_shift = 7,
|
||||
};
|
||||
|
||||
PNAME(mux_pll_p) = { "xin24m", "xin24m" };
|
||||
|
||||
PNAME(mux_armclk_p) = { "apll", "gpll_armclk" };
|
||||
PNAME(mux_busclk_p) = { "apll", "dpll_cpu", "gpll_cpu" };
|
||||
PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" };
|
||||
PNAME(mux_pll_src_3plls_p) = { "apll", "dpll", "gpll" };
|
||||
PNAME(mux_timer_p) = { "xin24m", "pclk_peri_src" };
|
||||
|
||||
PNAME(mux_pll_src_apll_dpll_gpll_usb480m_p) = { "apll", "dpll", "gpll" "usb480m" };
|
||||
|
||||
PNAME(mux_mmc_src_p) = { "apll", "dpll", "gpll", "xin24m" };
|
||||
PNAME(mux_i2s_pre_p) = { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" };
|
||||
PNAME(mux_i2s_clkout_p) = { "i2s_pre", "xin12m" };
|
||||
PNAME(mux_spdif_p) = { "spdif_src", "spdif_frac", "xin12m" };
|
||||
PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" };
|
||||
PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" };
|
||||
PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" };
|
||||
PNAME(mux_mac_p) = { "mac_pll_src", "ext_gmac" };
|
||||
PNAME(mux_dclk_p) = { "dclk_lcdc", "dclk_cru" };
|
||||
|
||||
static struct rockchip_pll_clock rk3036_pll_clks[] __initdata = {
|
||||
[apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
|
||||
RK2928_MODE_CON, 0, 5, 0, rk3036_pll_rates),
|
||||
[dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
|
||||
RK2928_MODE_CON, 4, 4, 0, NULL),
|
||||
[gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
|
||||
RK2928_MODE_CON, 12, 6, ROCKCHIP_PLL_SYNC_RATE, rk3036_pll_rates),
|
||||
};
|
||||
|
||||
#define MFLAGS CLK_MUX_HIWORD_MASK
|
||||
#define DFLAGS CLK_DIVIDER_HIWORD_MASK
|
||||
#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
|
||||
|
||||
static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
|
||||
/*
|
||||
* Clock-Architecture Diagram 1
|
||||
*/
|
||||
|
||||
GATE(0, "gpll_armclk", "gpll", CLK_IGNORE_UNUSED,
|
||||
RK2928_CLKGATE_CON(0), 6, GFLAGS),
|
||||
|
||||
/*
|
||||
* Clock-Architecture Diagram 2
|
||||
*/
|
||||
|
||||
GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
|
||||
RK2928_CLKGATE_CON(0), 2, GFLAGS),
|
||||
GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
|
||||
RK2928_CLKGATE_CON(0), 8, GFLAGS),
|
||||
COMPOSITE_NOGATE(0, "ddrphy2x", mux_ddrphy_p, CLK_IGNORE_UNUSED,
|
||||
RK2928_CLKSEL_CON(26), 8, 1, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
|
||||
|
||||
COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED,
|
||||
RK2928_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
|
||||
RK2928_CLKGATE_CON(0), 7, GFLAGS),
|
||||
COMPOSITE_NOMUX(0, "aclk_core_pre", "armclk", CLK_IGNORE_UNUSED,
|
||||
RK2928_CLKSEL_CON(1), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
|
||||
RK2928_CLKGATE_CON(0), 7, GFLAGS),
|
||||
|
||||
GATE(0, "dpll_cpu", "dpll", 0, RK2928_CLKGATE_CON(10), 8, GFLAGS),
|
||||
GATE(0, "gpll_cpu", "gpll", 0, RK2928_CLKGATE_CON(0), 1, GFLAGS),
|
||||
COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_busclk_p, 0,
|
||||
RK2928_CLKSEL_CON(0), 14, 2, MFLAGS, 8, 5, DFLAGS),
|
||||
GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_src", CLK_IGNORE_UNUSED,
|
||||
RK2928_CLKGATE_CON(0), 3, GFLAGS),
|
||||
COMPOSITE_NOMUX(PCLK_CPU, "pclk_cpu", "aclk_cpu_src", CLK_IGNORE_UNUSED,
|
||||
RK2928_CLKSEL_CON(1), 12, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
|
||||
RK2928_CLKGATE_CON(0), 5, GFLAGS),
|
||||
COMPOSITE_NOMUX(HCLK_CPU, "hclk_cpu", "aclk_cpu_src", CLK_IGNORE_UNUSED,
|
||||
RK2928_CLKSEL_CON(1), 8, 2, DFLAGS | CLK_DIVIDER_READ_ONLY,
|
||||
RK2928_CLKGATE_CON(0), 4, GFLAGS),
|
||||
|
||||
COMPOSITE(0, "aclk_peri_src", mux_pll_src_3plls_p, 0,
|
||||
RK2928_CLKSEL_CON(10), 14, 2, MFLAGS, 0, 5, DFLAGS,
|
||||
RK2928_CLKGATE_CON(2), 0, GFLAGS),
|
||||
|
||||
GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 0,
|
||||
RK2928_CLKGATE_CON(2), 1, GFLAGS),
|
||||
DIV(0, "pclk_peri_src", "aclk_peri_src", CLK_IGNORE_UNUSED,
|
||||
RK2928_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
|
||||
GATE(PCLK_PERI, "pclk_peri", "pclk_peri_src", 0,
|
||||
RK2928_CLKGATE_CON(2), 3, GFLAGS),
|
||||
DIV(0, "hclk_peri_src", "aclk_peri_src", CLK_IGNORE_UNUSED,
|
||||
RK2928_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
|
||||
GATE(HCLK_PERI, "hclk_peri", "hclk_peri_src", 0,
|
||||
RK2928_CLKGATE_CON(2), 2, GFLAGS),
|
||||
|
||||
COMPOSITE_NODIV(SCLK_TIMER0, "sclk_timer0", mux_timer_p, CLK_IGNORE_UNUSED,
|
||||
RK2928_CLKSEL_CON(2), 4, 1, DFLAGS,
|
||||
RK2928_CLKGATE_CON(1), 0, GFLAGS),
|
||||
COMPOSITE_NODIV(SCLK_TIMER1, "sclk_timer1", mux_timer_p, CLK_IGNORE_UNUSED,
|
||||
RK2928_CLKSEL_CON(2), 5, 1, DFLAGS,
|
||||
RK2928_CLKGATE_CON(1), 1, GFLAGS),
|
||||
COMPOSITE_NODIV(SCLK_TIMER2, "sclk_timer2", mux_timer_p, CLK_IGNORE_UNUSED,
|
||||
RK2928_CLKSEL_CON(2), 6, 1, DFLAGS,
|
||||
RK2928_CLKGATE_CON(2), 4, GFLAGS),
|
||||
COMPOSITE_NODIV(SCLK_TIMER3, "sclk_timer3", mux_timer_p, CLK_IGNORE_UNUSED,
|
||||
RK2928_CLKSEL_CON(2), 7, 1, DFLAGS,
|
||||
RK2928_CLKGATE_CON(2), 5, GFLAGS),
|
||||
|
||||
MUX(0, "uart_pll_clk", mux_pll_src_apll_dpll_gpll_usb480m_p, 0,
|
||||
RK2928_CLKSEL_CON(13), 10, 2, MFLAGS),
|
||||
COMPOSITE_NOMUX(0, "uart0_src", "uart_pll_clk", 0,
|
||||
RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,
|
||||
RK2928_CLKGATE_CON(1), 8, GFLAGS),
|
||||
COMPOSITE_NOMUX(0, "uart1_src", "uart_pll_clk", 0,
|
||||
RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,
|
||||
RK2928_CLKGATE_CON(1), 8, GFLAGS),
|
||||
COMPOSITE_NOMUX(0, "uart2_src", "uart_pll_clk", 0,
|
||||
RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,
|
||||
RK2928_CLKGATE_CON(1), 8, GFLAGS),
|
||||
COMPOSITE_FRAC(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
|
||||
RK2928_CLKSEL_CON(17), 0,
|
||||
RK2928_CLKGATE_CON(1), 9, GFLAGS),
|
||||
COMPOSITE_FRAC(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
|
||||
RK2928_CLKSEL_CON(18), 0,
|
||||
RK2928_CLKGATE_CON(1), 11, GFLAGS),
|
||||
COMPOSITE_FRAC(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
|
||||
RK2928_CLKSEL_CON(19), 0,
|
||||
RK2928_CLKGATE_CON(1), 13, GFLAGS),
|
||||
MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
|
||||
RK2928_CLKSEL_CON(13), 8, 2, MFLAGS),
|
||||
MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
|
||||
RK2928_CLKSEL_CON(14), 8, 2, MFLAGS),
|
||||
MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
|
||||
RK2928_CLKSEL_CON(15), 8, 2, MFLAGS),
|
||||
|
||||
COMPOSITE(0, "aclk_vcodec", mux_pll_src_3plls_p, 0,
|
||||
RK2928_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS,
|
||||
RK2928_CLKGATE_CON(3), 11, GFLAGS),
|
||||
|
||||
COMPOSITE(0, "aclk_hvec", mux_pll_src_3plls_p, 0,
|
||||
RK2928_CLKSEL_CON(20), 0, 2, MFLAGS, 2, 5, DFLAGS,
|
||||
RK2928_CLKGATE_CON(10), 6, GFLAGS),
|
||||
|
||||
COMPOSITE(0, "aclk_disp1_pre", mux_pll_src_3plls_p, 0,
|
||||
RK2928_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS,
|
||||
RK2928_CLKGATE_CON(1), 4, GFLAGS),
|
||||
COMPOSITE(0, "hclk_disp_pre", mux_pll_src_3plls_p, 0,
|
||||
RK2928_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,
|
||||
RK2928_CLKGATE_CON(0), 11, GFLAGS),
|
||||
COMPOSITE(SCLK_LCDC, "dclk_lcdc", mux_pll_src_3plls_p, 0,
|
||||
RK2928_CLKSEL_CON(28), 0, 2, MFLAGS, 8, 8, DFLAGS,
|
||||
RK2928_CLKGATE_CON(3), 2, GFLAGS),
|
||||
|
||||
COMPOSITE_NODIV(0, "sclk_sdmmc_src", mux_mmc_src_p, 0,
|
||||
RK2928_CLKSEL_CON(12), 8, 2, DFLAGS,
|
||||
RK2928_CLKGATE_CON(2), 11, GFLAGS),
|
||||
DIV(SCLK_SDMMC, "sclk_sdmmc", "sclk_sdmmc_src", 0,
|
||||
RK2928_CLKSEL_CON(11), 0, 7, DFLAGS),
|
||||
|
||||
COMPOSITE_NODIV(0, "sclk_sdio_src", mux_mmc_src_p, 0,
|
||||
RK2928_CLKSEL_CON(12), 10, 2, DFLAGS,
|
||||
RK2928_CLKGATE_CON(2), 13, GFLAGS),
|
||||
DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0,
|
||||
RK2928_CLKSEL_CON(11), 8, 7, DFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0,
|
||||
RK2928_CLKSEL_CON(12), 12, 2, MFLAGS, 0, 7, DFLAGS,
|
||||
RK2928_CLKGATE_CON(2), 14, GFLAGS),
|
||||
|
||||
MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RK3036_SDMMC_CON0, 1),
|
||||
MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3036_SDMMC_CON1, 0),
|
||||
|
||||
MMC(SCLK_SDIO_DRV, "sdio_drv", "sclk_sdio", RK3036_SDIO_CON0, 1),
|
||||
MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "sclk_sdio", RK3036_SDIO_CON1, 0),
|
||||
|
||||
MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3036_EMMC_CON0, 1),
|
||||
MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3036_EMMC_CON1, 0),
|
||||
|
||||
COMPOSITE(0, "i2s_src", mux_pll_src_3plls_p, 0,
|
||||
RK2928_CLKSEL_CON(3), 14, 2, MFLAGS, 0, 7, DFLAGS,
|
||||
RK2928_CLKGATE_CON(0), 9, GFLAGS),
|
||||
COMPOSITE_FRAC(0, "i2s_frac", "i2s_src", CLK_SET_RATE_PARENT,
|
||||
RK2928_CLKSEL_CON(7), 0,
|
||||
RK2928_CLKGATE_CON(0), 10, GFLAGS),
|
||||
MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT,
|
||||
RK2928_CLKSEL_CON(3), 8, 2, MFLAGS),
|
||||
COMPOSITE_NODIV(SCLK_I2S_OUT, "i2s_clkout", mux_i2s_clkout_p, 0,
|
||||
RK2928_CLKSEL_CON(3), 12, 1, MFLAGS,
|
||||
RK2928_CLKGATE_CON(0), 13, GFLAGS),
|
||||
GATE(SCLK_I2S, "sclk_i2s", "i2s_pre", CLK_SET_RATE_PARENT,
|
||||
RK2928_CLKGATE_CON(0), 14, GFLAGS),
|
||||
|
||||
COMPOSITE(0, "spdif_src", mux_pll_src_3plls_p, 0,
|
||||
RK2928_CLKSEL_CON(5), 10, 2, MFLAGS, 0, 7, DFLAGS,
|
||||
RK2928_CLKGATE_CON(2), 10, GFLAGS),
|
||||
COMPOSITE_FRAC(0, "spdif_frac", "spdif_src", 0,
|
||||
RK2928_CLKSEL_CON(9), 0,
|
||||
RK2928_CLKGATE_CON(2), 12, GFLAGS),
|
||||
MUX(SCLK_SPDIF, "sclk_spdif", mux_spdif_p, 0,
|
||||
RK2928_CLKSEL_CON(5), 8, 2, MFLAGS),
|
||||
|
||||
GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin12m", CLK_IGNORE_UNUSED,
|
||||
RK2928_CLKGATE_CON(1), 5, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_GPU, "sclk_gpu", mux_pll_src_3plls_p, 0,
|
||||
RK2928_CLKSEL_CON(34), 8, 2, MFLAGS, 0, 5, DFLAGS,
|
||||
RK2928_CLKGATE_CON(3), 13, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_SPI, "sclk_spi", mux_pll_src_3plls_p, 0,
|
||||
RK2928_CLKSEL_CON(25), 8, 2, MFLAGS, 0, 7, DFLAGS,
|
||||
RK2928_CLKGATE_CON(2), 9, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_3plls_p, 0,
|
||||
RK2928_CLKSEL_CON(16), 8, 2, MFLAGS, 10, 5, DFLAGS,
|
||||
RK2928_CLKGATE_CON(10), 4, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_apll_dpll_gpll_usb480m_p, 0,
|
||||
RK2928_CLKSEL_CON(16), 0, 2, MFLAGS, 2, 5, DFLAGS,
|
||||
RK2928_CLKGATE_CON(10), 5, GFLAGS),
|
||||
|
||||
COMPOSITE_NOGATE(0, "mac_pll_src", mux_pll_src_3plls_p, 0,
|
||||
RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 4, 5, DFLAGS),
|
||||
MUX(SCLK_MACREF, "mac_clk_ref", mux_mac_p, CLK_SET_RATE_PARENT,
|
||||
RK2928_CLKSEL_CON(21), 3, 1, MFLAGS),
|
||||
|
||||
COMPOSITE_NOMUX(SCLK_MAC, "mac_clk", "mac_clk_ref", 0,
|
||||
RK2928_CLKSEL_CON(21), 9, 5, DFLAGS,
|
||||
RK2928_CLKGATE_CON(2), 6, GFLAGS),
|
||||
|
||||
MUX(SCLK_HDMI, "dclk_hdmi", mux_dclk_p, 0,
|
||||
RK2928_CLKSEL_CON(31), 0, 1, MFLAGS),
|
||||
|
||||
/*
|
||||
* Clock-Architecture Diagram 3
|
||||
*/
|
||||
|
||||
/* aclk_cpu gates */
|
||||
GATE(0, "sclk_intmem", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 12, GFLAGS),
|
||||
GATE(0, "aclk_strc_sys", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 10, GFLAGS),
|
||||
|
||||
/* hclk_cpu gates */
|
||||
GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 6, GFLAGS),
|
||||
|
||||
/* pclk_cpu gates */
|
||||
GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 4, GFLAGS),
|
||||
GATE(PCLK_DDRUPCTL, "pclk_ddrupctl", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 7, GFLAGS),
|
||||
GATE(PCLK_ACODEC, "pclk_acodec", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 14, GFLAGS),
|
||||
GATE(PCLK_HDMI, "pclk_hdmi", "pclk_cpu", 0, RK2928_CLKGATE_CON(3), 8, GFLAGS),
|
||||
|
||||
/* aclk_vio gates */
|
||||
GATE(ACLK_VIO, "aclk_vio", "aclk_disp1_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(6), 13, GFLAGS),
|
||||
GATE(ACLK_LCDC, "aclk_lcdc", "aclk_disp1_pre", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS),
|
||||
|
||||
GATE(HCLK_VIO_BUS, "hclk_vio_bus", "hclk_disp_pre", 0, RK2928_CLKGATE_CON(6), 12, GFLAGS),
|
||||
GATE(HCLK_LCDC, "hclk_lcdc", "hclk_disp_pre", 0, RK2928_CLKGATE_CON(9), 5, GFLAGS),
|
||||
|
||||
/* hclk_video gates */
|
||||
GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_disp_pre", 0, RK2928_CLKGATE_CON(3), 12, GFLAGS),
|
||||
|
||||
/* xin24m gates */
|
||||
GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK2928_CLKGATE_CON(10), 0, GFLAGS),
|
||||
GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 0, RK2928_CLKGATE_CON(10), 1, GFLAGS),
|
||||
|
||||
/* aclk_peri gates */
|
||||
GATE(0, "aclk_peri_axi_matrix", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 3, GFLAGS),
|
||||
GATE(0, "aclk_cpu_peri", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 2, GFLAGS),
|
||||
GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 1, GFLAGS),
|
||||
GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 15, GFLAGS),
|
||||
|
||||
/* hclk_peri gates */
|
||||
GATE(0, "hclk_peri_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 0, GFLAGS),
|
||||
GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 13, GFLAGS),
|
||||
GATE(0, "hclk_peri_arbi", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 14, GFLAGS),
|
||||
GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 9, GFLAGS),
|
||||
GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 10, GFLAGS),
|
||||
GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 11, GFLAGS),
|
||||
GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 0, GFLAGS),
|
||||
GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 13, GFLAGS),
|
||||
GATE(HCLK_OTG1, "hclk_otg1", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(7), 3, GFLAGS),
|
||||
GATE(HCLK_I2S, "hclk_i2s", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS),
|
||||
GATE(0, "hclk_sfc", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 14, GFLAGS),
|
||||
GATE(0, "hclk_mac", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 15, GFLAGS),
|
||||
|
||||
/* pclk_peri gates */
|
||||
GATE(0, "pclk_peri_matrix", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 1, GFLAGS),
|
||||
GATE(0, "pclk_efuse", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 2, GFLAGS),
|
||||
GATE(PCLK_TIMER, "pclk_timer", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 7, GFLAGS),
|
||||
GATE(PCLK_PWM, "pclk_pwm", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 10, GFLAGS),
|
||||
GATE(PCLK_SPI, "pclk_spi", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 12, GFLAGS),
|
||||
GATE(PCLK_WDT, "pclk_wdt", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 15, GFLAGS),
|
||||
GATE(PCLK_UART0, "pclk_uart0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),
|
||||
GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),
|
||||
GATE(PCLK_UART2, "pclk_uart2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 2, GFLAGS),
|
||||
GATE(PCLK_I2C0, "pclk_i2c0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS),
|
||||
GATE(PCLK_I2C1, "pclk_i2c1", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 5, GFLAGS),
|
||||
GATE(PCLK_I2C2, "pclk_i2c2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS),
|
||||
GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS),
|
||||
GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 10, GFLAGS),
|
||||
GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS),
|
||||
};
|
||||
|
||||
static const char *const rk3036_critical_clocks[] __initconst = {
|
||||
"aclk_cpu",
|
||||
"aclk_peri",
|
||||
"hclk_peri",
|
||||
"pclk_peri",
|
||||
};
|
||||
|
||||
static void __init rk3036_clk_init(struct device_node *np)
|
||||
{
|
||||
void __iomem *reg_base;
|
||||
struct clk *clk;
|
||||
|
||||
reg_base = of_iomap(np, 0);
|
||||
if (!reg_base) {
|
||||
pr_err("%s: could not map cru region\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
|
||||
|
||||
/* xin12m is created by an cru-internal divider */
|
||||
clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2);
|
||||
if (IS_ERR(clk))
|
||||
pr_warn("%s: could not register clock xin12m: %ld\n",
|
||||
__func__, PTR_ERR(clk));
|
||||
|
||||
clk = clk_register_fixed_factor(NULL, "usb480m", "xin24m", 0, 20, 1);
|
||||
if (IS_ERR(clk))
|
||||
pr_warn("%s: could not register clock usb480m: %ld\n",
|
||||
__func__, PTR_ERR(clk));
|
||||
|
||||
clk = clk_register_fixed_factor(NULL, "ddrphy", "ddrphy2x", 0, 1, 2);
|
||||
if (IS_ERR(clk))
|
||||
pr_warn("%s: could not register clock ddrphy: %ld\n",
|
||||
__func__, PTR_ERR(clk));
|
||||
|
||||
clk = clk_register_fixed_factor(NULL, "hclk_vcodec_pre",
|
||||
"aclk_vcodec", 0, 1, 4);
|
||||
if (IS_ERR(clk))
|
||||
pr_warn("%s: could not register clock hclk_vcodec_pre: %ld\n",
|
||||
__func__, PTR_ERR(clk));
|
||||
|
||||
clk = clk_register_fixed_factor(NULL, "sclk_macref_out",
|
||||
"hclk_peri_src", 0, 1, 2);
|
||||
if (IS_ERR(clk))
|
||||
pr_warn("%s: could not register clock sclk_macref_out: %ld\n",
|
||||
__func__, PTR_ERR(clk));
|
||||
|
||||
rockchip_clk_register_plls(rk3036_pll_clks,
|
||||
ARRAY_SIZE(rk3036_pll_clks),
|
||||
RK3036_GRF_SOC_STATUS0);
|
||||
rockchip_clk_register_branches(rk3036_clk_branches,
|
||||
ARRAY_SIZE(rk3036_clk_branches));
|
||||
rockchip_clk_protect_critical(rk3036_critical_clocks,
|
||||
ARRAY_SIZE(rk3036_critical_clocks));
|
||||
|
||||
rockchip_clk_register_armclk(ARMCLK, "armclk",
|
||||
mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
|
||||
&rk3036_cpuclk_data, rk3036_cpuclk_rates,
|
||||
ARRAY_SIZE(rk3036_cpuclk_rates));
|
||||
|
||||
rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
|
||||
ROCKCHIP_SOFTRST_HIWORD_MASK);
|
||||
|
||||
rockchip_register_restart_notifier(RK2928_GLB_SRST_FST, NULL);
|
||||
}
|
||||
CLK_OF_DECLARE(rk3036_cru, "rockchip,rk3036-cru", rk3036_clk_init);
|
||||
|
|
@ -750,7 +750,7 @@ static void __init rk3188_common_clk_init(struct device_node *np)
|
|||
rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
|
||||
ROCKCHIP_SOFTRST_HIWORD_MASK);
|
||||
|
||||
rockchip_register_restart_notifier(RK2928_GLB_SRST_FST);
|
||||
rockchip_register_restart_notifier(RK2928_GLB_SRST_FST, NULL);
|
||||
}
|
||||
|
||||
static void __init rk3066a_clk_init(struct device_node *np)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,678 @@
|
|||
/*
|
||||
* Copyright (c) 2015 Rockchip Electronics Co. Ltd.
|
||||
* Author: Xing Zheng <zhengxing@rock-chips.com>
|
||||
* Jeffy Chen <jeffy.chen@rock-chips.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/syscore_ops.h>
|
||||
#include <dt-bindings/clock/rk3228-cru.h>
|
||||
#include "clk.h"
|
||||
|
||||
#define RK3228_GRF_SOC_STATUS0 0x480
|
||||
|
||||
enum rk3228_plls {
|
||||
apll, dpll, cpll, gpll,
|
||||
};
|
||||
|
||||
static struct rockchip_pll_rate_table rk3228_pll_rates[] = {
|
||||
/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
|
||||
RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
|
||||
RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0),
|
||||
RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0),
|
||||
RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0),
|
||||
RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0),
|
||||
RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0),
|
||||
RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0),
|
||||
RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0),
|
||||
RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0),
|
||||
RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0),
|
||||
RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0),
|
||||
RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0),
|
||||
RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0),
|
||||
RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0),
|
||||
RK3036_PLL_RATE( 594000000, 2, 99, 2, 1, 1, 0),
|
||||
RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0),
|
||||
RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0),
|
||||
RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0),
|
||||
RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0),
|
||||
RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0),
|
||||
RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0),
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
#define RK3228_DIV_CPU_MASK 0x1f
|
||||
#define RK3228_DIV_CPU_SHIFT 8
|
||||
|
||||
#define RK3228_DIV_PERI_MASK 0xf
|
||||
#define RK3228_DIV_PERI_SHIFT 0
|
||||
#define RK3228_DIV_ACLK_MASK 0x7
|
||||
#define RK3228_DIV_ACLK_SHIFT 4
|
||||
#define RK3228_DIV_HCLK_MASK 0x3
|
||||
#define RK3228_DIV_HCLK_SHIFT 8
|
||||
#define RK3228_DIV_PCLK_MASK 0x7
|
||||
#define RK3228_DIV_PCLK_SHIFT 12
|
||||
|
||||
#define RK3228_CLKSEL1(_core_peri_div) \
|
||||
{ \
|
||||
.reg = RK2928_CLKSEL_CON(1), \
|
||||
.val = HIWORD_UPDATE(_core_peri_div, RK3228_DIV_PERI_MASK, \
|
||||
RK3228_DIV_PERI_SHIFT) \
|
||||
}
|
||||
|
||||
#define RK3228_CPUCLK_RATE(_prate, _core_peri_div) \
|
||||
{ \
|
||||
.prate = _prate, \
|
||||
.divs = { \
|
||||
RK3228_CLKSEL1(_core_peri_div), \
|
||||
}, \
|
||||
}
|
||||
|
||||
static struct rockchip_cpuclk_rate_table rk3228_cpuclk_rates[] __initdata = {
|
||||
RK3228_CPUCLK_RATE(816000000, 4),
|
||||
RK3228_CPUCLK_RATE(600000000, 4),
|
||||
RK3228_CPUCLK_RATE(312000000, 4),
|
||||
};
|
||||
|
||||
static const struct rockchip_cpuclk_reg_data rk3228_cpuclk_data = {
|
||||
.core_reg = RK2928_CLKSEL_CON(0),
|
||||
.div_core_shift = 0,
|
||||
.div_core_mask = 0x1f,
|
||||
.mux_core_shift = 6,
|
||||
};
|
||||
|
||||
PNAME(mux_pll_p) = { "clk_24m", "xin24m" };
|
||||
|
||||
PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr", "apll_ddr" };
|
||||
PNAME(mux_armclk_p) = { "apll_core", "gpll_core", "dpll_core" };
|
||||
PNAME(mux_usb480m_phy_p) = { "usb480m_phy0", "usb480m_phy1" };
|
||||
PNAME(mux_usb480m_p) = { "usb480m_phy", "xin24m" };
|
||||
PNAME(mux_hdmiphy_p) = { "hdmiphy_phy", "xin24m" };
|
||||
PNAME(mux_aclk_cpu_src_p) = { "cpll_aclk_cpu", "gpll_aclk_cpu", "hdmiphy_aclk_cpu" };
|
||||
|
||||
PNAME(mux_pll_src_4plls_p) = { "cpll", "gpll", "hdmiphy" "usb480m" };
|
||||
PNAME(mux_pll_src_3plls_p) = { "cpll", "gpll", "hdmiphy" };
|
||||
PNAME(mux_pll_src_2plls_p) = { "cpll", "gpll" };
|
||||
PNAME(mux_sclk_hdmi_cec_p) = { "cpll", "gpll", "xin24m" };
|
||||
PNAME(mux_aclk_peri_src_p) = { "cpll_peri", "gpll_peri", "hdmiphy_peri" };
|
||||
PNAME(mux_mmc_src_p) = { "cpll", "gpll", "xin24m", "usb480m" };
|
||||
PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "usb480m" };
|
||||
|
||||
PNAME(mux_sclk_rga_p) = { "gpll", "cpll", "sclk_rga_src" };
|
||||
|
||||
PNAME(mux_sclk_vop_src_p) = { "gpll_vop", "cpll_vop" };
|
||||
PNAME(mux_dclk_vop_p) = { "hdmiphy", "sclk_vop_pre" };
|
||||
|
||||
PNAME(mux_i2s0_p) = { "i2s0_src", "i2s0_frac", "ext_i2s", "xin12m" };
|
||||
PNAME(mux_i2s1_pre_p) = { "i2s1_src", "i2s1_frac", "ext_i2s", "xin12m" };
|
||||
PNAME(mux_i2s_out_p) = { "i2s1_pre", "xin12m" };
|
||||
PNAME(mux_i2s2_p) = { "i2s2_src", "i2s2_frac", "xin12m" };
|
||||
PNAME(mux_sclk_spdif_p) = { "sclk_spdif_src", "spdif_frac", "xin12m" };
|
||||
|
||||
PNAME(mux_aclk_gpu_pre_p) = { "cpll_gpu", "gpll_gpu", "hdmiphy_gpu", "usb480m_gpu" };
|
||||
|
||||
PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" };
|
||||
PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" };
|
||||
PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" };
|
||||
|
||||
PNAME(mux_sclk_macphy_50m_p) = { "ext_gmac", "phy_50m_out" };
|
||||
PNAME(mux_sclk_gmac_pre_p) = { "sclk_gmac_src", "sclk_macphy_50m" };
|
||||
PNAME(mux_sclk_macphy_p) = { "sclk_gmac_src", "ext_gmac" };
|
||||
|
||||
static struct rockchip_pll_clock rk3228_pll_clks[] __initdata = {
|
||||
[apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
|
||||
RK2928_MODE_CON, 0, 7, 0, rk3228_pll_rates),
|
||||
[dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(3),
|
||||
RK2928_MODE_CON, 4, 6, 0, NULL),
|
||||
[cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(6),
|
||||
RK2928_MODE_CON, 8, 8, 0, NULL),
|
||||
[gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(9),
|
||||
RK2928_MODE_CON, 12, 9, ROCKCHIP_PLL_SYNC_RATE, rk3228_pll_rates),
|
||||
};
|
||||
|
||||
#define MFLAGS CLK_MUX_HIWORD_MASK
|
||||
#define DFLAGS CLK_DIVIDER_HIWORD_MASK
|
||||
#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
|
||||
|
||||
static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
|
||||
/*
|
||||
* Clock-Architecture Diagram 1
|
||||
*/
|
||||
|
||||
DIV(0, "clk_24m", "xin24m", CLK_IGNORE_UNUSED,
|
||||
RK2928_CLKSEL_CON(4), 8, 5, DFLAGS),
|
||||
|
||||
/* PD_DDR */
|
||||
GATE(0, "apll_ddr", "apll", CLK_IGNORE_UNUSED,
|
||||
RK2928_CLKGATE_CON(0), 2, GFLAGS),
|
||||
GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
|
||||
RK2928_CLKGATE_CON(0), 2, GFLAGS),
|
||||
GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
|
||||
RK2928_CLKGATE_CON(0), 2, GFLAGS),
|
||||
COMPOSITE(0, "ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED,
|
||||
RK2928_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
|
||||
RK2928_CLKGATE_CON(7), 1, GFLAGS),
|
||||
GATE(0, "ddrc", "ddrphy_pre", CLK_IGNORE_UNUSED,
|
||||
RK2928_CLKGATE_CON(8), 5, GFLAGS),
|
||||
GATE(0, "ddrphy", "ddrphy_pre", CLK_IGNORE_UNUSED,
|
||||
RK2928_CLKGATE_CON(7), 0, GFLAGS),
|
||||
|
||||
/* PD_CORE */
|
||||
GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED,
|
||||
RK2928_CLKGATE_CON(0), 6, GFLAGS),
|
||||
GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
|
||||
RK2928_CLKGATE_CON(0), 6, GFLAGS),
|
||||
GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
|
||||
RK2928_CLKGATE_CON(0), 6, GFLAGS),
|
||||
COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED,
|
||||
RK2928_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
|
||||
RK2928_CLKGATE_CON(4), 1, GFLAGS),
|
||||
COMPOSITE_NOMUX(0, "armcore", "armclk", CLK_IGNORE_UNUSED,
|
||||
RK2928_CLKSEL_CON(1), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
|
||||
RK2928_CLKGATE_CON(4), 0, GFLAGS),
|
||||
|
||||
/* PD_MISC */
|
||||
MUX(0, "hdmiphy", mux_hdmiphy_p, CLK_SET_RATE_PARENT,
|
||||
RK2928_MISC_CON, 13, 1, MFLAGS),
|
||||
MUX(0, "usb480m_phy", mux_usb480m_phy_p, CLK_SET_RATE_PARENT,
|
||||
RK2928_MISC_CON, 14, 1, MFLAGS),
|
||||
MUX(0, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
|
||||
RK2928_MISC_CON, 15, 1, MFLAGS),
|
||||
|
||||
/* PD_BUS */
|
||||
GATE(0, "hdmiphy_aclk_cpu", "hdmiphy", CLK_IGNORE_UNUSED,
|
||||
RK2928_CLKGATE_CON(0), 1, GFLAGS),
|
||||
GATE(0, "gpll_aclk_cpu", "gpll", CLK_IGNORE_UNUSED,
|
||||
RK2928_CLKGATE_CON(0), 1, GFLAGS),
|
||||
GATE(0, "cpll_aclk_cpu", "cpll", CLK_IGNORE_UNUSED,
|
||||
RK2928_CLKGATE_CON(0), 1, GFLAGS),
|
||||
COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, 0,
|
||||
RK2928_CLKSEL_CON(0), 13, 2, MFLAGS, 8, 5, DFLAGS),
|
||||
GATE(ARMCLK, "aclk_cpu", "aclk_cpu_src", 0,
|
||||
RK2928_CLKGATE_CON(6), 0, GFLAGS),
|
||||
COMPOSITE_NOMUX(0, "hclk_cpu", "aclk_cpu_src", 0,
|
||||
RK2928_CLKSEL_CON(1), 8, 2, DFLAGS,
|
||||
RK2928_CLKGATE_CON(6), 1, GFLAGS),
|
||||
COMPOSITE_NOMUX(0, "pclk_bus_src", "aclk_cpu_src", 0,
|
||||
RK2928_CLKSEL_CON(1), 12, 3, DFLAGS,
|
||||
RK2928_CLKGATE_CON(6), 2, GFLAGS),
|
||||
GATE(0, "pclk_cpu", "pclk_bus_src", 0,
|
||||
RK2928_CLKGATE_CON(6), 3, GFLAGS),
|
||||
GATE(0, "pclk_phy_pre", "pclk_bus_src", 0,
|
||||
RK2928_CLKGATE_CON(6), 4, GFLAGS),
|
||||
GATE(0, "pclk_ddr_pre", "pclk_bus_src", 0,
|
||||
RK2928_CLKGATE_CON(6), 13, GFLAGS),
|
||||
|
||||
/* PD_VIDEO */
|
||||
COMPOSITE(0, "aclk_vpu_pre", mux_pll_src_4plls_p, 0,
|
||||
RK2928_CLKSEL_CON(32), 5, 2, MFLAGS, 0, 5, DFLAGS,
|
||||
RK2928_CLKGATE_CON(3), 11, GFLAGS),
|
||||
GATE(0, "hclk_vpu_src", "aclk_vpu_pre", 0,
|
||||
RK2928_CLKGATE_CON(4), 4, GFLAGS),
|
||||
|
||||
COMPOSITE(0, "aclk_rkvdec_pre", mux_pll_src_4plls_p, 0,
|
||||
RK2928_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 5, DFLAGS,
|
||||
RK2928_CLKGATE_CON(3), 2, GFLAGS),
|
||||
GATE(0, "hclk_rkvdec_src", "aclk_rkvdec_pre", 0,
|
||||
RK2928_CLKGATE_CON(4), 5, GFLAGS),
|
||||
|
||||
COMPOSITE(0, "sclk_vdec_cabac", mux_pll_src_4plls_p, 0,
|
||||
RK2928_CLKSEL_CON(28), 14, 2, MFLAGS, 8, 5, DFLAGS,
|
||||
RK2928_CLKGATE_CON(3), 3, GFLAGS),
|
||||
|
||||
COMPOSITE(0, "sclk_vdec_core", mux_pll_src_4plls_p, 0,
|
||||
RK2928_CLKSEL_CON(34), 13, 2, MFLAGS, 8, 5, DFLAGS,
|
||||
RK2928_CLKGATE_CON(3), 4, GFLAGS),
|
||||
|
||||
/* PD_VIO */
|
||||
COMPOSITE(0, "aclk_iep_pre", mux_pll_src_4plls_p, 0,
|
||||
RK2928_CLKSEL_CON(31), 5, 2, MFLAGS, 0, 5, DFLAGS,
|
||||
RK2928_CLKGATE_CON(3), 0, GFLAGS),
|
||||
DIV(0, "hclk_vio_pre", "aclk_iep_pre", 0,
|
||||
RK2928_CLKSEL_CON(2), 0, 5, DFLAGS),
|
||||
|
||||
COMPOSITE(0, "aclk_hdcp_pre", mux_pll_src_4plls_p, 0,
|
||||
RK2928_CLKSEL_CON(31), 13, 2, MFLAGS, 8, 5, DFLAGS,
|
||||
RK2928_CLKGATE_CON(1), 4, GFLAGS),
|
||||
|
||||
MUX(0, "sclk_rga_src", mux_pll_src_4plls_p, 0,
|
||||
RK2928_CLKSEL_CON(33), 13, 2, MFLAGS),
|
||||
COMPOSITE_NOMUX(0, "aclk_rga_pre", "sclk_rga_src", 0,
|
||||
RK2928_CLKSEL_CON(33), 8, 5, DFLAGS,
|
||||
RK2928_CLKGATE_CON(1), 2, GFLAGS),
|
||||
COMPOSITE(0, "sclk_rga", mux_sclk_rga_p, 0,
|
||||
RK2928_CLKSEL_CON(22), 5, 2, MFLAGS, 0, 5, DFLAGS,
|
||||
RK2928_CLKGATE_CON(3), 6, GFLAGS),
|
||||
|
||||
COMPOSITE(0, "aclk_vop_pre", mux_pll_src_4plls_p, 0,
|
||||
RK2928_CLKSEL_CON(33), 5, 2, MFLAGS, 0, 5, DFLAGS,
|
||||
RK2928_CLKGATE_CON(1), 1, GFLAGS),
|
||||
|
||||
COMPOSITE(0, "sclk_hdcp", mux_pll_src_3plls_p, 0,
|
||||
RK2928_CLKSEL_CON(23), 14, 2, MFLAGS, 8, 6, DFLAGS,
|
||||
RK2928_CLKGATE_CON(3), 5, GFLAGS),
|
||||
|
||||
GATE(0, "sclk_hdmi_hdcp", "xin24m", 0,
|
||||
RK2928_CLKGATE_CON(3), 7, GFLAGS),
|
||||
|
||||
COMPOSITE(0, "sclk_hdmi_cec", mux_sclk_hdmi_cec_p, 0,
|
||||
RK2928_CLKSEL_CON(21), 14, 2, MFLAGS, 0, 14, DFLAGS,
|
||||
RK2928_CLKGATE_CON(3), 8, GFLAGS),
|
||||
|
||||
/* PD_PERI */
|
||||
GATE(0, "cpll_peri", "cpll", CLK_IGNORE_UNUSED,
|
||||
RK2928_CLKGATE_CON(2), 0, GFLAGS),
|
||||
GATE(0, "gpll_peri", "gpll", CLK_IGNORE_UNUSED,
|
||||
RK2928_CLKGATE_CON(2), 0, GFLAGS),
|
||||
GATE(0, "hdmiphy_peri", "hdmiphy", CLK_IGNORE_UNUSED,
|
||||
RK2928_CLKGATE_CON(2), 0, GFLAGS),
|
||||
COMPOSITE_NOGATE(0, "aclk_peri_src", mux_aclk_peri_src_p, 0,
|
||||
RK2928_CLKSEL_CON(10), 10, 2, MFLAGS, 0, 5, DFLAGS),
|
||||
COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0,
|
||||
RK2928_CLKSEL_CON(10), 12, 3, DFLAGS,
|
||||
RK2928_CLKGATE_CON(5), 2, GFLAGS),
|
||||
COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", 0,
|
||||
RK2928_CLKSEL_CON(10), 8, 2, DFLAGS,
|
||||
RK2928_CLKGATE_CON(5), 1, GFLAGS),
|
||||
GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 0,
|
||||
RK2928_CLKGATE_CON(5), 0, GFLAGS),
|
||||
|
||||
GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
|
||||
RK2928_CLKGATE_CON(6), 5, GFLAGS),
|
||||
GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
|
||||
RK2928_CLKGATE_CON(6), 6, GFLAGS),
|
||||
GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
|
||||
RK2928_CLKGATE_CON(6), 7, GFLAGS),
|
||||
GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
|
||||
RK2928_CLKGATE_CON(6), 8, GFLAGS),
|
||||
GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
|
||||
RK2928_CLKGATE_CON(6), 9, GFLAGS),
|
||||
GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
|
||||
RK2928_CLKGATE_CON(6), 10, GFLAGS),
|
||||
|
||||
COMPOSITE(0, "sclk_crypto", mux_pll_src_2plls_p, 0,
|
||||
RK2928_CLKSEL_CON(24), 5, 1, MFLAGS, 0, 5, DFLAGS,
|
||||
RK2928_CLKGATE_CON(2), 7, GFLAGS),
|
||||
|
||||
COMPOSITE(0, "sclk_tsp", mux_pll_src_2plls_p, 0,
|
||||
RK2928_CLKSEL_CON(22), 15, 1, MFLAGS, 8, 5, DFLAGS,
|
||||
RK2928_CLKGATE_CON(2), 6, GFLAGS),
|
||||
|
||||
GATE(0, "sclk_hsadc", "ext_hsadc", 0,
|
||||
RK3288_CLKGATE_CON(10), 12, GFLAGS),
|
||||
|
||||
COMPOSITE(0, "sclk_wifi", mux_pll_src_cpll_gpll_usb480m_p, 0,
|
||||
RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, 0, 6, DFLAGS,
|
||||
RK2928_CLKGATE_CON(2), 15, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_SDMMC, "sclk_sdmmc0", mux_mmc_src_p, 0,
|
||||
RK2928_CLKSEL_CON(11), 8, 2, MFLAGS, 0, 8, DFLAGS,
|
||||
RK2928_CLKGATE_CON(2), 11, GFLAGS),
|
||||
|
||||
COMPOSITE_NODIV(0, "sclk_sdio_src", mux_mmc_src_p, 0,
|
||||
RK2928_CLKSEL_CON(11), 10, 2, MFLAGS,
|
||||
RK2928_CLKGATE_CON(2), 13, GFLAGS),
|
||||
DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0,
|
||||
RK2928_CLKSEL_CON(12), 0, 8, DFLAGS),
|
||||
|
||||
COMPOSITE_NODIV(0, "sclk_emmc_src", mux_mmc_src_p, 0,
|
||||
RK2928_CLKSEL_CON(11), 12, 2, MFLAGS,
|
||||
RK2928_CLKGATE_CON(2), 14, GFLAGS),
|
||||
DIV(SCLK_EMMC, "sclk_emmc", "sclk_emmc_src", 0,
|
||||
RK2928_CLKSEL_CON(12), 8, 8, DFLAGS),
|
||||
|
||||
/*
|
||||
* Clock-Architecture Diagram 2
|
||||
*/
|
||||
|
||||
GATE(0, "gpll_vop", "gpll", 0,
|
||||
RK2928_CLKGATE_CON(3), 1, GFLAGS),
|
||||
GATE(0, "cpll_vop", "cpll", 0,
|
||||
RK2928_CLKGATE_CON(3), 1, GFLAGS),
|
||||
MUX(0, "sclk_vop_src", mux_sclk_vop_src_p, 0,
|
||||
RK2928_CLKSEL_CON(27), 0, 1, MFLAGS),
|
||||
DIV(0, "dclk_hdmiphy", "sclk_vop_src", 0,
|
||||
RK2928_CLKSEL_CON(29), 0, 3, DFLAGS),
|
||||
DIV(0, "sclk_vop_pre", "sclk_vop_src", 0,
|
||||
RK2928_CLKSEL_CON(27), 8, 8, DFLAGS),
|
||||
MUX(0, "dclk_vop", mux_dclk_vop_p, 0,
|
||||
RK2928_CLKSEL_CON(27), 1, 1, MFLAGS),
|
||||
|
||||
COMPOSITE(0, "i2s0_src", mux_pll_src_2plls_p, 0,
|
||||
RK2928_CLKSEL_CON(9), 15, 1, MFLAGS, 0, 7, DFLAGS,
|
||||
RK2928_CLKGATE_CON(0), 3, GFLAGS),
|
||||
COMPOSITE_FRAC(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT,
|
||||
RK3288_CLKSEL_CON(8), 0,
|
||||
RK3288_CLKGATE_CON(0), 4, GFLAGS),
|
||||
COMPOSITE_NODIV(SCLK_I2S0, "sclk_i2s0", mux_i2s0_p, 0,
|
||||
RK2928_CLKSEL_CON(9), 8, 2, MFLAGS,
|
||||
RK2928_CLKGATE_CON(0), 5, GFLAGS),
|
||||
|
||||
COMPOSITE(0, "i2s1_src", mux_pll_src_2plls_p, 0,
|
||||
RK2928_CLKSEL_CON(3), 15, 1, MFLAGS, 0, 7, DFLAGS,
|
||||
RK2928_CLKGATE_CON(0), 10, GFLAGS),
|
||||
COMPOSITE_FRAC(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT,
|
||||
RK3288_CLKSEL_CON(7), 0,
|
||||
RK3288_CLKGATE_CON(0), 11, GFLAGS),
|
||||
MUX(0, "i2s1_pre", mux_i2s1_pre_p, 0,
|
||||
RK2928_CLKSEL_CON(3), 8, 2, MFLAGS),
|
||||
GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", 0,
|
||||
RK2928_CLKGATE_CON(0), 14, GFLAGS),
|
||||
COMPOSITE_NODIV(SCLK_I2S_OUT, "i2s_out", mux_i2s_out_p, 0,
|
||||
RK2928_CLKSEL_CON(3), 12, 1, MFLAGS,
|
||||
RK2928_CLKGATE_CON(0), 13, GFLAGS),
|
||||
|
||||
COMPOSITE(0, "i2s2_src", mux_pll_src_2plls_p, 0,
|
||||
RK2928_CLKSEL_CON(16), 15, 1, MFLAGS, 0, 7, DFLAGS,
|
||||
RK2928_CLKGATE_CON(0), 7, GFLAGS),
|
||||
COMPOSITE_FRAC(0, "i2s2_frac", "i2s2_src", CLK_SET_RATE_PARENT,
|
||||
RK3288_CLKSEL_CON(30), 0,
|
||||
RK3288_CLKGATE_CON(0), 8, GFLAGS),
|
||||
COMPOSITE_NODIV(SCLK_I2S2, "sclk_i2s2", mux_i2s2_p, 0,
|
||||
RK2928_CLKSEL_CON(16), 8, 2, MFLAGS,
|
||||
RK2928_CLKGATE_CON(0), 9, GFLAGS),
|
||||
|
||||
COMPOSITE(0, "sclk_spdif_src", mux_pll_src_2plls_p, 0,
|
||||
RK2928_CLKSEL_CON(6), 15, 1, MFLAGS, 0, 7, DFLAGS,
|
||||
RK2928_CLKGATE_CON(2), 10, GFLAGS),
|
||||
COMPOSITE_FRAC(0, "spdif_frac", "sclk_spdif_src", CLK_SET_RATE_PARENT,
|
||||
RK3288_CLKSEL_CON(20), 0,
|
||||
RK3288_CLKGATE_CON(2), 12, GFLAGS),
|
||||
MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, 0,
|
||||
RK2928_CLKSEL_CON(6), 8, 2, MFLAGS),
|
||||
|
||||
GATE(0, "jtag", "ext_jtag", 0,
|
||||
RK2928_CLKGATE_CON(1), 3, GFLAGS),
|
||||
|
||||
GATE(0, "sclk_otgphy0", "xin24m", 0,
|
||||
RK2928_CLKGATE_CON(1), 5, GFLAGS),
|
||||
GATE(0, "sclk_otgphy1", "xin24m", 0,
|
||||
RK2928_CLKGATE_CON(1), 6, GFLAGS),
|
||||
|
||||
COMPOSITE_NOMUX(0, "sclk_tsadc", "xin24m", 0,
|
||||
RK2928_CLKSEL_CON(24), 6, 10, DFLAGS,
|
||||
RK2928_CLKGATE_CON(2), 8, GFLAGS),
|
||||
|
||||
GATE(0, "cpll_gpu", "cpll", 0,
|
||||
RK2928_CLKGATE_CON(3), 13, GFLAGS),
|
||||
GATE(0, "gpll_gpu", "gpll", 0,
|
||||
RK2928_CLKGATE_CON(3), 13, GFLAGS),
|
||||
GATE(0, "hdmiphy_gpu", "hdmiphy", 0,
|
||||
RK2928_CLKGATE_CON(3), 13, GFLAGS),
|
||||
GATE(0, "usb480m_gpu", "usb480m", 0,
|
||||
RK2928_CLKGATE_CON(3), 13, GFLAGS),
|
||||
COMPOSITE_NOGATE(0, "aclk_gpu_pre", mux_aclk_gpu_pre_p, 0,
|
||||
RK2928_CLKSEL_CON(34), 5, 2, MFLAGS, 0, 5, DFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_2plls_p, 0,
|
||||
RK2928_CLKSEL_CON(25), 8, 1, MFLAGS, 0, 7, DFLAGS,
|
||||
RK2928_CLKGATE_CON(2), 9, GFLAGS),
|
||||
|
||||
/* PD_UART */
|
||||
COMPOSITE(0, "uart0_src", mux_pll_src_cpll_gpll_usb480m_p, 0,
|
||||
RK2928_CLKSEL_CON(13), 12, 2, MFLAGS, 0, 7, DFLAGS,
|
||||
RK2928_CLKGATE_CON(1), 8, GFLAGS),
|
||||
COMPOSITE(0, "uart1_src", mux_pll_src_cpll_gpll_usb480m_p, 0,
|
||||
RK2928_CLKSEL_CON(14), 12, 2, MFLAGS, 0, 7, DFLAGS,
|
||||
RK2928_CLKGATE_CON(1), 10, GFLAGS),
|
||||
COMPOSITE(0, "uart2_src", mux_pll_src_cpll_gpll_usb480m_p,
|
||||
0, RK2928_CLKSEL_CON(15), 12, 2,
|
||||
MFLAGS, 0, 7, DFLAGS, RK2928_CLKGATE_CON(1), 12, GFLAGS),
|
||||
COMPOSITE_FRAC(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
|
||||
RK2928_CLKSEL_CON(17), 0,
|
||||
RK2928_CLKGATE_CON(1), 9, GFLAGS),
|
||||
COMPOSITE_FRAC(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
|
||||
RK2928_CLKSEL_CON(18), 0,
|
||||
RK2928_CLKGATE_CON(1), 11, GFLAGS),
|
||||
COMPOSITE_FRAC(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
|
||||
RK2928_CLKSEL_CON(19), 0,
|
||||
RK2928_CLKGATE_CON(1), 13, GFLAGS),
|
||||
MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
|
||||
RK2928_CLKSEL_CON(13), 8, 2, MFLAGS),
|
||||
MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
|
||||
RK2928_CLKSEL_CON(14), 8, 2, MFLAGS),
|
||||
MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
|
||||
RK2928_CLKSEL_CON(15), 8, 2, MFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_2plls_p, 0,
|
||||
RK2928_CLKSEL_CON(2), 14, 1, MFLAGS, 8, 5, DFLAGS,
|
||||
RK2928_CLKGATE_CON(1), 0, GFLAGS),
|
||||
|
||||
COMPOSITE(0, "sclk_gmac_src", mux_pll_src_2plls_p, 0,
|
||||
RK2928_CLKSEL_CON(5), 7, 1, MFLAGS, 0, 5, DFLAGS,
|
||||
RK2928_CLKGATE_CON(1), 7, GFLAGS),
|
||||
MUX(0, "sclk_macphy_50m", mux_sclk_macphy_50m_p, 0,
|
||||
RK2928_CLKSEL_CON(29), 10, 1, MFLAGS),
|
||||
MUX(0, "sclk_gmac_pre", mux_sclk_gmac_pre_p, 0,
|
||||
RK2928_CLKSEL_CON(5), 5, 1, MFLAGS),
|
||||
GATE(0, "sclk_mac_refout", "sclk_gmac_pre", 0,
|
||||
RK2928_CLKGATE_CON(5), 4, GFLAGS),
|
||||
GATE(0, "sclk_mac_ref", "sclk_gmac_pre", 0,
|
||||
RK2928_CLKGATE_CON(5), 3, GFLAGS),
|
||||
GATE(0, "sclk_mac_rx", "sclk_gmac_pre", 0,
|
||||
RK2928_CLKGATE_CON(5), 5, GFLAGS),
|
||||
GATE(0, "sclk_mac_tx", "sclk_gmac_pre", 0,
|
||||
RK2928_CLKGATE_CON(5), 6, GFLAGS),
|
||||
COMPOSITE(0, "sclk_macphy", mux_sclk_macphy_p, 0,
|
||||
RK2928_CLKSEL_CON(29), 12, 1, MFLAGS, 8, 2, DFLAGS,
|
||||
RK2928_CLKGATE_CON(5), 7, GFLAGS),
|
||||
COMPOSITE(0, "sclk_gmac_out", mux_pll_src_2plls_p, 0,
|
||||
RK2928_CLKSEL_CON(5), 15, 1, MFLAGS, 8, 5, DFLAGS,
|
||||
RK2928_CLKGATE_CON(2), 2, GFLAGS),
|
||||
|
||||
/*
|
||||
* Clock-Architecture Diagram 3
|
||||
*/
|
||||
|
||||
/* PD_VOP */
|
||||
GATE(0, "aclk_rga", "aclk_rga_pre", 0, RK2928_CLKGATE_CON(13), 0, GFLAGS),
|
||||
GATE(0, "aclk_rga_noc", "aclk_rga_pre", 0, RK2928_CLKGATE_CON(13), 11, GFLAGS),
|
||||
GATE(0, "aclk_iep", "aclk_iep_pre", 0, RK2928_CLKGATE_CON(13), 2, GFLAGS),
|
||||
GATE(0, "aclk_iep_noc", "aclk_iep_pre", 0, RK2928_CLKGATE_CON(13), 9, GFLAGS),
|
||||
|
||||
GATE(0, "aclk_vop", "aclk_vop_pre", 0, RK2928_CLKGATE_CON(13), 5, GFLAGS),
|
||||
GATE(0, "aclk_vop_noc", "aclk_vop_pre", 0, RK2928_CLKGATE_CON(13), 12, GFLAGS),
|
||||
|
||||
GATE(0, "aclk_hdcp", "aclk_hdcp_pre", 0, RK2928_CLKGATE_CON(14), 10, GFLAGS),
|
||||
GATE(0, "aclk_hdcp_noc", "aclk_hdcp_pre", 0, RK2928_CLKGATE_CON(13), 10, GFLAGS),
|
||||
|
||||
GATE(0, "hclk_rga", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 1, GFLAGS),
|
||||
GATE(0, "hclk_iep", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 3, GFLAGS),
|
||||
GATE(0, "hclk_vop", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 6, GFLAGS),
|
||||
GATE(0, "hclk_vio_ahb_arbi", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 7, GFLAGS),
|
||||
GATE(0, "hclk_vio_noc", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 8, GFLAGS),
|
||||
GATE(0, "hclk_vop_noc", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 13, GFLAGS),
|
||||
GATE(0, "hclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 7, GFLAGS),
|
||||
GATE(0, "hclk_hdcp_mmu", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 12, GFLAGS),
|
||||
GATE(0, "pclk_hdmi_ctrl", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 6, GFLAGS),
|
||||
GATE(0, "pclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 8, GFLAGS),
|
||||
GATE(0, "pclk_hdcp", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 11, GFLAGS),
|
||||
|
||||
/* PD_PERI */
|
||||
GATE(0, "aclk_peri_noc", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 0, GFLAGS),
|
||||
GATE(0, "aclk_gmac", "aclk_peri", 0, RK2928_CLKGATE_CON(11), 4, GFLAGS),
|
||||
|
||||
GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 0, GFLAGS),
|
||||
GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 1, GFLAGS),
|
||||
GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 2, GFLAGS),
|
||||
GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 3, GFLAGS),
|
||||
GATE(0, "hclk_host0", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 6, GFLAGS),
|
||||
GATE(0, "hclk_host0_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 7, GFLAGS),
|
||||
GATE(0, "hclk_host1", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 8, GFLAGS),
|
||||
GATE(0, "hclk_host1_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 9, GFLAGS),
|
||||
GATE(0, "hclk_host2", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 10, GFLAGS),
|
||||
GATE(0, "hclk_otg", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 12, GFLAGS),
|
||||
GATE(0, "hclk_otg_pmu", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 13, GFLAGS),
|
||||
GATE(0, "hclk_host2_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 14, GFLAGS),
|
||||
GATE(0, "hclk_peri_noc", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 1, GFLAGS),
|
||||
|
||||
GATE(0, "pclk_gmac", "pclk_peri", 0, RK2928_CLKGATE_CON(11), 5, GFLAGS),
|
||||
GATE(0, "pclk_peri_noc", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 2, GFLAGS),
|
||||
|
||||
/* PD_GPU */
|
||||
GATE(0, "aclk_gpu", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(13), 14, GFLAGS),
|
||||
GATE(0, "aclk_gpu_noc", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(13), 15, GFLAGS),
|
||||
|
||||
/* PD_BUS */
|
||||
GATE(0, "sclk_initmem_mbist", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),
|
||||
GATE(0, "aclk_initmem", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),
|
||||
GATE(ACLK_DMAC, "aclk_dmac_bus", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), 2, GFLAGS),
|
||||
GATE(0, "aclk_bus_noc", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 1, GFLAGS),
|
||||
|
||||
GATE(0, "hclk_rom", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 3, GFLAGS),
|
||||
GATE(0, "hclk_i2s0_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 7, GFLAGS),
|
||||
GATE(0, "hclk_i2s1_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 8, GFLAGS),
|
||||
GATE(0, "hclk_i2s2_2ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS),
|
||||
GATE(0, "hclk_spdif_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 10, GFLAGS),
|
||||
GATE(0, "hclk_tsp", "hclk_cpu", 0, RK2928_CLKGATE_CON(10), 11, GFLAGS),
|
||||
GATE(0, "hclk_crypto_mst", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS),
|
||||
GATE(0, "hclk_crypto_slv", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 12, GFLAGS),
|
||||
|
||||
GATE(0, "pclk_ddrupctl", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS),
|
||||
GATE(0, "pclk_ddrmon", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS),
|
||||
GATE(0, "pclk_msch_noc", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(10), 2, GFLAGS),
|
||||
|
||||
GATE(0, "pclk_efuse_1024", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS),
|
||||
GATE(0, "pclk_efuse_256", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 14, GFLAGS),
|
||||
GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 15, GFLAGS),
|
||||
GATE(PCLK_I2C1, "pclk_i2c1", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 0, GFLAGS),
|
||||
GATE(PCLK_I2C2, "pclk_i2c2", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 1, GFLAGS),
|
||||
GATE(PCLK_I2C3, "pclk_i2c3", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 2, GFLAGS),
|
||||
GATE(PCLK_TIMER, "pclk_timer0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 4, GFLAGS),
|
||||
GATE(0, "pclk_stimer", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 5, GFLAGS),
|
||||
GATE(PCLK_SPI0, "pclk_spi0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS),
|
||||
GATE(PCLK_PWM, "pclk_rk_pwm", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 7, GFLAGS),
|
||||
GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 8, GFLAGS),
|
||||
GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 9, GFLAGS),
|
||||
GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 10, GFLAGS),
|
||||
GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 11, GFLAGS),
|
||||
GATE(PCLK_UART0, "pclk_uart0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 12, GFLAGS),
|
||||
GATE(PCLK_UART1, "pclk_uart1", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 13, GFLAGS),
|
||||
GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 14, GFLAGS),
|
||||
GATE(0, "pclk_tsadc", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 15, GFLAGS),
|
||||
GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 0, GFLAGS),
|
||||
GATE(0, "pclk_cru", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 1, GFLAGS),
|
||||
GATE(0, "pclk_sgrf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 2, GFLAGS),
|
||||
GATE(0, "pclk_sim", "pclk_cpu", 0, RK2928_CLKGATE_CON(10), 3, GFLAGS),
|
||||
|
||||
GATE(0, "pclk_ddrphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 3, GFLAGS),
|
||||
GATE(0, "pclk_acodecphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 5, GFLAGS),
|
||||
GATE(0, "pclk_hdmiphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 7, GFLAGS),
|
||||
GATE(0, "pclk_vdacphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 8, GFLAGS),
|
||||
GATE(0, "pclk_phy_noc", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 9, GFLAGS),
|
||||
|
||||
GATE(0, "aclk_vpu", "aclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 0, GFLAGS),
|
||||
GATE(0, "aclk_vpu_noc", "aclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 4, GFLAGS),
|
||||
GATE(0, "aclk_rkvdec", "aclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 2, GFLAGS),
|
||||
GATE(0, "aclk_rkvdec_noc", "aclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 6, GFLAGS),
|
||||
GATE(0, "hclk_vpu", "hclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 1, GFLAGS),
|
||||
GATE(0, "hclk_vpu_noc", "hclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 5, GFLAGS),
|
||||
GATE(0, "hclk_rkvdec", "hclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 3, GFLAGS),
|
||||
GATE(0, "hclk_rkvdec_noc", "hclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 7, GFLAGS),
|
||||
|
||||
/* PD_MMC */
|
||||
MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RK3228_SDMMC_CON0, 1),
|
||||
MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3228_SDMMC_CON1, 1),
|
||||
|
||||
MMC(SCLK_SDIO_DRV, "sdio_drv", "sclk_sdio", RK3228_SDIO_CON0, 1),
|
||||
MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "sclk_sdio", RK3228_SDIO_CON1, 1),
|
||||
|
||||
MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3228_EMMC_CON0, 1),
|
||||
MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3228_EMMC_CON1, 1),
|
||||
};
|
||||
|
||||
static const char *const rk3228_critical_clocks[] __initconst = {
|
||||
"aclk_cpu",
|
||||
"aclk_peri",
|
||||
"hclk_peri",
|
||||
"pclk_peri",
|
||||
};
|
||||
|
||||
static void __init rk3228_clk_init(struct device_node *np)
|
||||
{
|
||||
void __iomem *reg_base;
|
||||
struct clk *clk;
|
||||
|
||||
reg_base = of_iomap(np, 0);
|
||||
if (!reg_base) {
|
||||
pr_err("%s: could not map cru region\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
|
||||
|
||||
/* xin12m is created by an cru-internal divider */
|
||||
clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2);
|
||||
if (IS_ERR(clk))
|
||||
pr_warn("%s: could not register clock xin12m: %ld\n",
|
||||
__func__, PTR_ERR(clk));
|
||||
|
||||
clk = clk_register_fixed_factor(NULL, "ddrphy_pre", "ddrphy4x", 0, 1, 4);
|
||||
if (IS_ERR(clk))
|
||||
pr_warn("%s: could not register clock ddrphy_pre: %ld\n",
|
||||
__func__, PTR_ERR(clk));
|
||||
|
||||
clk = clk_register_fixed_factor(NULL, "hclk_vpu_pre",
|
||||
"hclk_vpu_src", 0, 1, 4);
|
||||
if (IS_ERR(clk))
|
||||
pr_warn("%s: could not register clock hclk_vpu_pre: %ld\n",
|
||||
__func__, PTR_ERR(clk));
|
||||
|
||||
clk = clk_register_fixed_factor(NULL, "hclk_rkvdec_pre",
|
||||
"hclk_rkvdec_src", 0, 1, 4);
|
||||
if (IS_ERR(clk))
|
||||
pr_warn("%s: could not register clock hclk_rkvdec_pre: %ld\n",
|
||||
__func__, PTR_ERR(clk));
|
||||
|
||||
rockchip_clk_register_plls(rk3228_pll_clks,
|
||||
ARRAY_SIZE(rk3228_pll_clks),
|
||||
RK3228_GRF_SOC_STATUS0);
|
||||
rockchip_clk_register_branches(rk3228_clk_branches,
|
||||
ARRAY_SIZE(rk3228_clk_branches));
|
||||
rockchip_clk_protect_critical(rk3228_critical_clocks,
|
||||
ARRAY_SIZE(rk3228_critical_clocks));
|
||||
|
||||
rockchip_clk_register_armclk(ARMCLK, "armclk",
|
||||
mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
|
||||
&rk3228_cpuclk_data, rk3228_cpuclk_rates,
|
||||
ARRAY_SIZE(rk3228_cpuclk_rates));
|
||||
|
||||
rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
|
||||
ROCKCHIP_SOFTRST_HIWORD_MASK);
|
||||
|
||||
rockchip_register_restart_notifier(RK3228_GLB_SRST_FST, NULL);
|
||||
}
|
||||
CLK_OF_DECLARE(rk3228_cru, "rockchip,rk3228-cru", rk3228_clk_init);
|
||||
|
|
@ -295,7 +295,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
|
|||
RK3288_CLKGATE_CON(0), 4, GFLAGS),
|
||||
GATE(0, "c2c_host", "aclk_cpu_src", 0,
|
||||
RK3288_CLKGATE_CON(13), 8, GFLAGS),
|
||||
COMPOSITE_NOMUX(0, "crypto", "aclk_cpu_pre", 0,
|
||||
COMPOSITE_NOMUX(SCLK_CRYPTO, "crypto", "aclk_cpu_pre", 0,
|
||||
RK3288_CLKSEL_CON(26), 6, 2, DFLAGS,
|
||||
RK3288_CLKGATE_CON(5), 4, GFLAGS),
|
||||
GATE(0, "aclk_bus_2pmu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,
|
||||
|
|
@ -644,10 +644,10 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
|
|||
GATE(PCLK_PUBL0, "pclk_publ0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 15, GFLAGS),
|
||||
GATE(PCLK_DDRUPCTL1, "pclk_ddrupctl1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 0, GFLAGS),
|
||||
GATE(PCLK_PUBL1, "pclk_publ1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 1, GFLAGS),
|
||||
GATE(0, "pclk_efuse_1024", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 2, GFLAGS),
|
||||
GATE(PCLK_EFUSE1024, "pclk_efuse_1024", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 2, GFLAGS),
|
||||
GATE(PCLK_TZPC, "pclk_tzpc", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 3, GFLAGS),
|
||||
GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 9, GFLAGS),
|
||||
GATE(0, "pclk_efuse_256", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 10, GFLAGS),
|
||||
GATE(PCLK_EFUSE256, "pclk_efuse_256", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 10, GFLAGS),
|
||||
GATE(PCLK_RKPWM, "pclk_rkpwm", "pclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 11, GFLAGS),
|
||||
|
||||
/* ddrctrl [DDR Controller PHY clock] gates */
|
||||
|
|
@ -709,7 +709,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
|
|||
GATE(SCLK_LCDC_PWM1, "sclk_lcdc_pwm1", "xin24m", 0, RK3288_CLKGATE_CON(13), 11, GFLAGS),
|
||||
GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK3288_CLKGATE_CON(5), 9, GFLAGS),
|
||||
GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 0, RK3288_CLKGATE_CON(5), 10, GFLAGS),
|
||||
GATE(0, "sclk_mipidsi_24m", "xin24m", 0, RK3288_CLKGATE_CON(5), 15, GFLAGS),
|
||||
GATE(SCLK_MIPIDSI_24M, "sclk_mipidsi_24m", "xin24m", 0, RK3288_CLKGATE_CON(5), 15, GFLAGS),
|
||||
|
||||
/* sclk_gpu gates */
|
||||
GATE(ACLK_GPU, "aclk_gpu", "sclk_gpu", 0, RK3288_CLKGATE_CON(18), 0, GFLAGS),
|
||||
|
|
@ -783,10 +783,10 @@ static const char *const rk3288_critical_clocks[] __initconst = {
|
|||
"pclk_pd_pmu",
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static void __iomem *rk3288_cru_base;
|
||||
|
||||
/* Some CRU registers will be reset in maskrom when the system
|
||||
/*
|
||||
* Some CRU registers will be reset in maskrom when the system
|
||||
* wakes up from fastboot.
|
||||
* So save them before suspend, restore them after resume.
|
||||
*/
|
||||
|
|
@ -840,33 +840,27 @@ static void rk3288_clk_resume(void)
|
|||
}
|
||||
}
|
||||
|
||||
static void rk3288_clk_shutdown(void)
|
||||
{
|
||||
writel_relaxed(0xf3030000, rk3288_cru_base + RK3288_MODE_CON);
|
||||
}
|
||||
|
||||
static struct syscore_ops rk3288_clk_syscore_ops = {
|
||||
.suspend = rk3288_clk_suspend,
|
||||
.resume = rk3288_clk_resume,
|
||||
};
|
||||
|
||||
static void rk3288_clk_sleep_init(void __iomem *reg_base)
|
||||
{
|
||||
rk3288_cru_base = reg_base;
|
||||
register_syscore_ops(&rk3288_clk_syscore_ops);
|
||||
}
|
||||
|
||||
#else /* CONFIG_PM_SLEEP */
|
||||
static void rk3288_clk_sleep_init(void __iomem *reg_base) {}
|
||||
#endif
|
||||
|
||||
static void __init rk3288_clk_init(struct device_node *np)
|
||||
{
|
||||
void __iomem *reg_base;
|
||||
struct clk *clk;
|
||||
|
||||
reg_base = of_iomap(np, 0);
|
||||
if (!reg_base) {
|
||||
rk3288_cru_base = of_iomap(np, 0);
|
||||
if (!rk3288_cru_base) {
|
||||
pr_err("%s: could not map cru region\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
|
||||
rockchip_clk_init(np, rk3288_cru_base, CLK_NR_CLKS);
|
||||
|
||||
/* xin12m is created by an cru-internal divider */
|
||||
clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2);
|
||||
|
|
@ -907,10 +901,12 @@ static void __init rk3288_clk_init(struct device_node *np)
|
|||
&rk3288_cpuclk_data, rk3288_cpuclk_rates,
|
||||
ARRAY_SIZE(rk3288_cpuclk_rates));
|
||||
|
||||
rockchip_register_softrst(np, 12, reg_base + RK3288_SOFTRST_CON(0),
|
||||
rockchip_register_softrst(np, 12,
|
||||
rk3288_cru_base + RK3288_SOFTRST_CON(0),
|
||||
ROCKCHIP_SOFTRST_HIWORD_MASK);
|
||||
|
||||
rockchip_register_restart_notifier(RK3288_GLB_SRST_FST);
|
||||
rk3288_clk_sleep_init(reg_base);
|
||||
rockchip_register_restart_notifier(RK3288_GLB_SRST_FST,
|
||||
rk3288_clk_shutdown);
|
||||
register_syscore_ops(&rk3288_clk_syscore_ops);
|
||||
}
|
||||
CLK_OF_DECLARE(rk3288_cru, "rockchip,rk3288-cru", rk3288_clk_init);
|
||||
|
|
|
|||
|
|
@ -184,13 +184,13 @@ static const struct rockchip_cpuclk_reg_data rk3368_cpuclkl_data = {
|
|||
|
||||
#define RK3368_CLKSEL0(_offs, _aclkm) \
|
||||
{ \
|
||||
.reg = RK3288_CLKSEL_CON(0 + _offs), \
|
||||
.reg = RK3368_CLKSEL_CON(0 + _offs), \
|
||||
.val = HIWORD_UPDATE(_aclkm, RK3368_DIV_ACLKM_MASK, \
|
||||
RK3368_DIV_ACLKM_SHIFT), \
|
||||
}
|
||||
#define RK3368_CLKSEL1(_offs, _atclk, _pdbg) \
|
||||
{ \
|
||||
.reg = RK3288_CLKSEL_CON(1 + _offs), \
|
||||
.reg = RK3368_CLKSEL_CON(1 + _offs), \
|
||||
.val = HIWORD_UPDATE(_atclk, RK3368_DIV_ATCLK_MASK, \
|
||||
RK3368_DIV_ATCLK_SHIFT) | \
|
||||
HIWORD_UPDATE(_pdbg, RK3368_DIV_PCLK_DBG_MASK, \
|
||||
|
|
@ -819,6 +819,13 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
|
|||
};
|
||||
|
||||
static const char *const rk3368_critical_clocks[] __initconst = {
|
||||
"aclk_bus",
|
||||
"aclk_peri",
|
||||
/*
|
||||
* pwm1 supplies vdd_logic on a lot of boards, is currently unhandled
|
||||
* but needs to stay enabled there (including its parents) at all times.
|
||||
*/
|
||||
"pclk_pwm1",
|
||||
"pclk_pd_pmu",
|
||||
};
|
||||
|
||||
|
|
@ -882,6 +889,6 @@ static void __init rk3368_clk_init(struct device_node *np)
|
|||
rockchip_register_softrst(np, 15, reg_base + RK3368_SOFTRST_CON(0),
|
||||
ROCKCHIP_SOFTRST_HIWORD_MASK);
|
||||
|
||||
rockchip_register_restart_notifier(RK3368_GLB_SRST_FST);
|
||||
rockchip_register_restart_notifier(RK3368_GLB_SRST_FST, NULL);
|
||||
}
|
||||
CLK_OF_DECLARE(rk3368_cru, "rockchip,rk3368-cru", rk3368_clk_init);
|
||||
|
|
|
|||
|
|
@ -341,9 +341,13 @@ void __init rockchip_clk_protect_critical(const char *const clocks[],
|
|||
}
|
||||
|
||||
static unsigned int reg_restart;
|
||||
static void (*cb_restart)(void);
|
||||
static int rockchip_restart_notify(struct notifier_block *this,
|
||||
unsigned long mode, void *cmd)
|
||||
{
|
||||
if (cb_restart)
|
||||
cb_restart();
|
||||
|
||||
writel(0xfdb9, reg_base + reg_restart);
|
||||
return NOTIFY_DONE;
|
||||
}
|
||||
|
|
@ -353,11 +357,12 @@ static struct notifier_block rockchip_restart_handler = {
|
|||
.priority = 128,
|
||||
};
|
||||
|
||||
void __init rockchip_register_restart_notifier(unsigned int reg)
|
||||
void __init rockchip_register_restart_notifier(unsigned int reg, void (*cb)(void))
|
||||
{
|
||||
int ret;
|
||||
|
||||
reg_restart = reg;
|
||||
cb_restart = cb;
|
||||
ret = register_restart_handler(&rockchip_restart_handler);
|
||||
if (ret)
|
||||
pr_err("%s: cannot register restart handler, %d\n",
|
||||
|
|
|
|||
|
|
@ -2,6 +2,9 @@
|
|||
* Copyright (c) 2014 MundoReader S.L.
|
||||
* Author: Heiko Stuebner <heiko@sntech.de>
|
||||
*
|
||||
* Copyright (c) 2015 Rockchip Electronics Co. Ltd.
|
||||
* Author: Xing Zheng <zhengxing@rock-chips.com>
|
||||
*
|
||||
* based on
|
||||
*
|
||||
* samsung/clk.h
|
||||
|
|
@ -30,7 +33,7 @@ struct clk;
|
|||
#define HIWORD_UPDATE(val, mask, shift) \
|
||||
((val) << (shift) | (mask) << ((shift) + 16))
|
||||
|
||||
/* register positions shared by RK2928, RK3066 and RK3188 */
|
||||
/* register positions shared by RK2928, RK3036, RK3066, RK3188 and RK3228 */
|
||||
#define RK2928_PLL_CON(x) ((x) * 0x4)
|
||||
#define RK2928_MODE_CON 0x40
|
||||
#define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44)
|
||||
|
|
@ -40,6 +43,22 @@ struct clk;
|
|||
#define RK2928_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
|
||||
#define RK2928_MISC_CON 0x134
|
||||
|
||||
#define RK3036_SDMMC_CON0 0x144
|
||||
#define RK3036_SDMMC_CON1 0x148
|
||||
#define RK3036_SDIO_CON0 0x14c
|
||||
#define RK3036_SDIO_CON1 0x150
|
||||
#define RK3036_EMMC_CON0 0x154
|
||||
#define RK3036_EMMC_CON1 0x158
|
||||
|
||||
#define RK3228_GLB_SRST_FST 0x1f0
|
||||
#define RK3228_GLB_SRST_SND 0x1f4
|
||||
#define RK3228_SDMMC_CON0 0x1c0
|
||||
#define RK3228_SDMMC_CON1 0x1c4
|
||||
#define RK3228_SDIO_CON0 0x1c8
|
||||
#define RK3228_SDIO_CON1 0x1cc
|
||||
#define RK3228_EMMC_CON0 0x1d8
|
||||
#define RK3228_EMMC_CON1 0x1dc
|
||||
|
||||
#define RK3288_PLL_CON(x) RK2928_PLL_CON(x)
|
||||
#define RK3288_MODE_CON 0x50
|
||||
#define RK3288_CLKSEL_CON(x) ((x) * 0x4 + 0x60)
|
||||
|
|
@ -74,9 +93,22 @@ struct clk;
|
|||
#define RK3368_EMMC_CON1 0x41c
|
||||
|
||||
enum rockchip_pll_type {
|
||||
pll_rk3036,
|
||||
pll_rk3066,
|
||||
};
|
||||
|
||||
#define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \
|
||||
_postdiv2, _dsmpd, _frac) \
|
||||
{ \
|
||||
.rate = _rate##U, \
|
||||
.fbdiv = _fbdiv, \
|
||||
.postdiv1 = _postdiv1, \
|
||||
.refdiv = _refdiv, \
|
||||
.postdiv2 = _postdiv2, \
|
||||
.dsmpd = _dsmpd, \
|
||||
.frac = _frac, \
|
||||
}
|
||||
|
||||
#define RK3066_PLL_RATE(_rate, _nr, _nf, _no) \
|
||||
{ \
|
||||
.rate = _rate##U, \
|
||||
|
|
@ -101,6 +133,13 @@ struct rockchip_pll_rate_table {
|
|||
unsigned int nf;
|
||||
unsigned int no;
|
||||
unsigned int nb;
|
||||
/* for RK3036 */
|
||||
unsigned int fbdiv;
|
||||
unsigned int postdiv1;
|
||||
unsigned int refdiv;
|
||||
unsigned int postdiv2;
|
||||
unsigned int dsmpd;
|
||||
unsigned int frac;
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
@ -464,7 +503,7 @@ void rockchip_clk_register_armclk(unsigned int lookup_id, const char *name,
|
|||
const struct rockchip_cpuclk_rate_table *rates,
|
||||
int nrates);
|
||||
void rockchip_clk_protect_critical(const char *const clocks[], int nclocks);
|
||||
void rockchip_register_restart_notifier(unsigned int reg);
|
||||
void rockchip_register_restart_notifier(unsigned int reg, void (*cb)(void));
|
||||
|
||||
#define ROCKCHIP_SOFTRST_HIWORD_MASK BIT(0)
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,193 @@
|
|||
/*
|
||||
* Copyright (c) 2015 Rockchip Electronics Co. Ltd.
|
||||
* Author: Xing Zheng <zhengxing@rock-chips.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H
|
||||
#define _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H
|
||||
|
||||
/* core clocks */
|
||||
#define PLL_APLL 1
|
||||
#define PLL_DPLL 2
|
||||
#define PLL_GPLL 3
|
||||
#define ARMCLK 4
|
||||
|
||||
/* sclk gates (special clocks) */
|
||||
#define SCLK_GPU 64
|
||||
#define SCLK_SPI 65
|
||||
#define SCLK_SDMMC 68
|
||||
#define SCLK_SDIO 69
|
||||
#define SCLK_EMMC 71
|
||||
#define SCLK_NANDC 76
|
||||
#define SCLK_UART0 77
|
||||
#define SCLK_UART1 78
|
||||
#define SCLK_UART2 79
|
||||
#define SCLK_I2S 82
|
||||
#define SCLK_SPDIF 83
|
||||
#define SCLK_TIMER0 85
|
||||
#define SCLK_TIMER1 86
|
||||
#define SCLK_TIMER2 87
|
||||
#define SCLK_TIMER3 88
|
||||
#define SCLK_OTGPHY0 93
|
||||
#define SCLK_LCDC 100
|
||||
#define SCLK_HDMI 109
|
||||
#define SCLK_HEVC 111
|
||||
#define SCLK_I2S_OUT 113
|
||||
#define SCLK_SDMMC_DRV 114
|
||||
#define SCLK_SDIO_DRV 115
|
||||
#define SCLK_EMMC_DRV 117
|
||||
#define SCLK_SDMMC_SAMPLE 118
|
||||
#define SCLK_SDIO_SAMPLE 119
|
||||
#define SCLK_EMMC_SAMPLE 121
|
||||
#define SCLK_PVTM_CORE 123
|
||||
#define SCLK_PVTM_GPU 124
|
||||
#define SCLK_PVTM_VIDEO 125
|
||||
#define SCLK_MAC 151
|
||||
#define SCLK_MACREF 152
|
||||
#define SCLK_SFC 160
|
||||
|
||||
/* aclk gates */
|
||||
#define ACLK_DMAC2 194
|
||||
#define ACLK_LCDC 197
|
||||
#define ACLK_VIO 203
|
||||
#define ACLK_VCODEC 208
|
||||
#define ACLK_CPU 209
|
||||
#define ACLK_PERI 210
|
||||
|
||||
/* pclk gates */
|
||||
#define PCLK_GPIO0 320
|
||||
#define PCLK_GPIO1 321
|
||||
#define PCLK_GPIO2 322
|
||||
#define PCLK_GRF 329
|
||||
#define PCLK_I2C0 332
|
||||
#define PCLK_I2C1 333
|
||||
#define PCLK_I2C2 334
|
||||
#define PCLK_SPI 338
|
||||
#define PCLK_UART0 341
|
||||
#define PCLK_UART1 342
|
||||
#define PCLK_UART2 343
|
||||
#define PCLK_PWM 350
|
||||
#define PCLK_TIMER 353
|
||||
#define PCLK_HDMI 360
|
||||
#define PCLK_CPU 362
|
||||
#define PCLK_PERI 363
|
||||
#define PCLK_DDRUPCTL 364
|
||||
#define PCLK_WDT 368
|
||||
#define PCLK_ACODEC 369
|
||||
|
||||
/* hclk gates */
|
||||
#define HCLK_OTG0 449
|
||||
#define HCLK_OTG1 450
|
||||
#define HCLK_NANDC 453
|
||||
#define HCLK_SDMMC 456
|
||||
#define HCLK_SDIO 457
|
||||
#define HCLK_EMMC 459
|
||||
#define HCLK_I2S 462
|
||||
#define HCLK_LCDC 465
|
||||
#define HCLK_ROM 467
|
||||
#define HCLK_VIO_BUS 472
|
||||
#define HCLK_VCODEC 476
|
||||
#define HCLK_CPU 477
|
||||
#define HCLK_PERI 478
|
||||
|
||||
#define CLK_NR_CLKS (HCLK_PERI + 1)
|
||||
|
||||
/* soft-reset indices */
|
||||
#define SRST_CORE0 0
|
||||
#define SRST_CORE1 1
|
||||
#define SRST_CORE0_DBG 4
|
||||
#define SRST_CORE1_DBG 5
|
||||
#define SRST_CORE0_POR 8
|
||||
#define SRST_CORE1_POR 9
|
||||
#define SRST_L2C 12
|
||||
#define SRST_TOPDBG 13
|
||||
#define SRST_STRC_SYS_A 14
|
||||
#define SRST_PD_CORE_NIU 15
|
||||
|
||||
#define SRST_TIMER2 16
|
||||
#define SRST_CPUSYS_H 17
|
||||
#define SRST_AHB2APB_H 19
|
||||
#define SRST_TIMER3 20
|
||||
#define SRST_INTMEM 21
|
||||
#define SRST_ROM 22
|
||||
#define SRST_PERI_NIU 23
|
||||
#define SRST_I2S 24
|
||||
#define SRST_DDR_PLL 25
|
||||
#define SRST_GPU_DLL 26
|
||||
#define SRST_TIMER0 27
|
||||
#define SRST_TIMER1 28
|
||||
#define SRST_CORE_DLL 29
|
||||
#define SRST_EFUSE_P 30
|
||||
#define SRST_ACODEC_P 31
|
||||
|
||||
#define SRST_GPIO0 32
|
||||
#define SRST_GPIO1 33
|
||||
#define SRST_GPIO2 34
|
||||
#define SRST_UART0 39
|
||||
#define SRST_UART1 40
|
||||
#define SRST_UART2 41
|
||||
#define SRST_I2C0 43
|
||||
#define SRST_I2C1 44
|
||||
#define SRST_I2C2 45
|
||||
#define SRST_SFC 47
|
||||
|
||||
#define SRST_PWM0 48
|
||||
#define SRST_DAP 51
|
||||
#define SRST_DAP_SYS 52
|
||||
#define SRST_GRF 55
|
||||
#define SRST_PERIPHSYS_A 57
|
||||
#define SRST_PERIPHSYS_H 58
|
||||
#define SRST_PERIPHSYS_P 59
|
||||
#define SRST_CPU_PERI 61
|
||||
#define SRST_EMEM_PERI 62
|
||||
#define SRST_USB_PERI 63
|
||||
|
||||
#define SRST_DMA2 64
|
||||
#define SRST_MAC 66
|
||||
#define SRST_NANDC 68
|
||||
#define SRST_USBOTG0 69
|
||||
#define SRST_OTGC0 71
|
||||
#define SRST_USBOTG1 72
|
||||
#define SRST_OTGC1 74
|
||||
#define SRST_DDRMSCH 79
|
||||
|
||||
#define SRST_MMC0 81
|
||||
#define SRST_SDIO 82
|
||||
#define SRST_EMMC 83
|
||||
#define SRST_SPI0 84
|
||||
#define SRST_WDT 86
|
||||
#define SRST_DDRPHY 88
|
||||
#define SRST_DDRPHY_P 89
|
||||
#define SRST_DDRCTRL 90
|
||||
#define SRST_DDRCTRL_P 91
|
||||
|
||||
#define SRST_HDMI_P 96
|
||||
#define SRST_VIO_BUS_H 99
|
||||
#define SRST_UTMI0 103
|
||||
#define SRST_UTMI1 104
|
||||
#define SRST_USBPOR 105
|
||||
|
||||
#define SRST_VCODEC_A 112
|
||||
#define SRST_VCODEC_H 113
|
||||
#define SRST_VIO1_A 114
|
||||
#define SRST_HEVC 115
|
||||
#define SRST_VCODEC_NIU_A 116
|
||||
#define SRST_LCDC1_A 117
|
||||
#define SRST_LCDC1_H 118
|
||||
#define SRST_LCDC1_D 119
|
||||
#define SRST_GPU 120
|
||||
#define SRST_GPU_NIU_A 122
|
||||
|
||||
#define SRST_DBG_P 131
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,220 @@
|
|||
/*
|
||||
* Copyright (c) 2015 Rockchip Electronics Co. Ltd.
|
||||
* Author: Jeffy Chen <jeffy.chen@rock-chips.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
|
||||
#define _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
|
||||
|
||||
/* core clocks */
|
||||
#define PLL_APLL 1
|
||||
#define PLL_DPLL 2
|
||||
#define PLL_CPLL 3
|
||||
#define PLL_GPLL 4
|
||||
#define ARMCLK 5
|
||||
|
||||
/* sclk gates (special clocks) */
|
||||
#define SCLK_SPI0 65
|
||||
#define SCLK_NANDC 67
|
||||
#define SCLK_SDMMC 68
|
||||
#define SCLK_SDIO 69
|
||||
#define SCLK_EMMC 71
|
||||
#define SCLK_UART0 77
|
||||
#define SCLK_UART1 78
|
||||
#define SCLK_UART2 79
|
||||
#define SCLK_I2S0 80
|
||||
#define SCLK_I2S1 81
|
||||
#define SCLK_I2S2 82
|
||||
#define SCLK_SPDIF 83
|
||||
#define SCLK_TIMER0 85
|
||||
#define SCLK_TIMER1 86
|
||||
#define SCLK_TIMER2 87
|
||||
#define SCLK_TIMER3 88
|
||||
#define SCLK_TIMER4 89
|
||||
#define SCLK_TIMER5 90
|
||||
#define SCLK_I2S_OUT 113
|
||||
#define SCLK_SDMMC_DRV 114
|
||||
#define SCLK_SDIO_DRV 115
|
||||
#define SCLK_EMMC_DRV 117
|
||||
#define SCLK_SDMMC_SAMPLE 118
|
||||
#define SCLK_SDIO_SAMPLE 119
|
||||
#define SCLK_EMMC_SAMPLE 121
|
||||
|
||||
/* aclk gates */
|
||||
#define ACLK_DMAC 194
|
||||
#define ACLK_PERI 210
|
||||
|
||||
/* pclk gates */
|
||||
#define PCLK_GPIO0 320
|
||||
#define PCLK_GPIO1 321
|
||||
#define PCLK_GPIO2 322
|
||||
#define PCLK_GPIO3 323
|
||||
#define PCLK_GRF 329
|
||||
#define PCLK_I2C0 332
|
||||
#define PCLK_I2C1 333
|
||||
#define PCLK_I2C2 334
|
||||
#define PCLK_I2C3 335
|
||||
#define PCLK_SPI0 338
|
||||
#define PCLK_UART0 341
|
||||
#define PCLK_UART1 342
|
||||
#define PCLK_UART2 343
|
||||
#define PCLK_PWM 350
|
||||
#define PCLK_TIMER 353
|
||||
#define PCLK_PERI 363
|
||||
|
||||
/* hclk gates */
|
||||
#define HCLK_NANDC 453
|
||||
#define HCLK_SDMMC 456
|
||||
#define HCLK_SDIO 457
|
||||
#define HCLK_EMMC 459
|
||||
#define HCLK_PERI 478
|
||||
|
||||
#define CLK_NR_CLKS (HCLK_PERI + 1)
|
||||
|
||||
/* soft-reset indices */
|
||||
#define SRST_CORE0_PO 0
|
||||
#define SRST_CORE1_PO 1
|
||||
#define SRST_CORE2_PO 2
|
||||
#define SRST_CORE3_PO 3
|
||||
#define SRST_CORE0 4
|
||||
#define SRST_CORE1 5
|
||||
#define SRST_CORE2 6
|
||||
#define SRST_CORE3 7
|
||||
#define SRST_CORE0_DBG 8
|
||||
#define SRST_CORE1_DBG 9
|
||||
#define SRST_CORE2_DBG 10
|
||||
#define SRST_CORE3_DBG 11
|
||||
#define SRST_TOPDBG 12
|
||||
#define SRST_ACLK_CORE 13
|
||||
#define SRST_NOC 14
|
||||
#define SRST_L2C 15
|
||||
|
||||
#define SRST_CPUSYS_H 18
|
||||
#define SRST_BUSSYS_H 19
|
||||
#define SRST_SPDIF 20
|
||||
#define SRST_INTMEM 21
|
||||
#define SRST_ROM 22
|
||||
#define SRST_OTG_ADP 23
|
||||
#define SRST_I2S0 24
|
||||
#define SRST_I2S1 25
|
||||
#define SRST_I2S2 26
|
||||
#define SRST_ACODEC_P 27
|
||||
#define SRST_DFIMON 28
|
||||
#define SRST_MSCH 29
|
||||
#define SRST_EFUSE1024 30
|
||||
#define SRST_EFUSE256 31
|
||||
|
||||
#define SRST_GPIO0 32
|
||||
#define SRST_GPIO1 33
|
||||
#define SRST_GPIO2 34
|
||||
#define SRST_GPIO3 35
|
||||
#define SRST_PERIPH_NOC_A 36
|
||||
#define SRST_PERIPH_NOC_BUS_H 37
|
||||
#define SRST_PERIPH_NOC_P 38
|
||||
#define SRST_UART0 39
|
||||
#define SRST_UART1 40
|
||||
#define SRST_UART2 41
|
||||
#define SRST_PHYNOC 42
|
||||
#define SRST_I2C0 43
|
||||
#define SRST_I2C1 44
|
||||
#define SRST_I2C2 45
|
||||
#define SRST_I2C3 46
|
||||
|
||||
#define SRST_PWM 48
|
||||
#define SRST_A53_GIC 49
|
||||
#define SRST_DAP 51
|
||||
#define SRST_DAP_NOC 52
|
||||
#define SRST_CRYPTO 53
|
||||
#define SRST_SGRF 54
|
||||
#define SRST_GRF 55
|
||||
#define SRST_GMAC 56
|
||||
#define SRST_PERIPH_NOC_H 58
|
||||
#define SRST_MACPHY 63
|
||||
|
||||
#define SRST_DMA 64
|
||||
#define SRST_NANDC 68
|
||||
#define SRST_USBOTG 69
|
||||
#define SRST_OTGC 70
|
||||
#define SRST_USBHOST0 71
|
||||
#define SRST_HOST_CTRL0 72
|
||||
#define SRST_USBHOST1 73
|
||||
#define SRST_HOST_CTRL1 74
|
||||
#define SRST_USBHOST2 75
|
||||
#define SRST_HOST_CTRL2 76
|
||||
#define SRST_USBPOR0 77
|
||||
#define SRST_USBPOR1 78
|
||||
#define SRST_DDRMSCH 79
|
||||
|
||||
#define SRST_SMART_CARD 80
|
||||
#define SRST_SDMMC 81
|
||||
#define SRST_SDIO 82
|
||||
#define SRST_EMMC 83
|
||||
#define SRST_SPI 84
|
||||
#define SRST_TSP_H 85
|
||||
#define SRST_TSP 86
|
||||
#define SRST_TSADC 87
|
||||
#define SRST_DDRPHY 88
|
||||
#define SRST_DDRPHY_P 89
|
||||
#define SRST_DDRCTRL 90
|
||||
#define SRST_DDRCTRL_P 91
|
||||
#define SRST_HOST0_ECHI 92
|
||||
#define SRST_HOST1_ECHI 93
|
||||
#define SRST_HOST2_ECHI 94
|
||||
#define SRST_VOP_NOC_A 95
|
||||
|
||||
#define SRST_HDMI_P 96
|
||||
#define SRST_VIO_ARBI_H 97
|
||||
#define SRST_IEP_NOC_A 98
|
||||
#define SRST_VIO_NOC_H 99
|
||||
#define SRST_VOP_A 100
|
||||
#define SRST_VOP_H 101
|
||||
#define SRST_VOP_D 102
|
||||
#define SRST_UTMI0 103
|
||||
#define SRST_UTMI1 104
|
||||
#define SRST_UTMI2 105
|
||||
#define SRST_UTMI3 106
|
||||
#define SRST_RGA 107
|
||||
#define SRST_RGA_NOC_A 108
|
||||
#define SRST_RGA_A 109
|
||||
#define SRST_RGA_H 110
|
||||
#define SRST_HDCP_A 111
|
||||
|
||||
#define SRST_VPU_A 112
|
||||
#define SRST_VPU_H 113
|
||||
#define SRST_VPU_NOC_A 116
|
||||
#define SRST_VPU_NOC_H 117
|
||||
#define SRST_RKVDEC_A 118
|
||||
#define SRST_RKVDEC_NOC_A 119
|
||||
#define SRST_RKVDEC_H 120
|
||||
#define SRST_RKVDEC_NOC_H 121
|
||||
#define SRST_RKVDEC_CORE 122
|
||||
#define SRST_RKVDEC_CABAC 123
|
||||
#define SRST_IEP_A 124
|
||||
#define SRST_IEP_H 125
|
||||
#define SRST_GPU_A 126
|
||||
#define SRST_GPU_NOC_A 127
|
||||
|
||||
#define SRST_CORE_DBG 128
|
||||
#define SRST_DBG_P 129
|
||||
#define SRST_TIMER0 130
|
||||
#define SRST_TIMER1 131
|
||||
#define SRST_TIMER2 132
|
||||
#define SRST_TIMER3 133
|
||||
#define SRST_TIMER4 134
|
||||
#define SRST_TIMER5 135
|
||||
#define SRST_VIO_H2P 136
|
||||
#define SRST_HDMIPHY 139
|
||||
#define SRST_VDAC 140
|
||||
#define SRST_TIMER_6CH_P 141
|
||||
|
||||
#endif
|
||||
|
|
@ -86,6 +86,8 @@
|
|||
#define SCLK_USBPHY480M_SRC 122
|
||||
#define SCLK_PVTM_CORE 123
|
||||
#define SCLK_PVTM_GPU 124
|
||||
#define SCLK_CRYPTO 125
|
||||
#define SCLK_MIPIDSI_24M 126
|
||||
|
||||
#define SCLK_MAC 151
|
||||
#define SCLK_MACREF_OUT 152
|
||||
|
|
@ -164,6 +166,8 @@
|
|||
#define PCLK_DDRUPCTL1 366
|
||||
#define PCLK_PUBL1 367
|
||||
#define PCLK_WDT 368
|
||||
#define PCLK_EFUSE256 369
|
||||
#define PCLK_EFUSE1024 370
|
||||
|
||||
/* hclk gates */
|
||||
#define HCLK_GPS 448
|
||||
|
|
|
|||
Загрузка…
Ссылка в новой задаче