i40e: Allow RSS Hash set with less than four parameters
This patch implements a feature change which allows using ethtool to set RSS hash opts using less than four parameters if desired. Change-ID: I0fbb91255d81e997c456697c21ac39cc9754821b Signed-off-by: Carolyn Wyborny <carolyn.wyborny@intel.com> Signed-off-by: Kiran Patil <kiran.patil@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
This commit is contained in:
Carolyn Wyborny
Jeff Kirsher
Родитель
b7d2cd951f
Коммит
eb0dd6e4a3
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@ -586,9 +586,6 @@ struct i40e_vsi {
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/* VSI specific handlers */
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irqreturn_t (*irq_handler)(int irq, void *data);
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/* current rxnfc data */
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struct ethtool_rxnfc rxnfc; /* current rss hash opts */
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} ____cacheline_internodealigned_in_smp;
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struct i40e_netdev_priv {
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@ -2141,41 +2141,72 @@ static int i40e_set_per_queue_coalesce(struct net_device *netdev, u32 queue,
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**/
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static int i40e_get_rss_hash_opts(struct i40e_pf *pf, struct ethtool_rxnfc *cmd)
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{
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struct i40e_hw *hw = &pf->hw;
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u8 flow_pctype = 0;
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u64 i_set = 0;
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cmd->data = 0;
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if (pf->vsi[pf->lan_vsi]->rxnfc.data != 0) {
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cmd->data = pf->vsi[pf->lan_vsi]->rxnfc.data;
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cmd->flow_type = pf->vsi[pf->lan_vsi]->rxnfc.flow_type;
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return 0;
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}
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/* Report default options for RSS on i40e */
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switch (cmd->flow_type) {
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case TCP_V4_FLOW:
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flow_pctype = I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
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break;
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case UDP_V4_FLOW:
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cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
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/* fall through to add IP fields */
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flow_pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
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break;
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case TCP_V6_FLOW:
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flow_pctype = I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
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break;
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case UDP_V6_FLOW:
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flow_pctype = I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
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break;
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case SCTP_V4_FLOW:
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case AH_ESP_V4_FLOW:
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case AH_V4_FLOW:
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case ESP_V4_FLOW:
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case IPV4_FLOW:
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cmd->data |= RXH_IP_SRC | RXH_IP_DST;
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break;
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case TCP_V6_FLOW:
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case UDP_V6_FLOW:
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cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
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/* fall through to add IP fields */
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case SCTP_V6_FLOW:
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case AH_ESP_V6_FLOW:
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case AH_V6_FLOW:
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case ESP_V6_FLOW:
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case IPV6_FLOW:
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/* Default is src/dest for IP, no matter the L4 hashing */
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cmd->data |= RXH_IP_SRC | RXH_IP_DST;
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break;
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default:
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return -EINVAL;
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}
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/* Read flow based hash input set register */
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if (flow_pctype) {
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i_set = (u64)i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0,
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flow_pctype)) |
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((u64)i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1,
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flow_pctype)) << 32);
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}
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/* Process bits of hash input set */
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if (i_set) {
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if (i_set & I40E_L4_SRC_MASK)
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cmd->data |= RXH_L4_B_0_1;
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if (i_set & I40E_L4_DST_MASK)
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cmd->data |= RXH_L4_B_2_3;
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if (cmd->flow_type == TCP_V4_FLOW ||
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cmd->flow_type == UDP_V4_FLOW) {
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if (i_set & I40E_L3_SRC_MASK)
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cmd->data |= RXH_IP_SRC;
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if (i_set & I40E_L3_DST_MASK)
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cmd->data |= RXH_IP_DST;
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} else if (cmd->flow_type == TCP_V6_FLOW ||
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cmd->flow_type == UDP_V6_FLOW) {
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if (i_set & I40E_L3_V6_SRC_MASK)
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cmd->data |= RXH_IP_SRC;
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if (i_set & I40E_L3_V6_DST_MASK)
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cmd->data |= RXH_IP_DST;
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}
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}
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return 0;
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}
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@ -2317,6 +2348,51 @@ static int i40e_get_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd,
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return ret;
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}
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/**
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* i40e_get_rss_hash_bits - Read RSS Hash bits from register
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* @nfc: pointer to user request
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* @i_setc bits currently set
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*
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* Returns value of bits to be set per user request
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**/
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static u64 i40e_get_rss_hash_bits(struct ethtool_rxnfc *nfc, u64 i_setc)
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{
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u64 i_set = i_setc;
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u64 src_l3 = 0, dst_l3 = 0;
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if (nfc->data & RXH_L4_B_0_1)
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i_set |= I40E_L4_SRC_MASK;
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else
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i_set &= ~I40E_L4_SRC_MASK;
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if (nfc->data & RXH_L4_B_2_3)
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i_set |= I40E_L4_DST_MASK;
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else
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i_set &= ~I40E_L4_DST_MASK;
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if (nfc->flow_type == TCP_V6_FLOW || nfc->flow_type == UDP_V6_FLOW) {
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src_l3 = I40E_L3_V6_SRC_MASK;
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dst_l3 = I40E_L3_V6_DST_MASK;
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} else if (nfc->flow_type == TCP_V4_FLOW ||
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nfc->flow_type == UDP_V4_FLOW) {
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src_l3 = I40E_L3_SRC_MASK;
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dst_l3 = I40E_L3_DST_MASK;
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} else {
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/* Any other flow type are not supported here */
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return i_set;
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}
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if (nfc->data & RXH_IP_SRC)
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i_set |= src_l3;
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else
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i_set &= ~src_l3;
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if (nfc->data & RXH_IP_DST)
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i_set |= dst_l3;
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else
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i_set &= ~dst_l3;
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return i_set;
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}
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/**
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* i40e_set_rss_hash_opt - Enable/Disable flow types for RSS hash
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* @pf: pointer to the physical function struct
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@ -2329,6 +2405,8 @@ static int i40e_set_rss_hash_opt(struct i40e_pf *pf, struct ethtool_rxnfc *nfc)
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struct i40e_hw *hw = &pf->hw;
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u64 hena = (u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0)) |
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((u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1)) << 32);
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u8 flow_pctype = 0;
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u64 i_set, i_setc;
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/* RSS does not support anything other than hashing
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* to queues on src and dst IPs and ports
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@ -2337,75 +2415,39 @@ static int i40e_set_rss_hash_opt(struct i40e_pf *pf, struct ethtool_rxnfc *nfc)
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RXH_L4_B_0_1 | RXH_L4_B_2_3))
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return -EINVAL;
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/* We need at least the IP SRC and DEST fields for hashing */
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if (!(nfc->data & RXH_IP_SRC) ||
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!(nfc->data & RXH_IP_DST))
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return -EINVAL;
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switch (nfc->flow_type) {
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case TCP_V4_FLOW:
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switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
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case 0:
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return -EINVAL;
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case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
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flow_pctype = I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
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if (pf->flags & I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE)
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hena |=
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BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
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hena |= BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP);
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break;
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default:
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return -EINVAL;
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}
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break;
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case TCP_V6_FLOW:
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switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
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case 0:
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return -EINVAL;
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case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
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flow_pctype = I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
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if (pf->flags & I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE)
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hena |=
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BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
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if (pf->flags & I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE)
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hena |=
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BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
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hena |= BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP);
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break;
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default:
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return -EINVAL;
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}
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break;
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case UDP_V4_FLOW:
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switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
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case 0:
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return -EINVAL;
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case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
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flow_pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
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if (pf->flags & I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE)
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hena |=
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BIT_ULL(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
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BIT_ULL(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
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hena |= (BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
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BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV4));
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break;
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default:
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return -EINVAL;
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}
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hena |= BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV4);
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break;
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case UDP_V6_FLOW:
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switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
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case 0:
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return -EINVAL;
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case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
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flow_pctype = I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
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if (pf->flags & I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE)
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hena |=
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BIT_ULL(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
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BIT_ULL(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
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hena |= (BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
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BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV6));
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break;
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default:
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return -EINVAL;
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}
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hena |= BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV6);
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break;
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case AH_ESP_V4_FLOW:
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case AH_V4_FLOW:
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@ -2437,13 +2479,23 @@ static int i40e_set_rss_hash_opt(struct i40e_pf *pf, struct ethtool_rxnfc *nfc)
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return -EINVAL;
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}
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if (flow_pctype) {
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i_setc = (u64)i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0,
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flow_pctype)) |
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((u64)i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1,
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flow_pctype)) << 32);
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i_set = i40e_get_rss_hash_bits(nfc, i_setc);
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i40e_write_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, flow_pctype),
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(u32)i_set);
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i40e_write_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, flow_pctype),
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(u32)(i_set >> 32));
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hena |= BIT_ULL(flow_pctype);
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}
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i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (u32)hena);
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i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
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i40e_flush(hw);
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/* Save setting for future output/update */
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pf->vsi[pf->lan_vsi]->rxnfc = *nfc;
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return 0;
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}
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