Merge branch 'linux-4.2' of git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-fixes
Various minor fixes all over the place, nothing too scary. * 'linux-4.2' of git://anongit.freedesktop.org/git/nouveau/linux-2.6: drm/nouveau/fbcon/g80: reduce PUSH_SPACE alloc, fire ring on accel init drm/nouveau/fbcon/gf100-: reduce RING_SPACE allocation drm/nouveau/fbcon/nv11-: correctly account for ring space usage drm/nouveau/bios: add proper support for opcode 0x59 drm/nouveau/bios: add 0x59 and 0x5a opcodes drm/nouveau/disp: Use NULL for pointers drm/nouveau/pm: fix a potential race condition when creating an engine context drm/nouveau/pm: prevent freeing the wrong engine context drm/nouveau/gr/gf100: wait for GR idle after GO_IDLE bundle drm/nouveau/gr/gf100: wait on bottom half of FE's pipeline drm/nouveau/fifo/gk104: kick channels when deactivating them drm/nouveau/ibus/gk20a: increase SM wait timeout drm/nouveau/platform: fix compile error if !CONFIG_IOMMU drm/nouveau: Do not leak client objects drm/nouveau/clk/gt215: u32->s32 for difference in req. and set clock drm/nouveau/drm/nv04-nv40/instmem: protect access to priv->heap by mutex drm/nouveau: hold mutex when calling nouveau_abi16_fini()
This commit is contained in:
Dave Airlie
Коммит
eb8bb7774e
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@ -128,6 +128,7 @@ nouveau_cli_destroy(struct nouveau_cli *cli)
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nvkm_vm_ref(NULL, &nvxx_client(&cli->base)->vm, NULL);
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nvif_client_fini(&cli->base);
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usif_client_fini(cli);
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kfree(cli);
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}
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static void
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@ -865,8 +866,10 @@ nouveau_drm_preclose(struct drm_device *dev, struct drm_file *fpriv)
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pm_runtime_get_sync(dev->dev);
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mutex_lock(&cli->mutex);
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if (cli->abi16)
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nouveau_abi16_fini(cli->abi16);
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mutex_unlock(&cli->mutex);
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mutex_lock(&drm->client.mutex);
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list_del(&cli->head);
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@ -92,6 +92,8 @@ static int nouveau_platform_power_down(struct nouveau_platform_gpu *gpu)
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return 0;
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}
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#if IS_ENABLED(CONFIG_IOMMU_API)
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static void nouveau_platform_probe_iommu(struct device *dev,
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struct nouveau_platform_gpu *gpu)
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{
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@ -158,6 +160,20 @@ static void nouveau_platform_remove_iommu(struct device *dev,
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}
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}
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#else
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static void nouveau_platform_probe_iommu(struct device *dev,
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struct nouveau_platform_gpu *gpu)
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{
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}
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static void nouveau_platform_remove_iommu(struct device *dev,
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struct nouveau_platform_gpu *gpu)
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{
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}
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#endif
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static int nouveau_platform_probe(struct platform_device *pdev)
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{
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struct nouveau_platform_gpu *gpu;
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@ -203,7 +203,7 @@ nv04_fbcon_accel_init(struct fb_info *info)
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if (ret)
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return ret;
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if (RING_SPACE(chan, 49)) {
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if (RING_SPACE(chan, 49 + (device->info.chipset >= 0x11 ? 4 : 0))) {
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nouveau_fbcon_gpu_lockup(info);
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return 0;
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}
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@ -188,7 +188,7 @@ nv50_fbcon_accel_init(struct fb_info *info)
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if (ret)
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return ret;
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ret = RING_SPACE(chan, 59);
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ret = RING_SPACE(chan, 58);
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if (ret) {
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nouveau_fbcon_gpu_lockup(info);
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return ret;
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@ -252,6 +252,7 @@ nv50_fbcon_accel_init(struct fb_info *info)
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OUT_RING(chan, info->var.yres_virtual);
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OUT_RING(chan, upper_32_bits(fb->vma.offset));
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OUT_RING(chan, lower_32_bits(fb->vma.offset));
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FIRE_RING(chan);
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return 0;
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}
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@ -188,7 +188,7 @@ nvc0_fbcon_accel_init(struct fb_info *info)
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return -EINVAL;
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}
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ret = RING_SPACE(chan, 60);
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ret = RING_SPACE(chan, 58);
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if (ret) {
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WARN_ON(1);
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nouveau_fbcon_gpu_lockup(info);
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@ -809,7 +809,7 @@ exec_lookup(struct nv50_disp_priv *priv, int head, int or, u32 ctrl,
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case 0x00000900: type = DCB_OUTPUT_DP; mask = 2; break;
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default:
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nv_error(priv, "unknown SOR mc 0x%08x\n", ctrl);
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return 0x0000;
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return NULL;
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}
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}
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@ -165,15 +165,31 @@ gk104_fifo_context_attach(struct nvkm_object *parent,
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return 0;
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}
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static int
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gk104_fifo_chan_kick(struct gk104_fifo_chan *chan)
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{
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struct nvkm_object *obj = (void *)chan;
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struct gk104_fifo_priv *priv = (void *)obj->engine;
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nv_wr32(priv, 0x002634, chan->base.chid);
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if (!nv_wait(priv, 0x002634, 0x100000, 0x000000)) {
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nv_error(priv, "channel %d [%s] kick timeout\n",
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chan->base.chid, nvkm_client_name(chan));
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return -EBUSY;
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}
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return 0;
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}
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static int
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gk104_fifo_context_detach(struct nvkm_object *parent, bool suspend,
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struct nvkm_object *object)
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{
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struct nvkm_bar *bar = nvkm_bar(parent);
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struct gk104_fifo_priv *priv = (void *)parent->engine;
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struct gk104_fifo_base *base = (void *)parent->parent;
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struct gk104_fifo_chan *chan = (void *)parent;
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u32 addr;
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int ret;
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switch (nv_engidx(object->engine)) {
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case NVDEV_ENGINE_SW : return 0;
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@ -188,13 +204,9 @@ gk104_fifo_context_detach(struct nvkm_object *parent, bool suspend,
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return -EINVAL;
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}
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nv_wr32(priv, 0x002634, chan->base.chid);
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if (!nv_wait(priv, 0x002634, 0xffffffff, chan->base.chid)) {
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nv_error(priv, "channel %d [%s] kick timeout\n",
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chan->base.chid, nvkm_client_name(chan));
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if (suspend)
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return -EBUSY;
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}
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ret = gk104_fifo_chan_kick(chan);
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if (ret && suspend)
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return ret;
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if (addr) {
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nv_wo32(base, addr + 0x00, 0x00000000);
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@ -319,6 +331,7 @@ gk104_fifo_chan_fini(struct nvkm_object *object, bool suspend)
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gk104_fifo_runlist_update(priv, chan->engine);
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}
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gk104_fifo_chan_kick(chan);
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nv_wr32(priv, 0x800000 + (chid * 8), 0x00000000);
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return nvkm_fifo_channel_fini(&chan->base, suspend);
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}
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@ -663,6 +663,37 @@ gf100_gr_zbc_init(struct gf100_gr_priv *priv)
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gf100_gr_zbc_clear_depth(priv, index);
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}
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/**
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* Wait until GR goes idle. GR is considered idle if it is disabled by the
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* MC (0x200) register, or GR is not busy and a context switch is not in
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* progress.
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*/
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int
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gf100_gr_wait_idle(struct gf100_gr_priv *priv)
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{
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unsigned long end_jiffies = jiffies + msecs_to_jiffies(2000);
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bool gr_enabled, ctxsw_active, gr_busy;
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do {
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/*
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* required to make sure FIFO_ENGINE_STATUS (0x2640) is
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* up-to-date
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*/
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nv_rd32(priv, 0x400700);
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gr_enabled = nv_rd32(priv, 0x200) & 0x1000;
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ctxsw_active = nv_rd32(priv, 0x2640) & 0x8000;
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gr_busy = nv_rd32(priv, 0x40060c) & 0x1;
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if (!gr_enabled || (!gr_busy && !ctxsw_active))
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return 0;
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} while (time_before(jiffies, end_jiffies));
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nv_error(priv, "wait for idle timeout (en: %d, ctxsw: %d, busy: %d)\n",
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gr_enabled, ctxsw_active, gr_busy);
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return -EAGAIN;
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}
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void
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gf100_gr_mmio(struct gf100_gr_priv *priv, const struct gf100_gr_pack *p)
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{
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@ -699,7 +730,13 @@ gf100_gr_icmd(struct gf100_gr_priv *priv, const struct gf100_gr_pack *p)
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while (addr < next) {
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nv_wr32(priv, 0x400200, addr);
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nv_wait(priv, 0x400700, 0x00000002, 0x00000000);
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/**
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* Wait for GR to go idle after submitting a
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* GO_IDLE bundle
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*/
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if ((addr & 0xffff) == 0xe100)
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gf100_gr_wait_idle(priv);
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nv_wait(priv, 0x400700, 0x00000004, 0x00000000);
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addr += init->pitch;
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}
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}
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@ -181,6 +181,7 @@ struct gf100_gr_oclass {
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int ppc_nr;
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};
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int gf100_gr_wait_idle(struct gf100_gr_priv *);
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void gf100_gr_mmio(struct gf100_gr_priv *, const struct gf100_gr_pack *);
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void gf100_gr_icmd(struct gf100_gr_priv *, const struct gf100_gr_pack *);
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void gf100_gr_mthd(struct gf100_gr_priv *, const struct gf100_gr_pack *);
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@ -332,9 +332,12 @@ static void
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nvkm_perfctx_dtor(struct nvkm_object *object)
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{
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struct nvkm_pm *ppm = (void *)object->engine;
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struct nvkm_perfctx *ctx = (void *)object;
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mutex_lock(&nv_subdev(ppm)->mutex);
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nvkm_engctx_destroy(&ppm->context->base);
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ppm->context = NULL;
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nvkm_engctx_destroy(&ctx->base);
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if (ppm->context == ctx)
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ppm->context = NULL;
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mutex_unlock(&nv_subdev(ppm)->mutex);
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}
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@ -355,12 +358,11 @@ nvkm_perfctx_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
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mutex_lock(&nv_subdev(ppm)->mutex);
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if (ppm->context == NULL)
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ppm->context = ctx;
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if (ctx != ppm->context)
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ret = -EBUSY;
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mutex_unlock(&nv_subdev(ppm)->mutex);
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if (ctx != ppm->context)
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return -EBUSY;
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return 0;
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return ret;
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}
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struct nvkm_oclass
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@ -1284,6 +1284,44 @@ init_zm_reg_sequence(struct nvbios_init *init)
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}
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}
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/**
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* INIT_PLL_INDIRECT - opcode 0x59
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*
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*/
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static void
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init_pll_indirect(struct nvbios_init *init)
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{
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struct nvkm_bios *bios = init->bios;
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u32 reg = nv_ro32(bios, init->offset + 1);
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u16 addr = nv_ro16(bios, init->offset + 5);
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u32 freq = (u32)nv_ro16(bios, addr) * 1000;
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trace("PLL_INDIRECT\tR[0x%06x] =PLL= VBIOS[%04x] = %dkHz\n",
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reg, addr, freq);
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init->offset += 7;
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init_prog_pll(init, reg, freq);
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}
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/**
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* INIT_ZM_REG_INDIRECT - opcode 0x5a
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*
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*/
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static void
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init_zm_reg_indirect(struct nvbios_init *init)
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{
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struct nvkm_bios *bios = init->bios;
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u32 reg = nv_ro32(bios, init->offset + 1);
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u16 addr = nv_ro16(bios, init->offset + 5);
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u32 data = nv_ro32(bios, addr);
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trace("ZM_REG_INDIRECT\tR[0x%06x] = VBIOS[0x%04x] = 0x%08x\n",
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reg, addr, data);
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init->offset += 7;
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init_wr32(init, addr, data);
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}
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/**
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* INIT_SUB_DIRECT - opcode 0x5b
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*
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@ -2145,6 +2183,8 @@ static struct nvbios_init_opcode {
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[0x56] = { init_condition_time },
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[0x57] = { init_ltime },
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[0x58] = { init_zm_reg_sequence },
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[0x59] = { init_pll_indirect },
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[0x5a] = { init_zm_reg_indirect },
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[0x5b] = { init_sub_direct },
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[0x5c] = { init_jump },
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[0x5e] = { init_i2c_if },
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@ -180,7 +180,8 @@ gt215_clk_info(struct nvkm_clk *clock, int clk, u32 khz,
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struct gt215_clk_info *info)
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{
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struct gt215_clk_priv *priv = (void *)clock;
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u32 oclk, sclk, sdiv, diff;
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u32 oclk, sclk, sdiv;
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s32 diff;
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info->clk = 0;
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@ -38,6 +38,14 @@ gk20a_ibus_init_priv_ring(struct gk20a_ibus_priv *priv)
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nv_wr32(priv, 0x12004c, 0x4);
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nv_wr32(priv, 0x122204, 0x2);
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nv_rd32(priv, 0x122204);
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/*
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* Bug: increase clock timeout to avoid operation failure at high
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* gpcclk rate.
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*/
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nv_wr32(priv, 0x122354, 0x800);
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nv_wr32(priv, 0x128328, 0x800);
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nv_wr32(priv, 0x124320, 0x800);
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}
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static void
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@ -50,7 +50,12 @@ nv04_instobj_dtor(struct nvkm_object *object)
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{
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struct nv04_instmem_priv *priv = (void *)nvkm_instmem(object);
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struct nv04_instobj_priv *node = (void *)object;
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struct nvkm_subdev *subdev = (void *)priv;
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mutex_lock(&subdev->mutex);
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nvkm_mm_free(&priv->heap, &node->mem);
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mutex_unlock(&subdev->mutex);
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nvkm_instobj_destroy(&node->base);
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}
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@ -62,6 +67,7 @@ nv04_instobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
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struct nv04_instmem_priv *priv = (void *)nvkm_instmem(parent);
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struct nv04_instobj_priv *node;
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struct nvkm_instobj_args *args = data;
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struct nvkm_subdev *subdev = (void *)priv;
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int ret;
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if (!args->align)
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@ -72,8 +78,10 @@ nv04_instobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
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if (ret)
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return ret;
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|
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mutex_lock(&subdev->mutex);
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ret = nvkm_mm_head(&priv->heap, 0, 1, args->size, args->size,
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args->align, &node->mem);
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mutex_unlock(&subdev->mutex);
|
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if (ret)
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return ret;
|
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