soc: mediatek: pm-domains: Add support for mt8183
Add the needed board data to support mt8183 SoC. Signed-off-by: Matthias Brugger <mbrugger@suse.com> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Link: https://lore.kernel.org/r/20201030113622.201188-12-enric.balletbo@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This commit is contained in:
Matthias Brugger
Matthias Brugger
Родитель
1d4597fa18
Коммит
eb9fa767fb
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@ -0,0 +1,221 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __SOC_MEDIATEK_MT8183_PM_DOMAINS_H
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#define __SOC_MEDIATEK_MT8183_PM_DOMAINS_H
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#include "mtk-pm-domains.h"
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#include <dt-bindings/power/mt8183-power.h>
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/*
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* MT8183 power domain support
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*/
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static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
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[MT8183_POWER_DOMAIN_AUDIO] = {
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.sta_mask = PWR_STATUS_AUDIO,
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.ctl_offs = 0x0314,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = GENMASK(15, 12),
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},
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[MT8183_POWER_DOMAIN_CONN] = {
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.sta_mask = PWR_STATUS_CONN,
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.ctl_offs = 0x032c,
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.sram_pdn_bits = 0,
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.sram_pdn_ack_bits = 0,
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.bp_infracfg = {
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BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_CONN, MT8183_TOP_AXI_PROT_EN_SET,
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MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1),
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},
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},
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[MT8183_POWER_DOMAIN_MFG_ASYNC] = {
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.sta_mask = PWR_STATUS_MFG_ASYNC,
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.ctl_offs = 0x0334,
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.sram_pdn_bits = 0,
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.sram_pdn_ack_bits = 0,
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},
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[MT8183_POWER_DOMAIN_MFG] = {
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.sta_mask = PWR_STATUS_MFG,
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.ctl_offs = 0x0338,
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.sram_pdn_bits = GENMASK(8, 8),
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.sram_pdn_ack_bits = GENMASK(12, 12),
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},
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[MT8183_POWER_DOMAIN_MFG_CORE0] = {
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.sta_mask = BIT(7),
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.ctl_offs = 0x034c,
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.sram_pdn_bits = GENMASK(8, 8),
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.sram_pdn_ack_bits = GENMASK(12, 12),
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},
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[MT8183_POWER_DOMAIN_MFG_CORE1] = {
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.sta_mask = BIT(20),
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.ctl_offs = 0x0310,
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.sram_pdn_bits = GENMASK(8, 8),
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.sram_pdn_ack_bits = GENMASK(12, 12),
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},
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[MT8183_POWER_DOMAIN_MFG_2D] = {
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.sta_mask = PWR_STATUS_MFG_2D,
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.ctl_offs = 0x0348,
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.sram_pdn_bits = GENMASK(8, 8),
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.sram_pdn_ack_bits = GENMASK(12, 12),
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.bp_infracfg = {
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BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_1_MFG, MT8183_TOP_AXI_PROT_EN_1_SET,
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MT8183_TOP_AXI_PROT_EN_1_CLR, MT8183_TOP_AXI_PROT_EN_STA1_1),
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BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MFG, MT8183_TOP_AXI_PROT_EN_SET,
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MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1),
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},
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},
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[MT8183_POWER_DOMAIN_DISP] = {
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.sta_mask = PWR_STATUS_DISP,
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.ctl_offs = 0x030c,
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.sram_pdn_bits = GENMASK(8, 8),
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.sram_pdn_ack_bits = GENMASK(12, 12),
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.bp_infracfg = {
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BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_1_DISP, MT8183_TOP_AXI_PROT_EN_1_SET,
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MT8183_TOP_AXI_PROT_EN_1_CLR, MT8183_TOP_AXI_PROT_EN_STA1_1),
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BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_DISP, MT8183_TOP_AXI_PROT_EN_SET,
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MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1),
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},
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.bp_smi = {
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BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_DISP,
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MT8183_SMI_COMMON_CLAMP_EN_SET,
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MT8183_SMI_COMMON_CLAMP_EN_CLR,
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MT8183_SMI_COMMON_CLAMP_EN),
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},
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},
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[MT8183_POWER_DOMAIN_CAM] = {
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.sta_mask = BIT(25),
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.ctl_offs = 0x0344,
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.sram_pdn_bits = GENMASK(9, 8),
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.sram_pdn_ack_bits = GENMASK(13, 12),
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.bp_infracfg = {
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BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_CAM, MT8183_TOP_AXI_PROT_EN_MM_SET,
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MT8183_TOP_AXI_PROT_EN_MM_CLR, MT8183_TOP_AXI_PROT_EN_MM_STA1),
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BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_CAM, MT8183_TOP_AXI_PROT_EN_SET,
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MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1),
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BUS_PROT_WR_IGN(MT8183_TOP_AXI_PROT_EN_MM_CAM_2ND,
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MT8183_TOP_AXI_PROT_EN_MM_SET,
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MT8183_TOP_AXI_PROT_EN_MM_CLR,
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MT8183_TOP_AXI_PROT_EN_MM_STA1),
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},
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.bp_smi = {
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BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_CAM,
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MT8183_SMI_COMMON_CLAMP_EN_SET,
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MT8183_SMI_COMMON_CLAMP_EN_CLR,
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MT8183_SMI_COMMON_CLAMP_EN),
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},
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},
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[MT8183_POWER_DOMAIN_ISP] = {
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.sta_mask = PWR_STATUS_ISP,
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.ctl_offs = 0x0308,
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.sram_pdn_bits = GENMASK(9, 8),
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.sram_pdn_ack_bits = GENMASK(13, 12),
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.bp_infracfg = {
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BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_ISP,
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MT8183_TOP_AXI_PROT_EN_MM_SET,
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MT8183_TOP_AXI_PROT_EN_MM_CLR,
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MT8183_TOP_AXI_PROT_EN_MM_STA1),
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BUS_PROT_WR_IGN(MT8183_TOP_AXI_PROT_EN_MM_ISP_2ND,
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MT8183_TOP_AXI_PROT_EN_MM_SET,
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MT8183_TOP_AXI_PROT_EN_MM_CLR,
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MT8183_TOP_AXI_PROT_EN_MM_STA1),
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},
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.bp_smi = {
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BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_ISP,
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MT8183_SMI_COMMON_CLAMP_EN_SET,
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MT8183_SMI_COMMON_CLAMP_EN_CLR,
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MT8183_SMI_COMMON_CLAMP_EN),
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},
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},
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[MT8183_POWER_DOMAIN_VDEC] = {
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.sta_mask = BIT(31),
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.ctl_offs = 0x0300,
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.sram_pdn_bits = GENMASK(8, 8),
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.sram_pdn_ack_bits = GENMASK(12, 12),
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.bp_smi = {
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BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_VDEC,
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MT8183_SMI_COMMON_CLAMP_EN_SET,
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MT8183_SMI_COMMON_CLAMP_EN_CLR,
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MT8183_SMI_COMMON_CLAMP_EN),
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},
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},
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[MT8183_POWER_DOMAIN_VENC] = {
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.sta_mask = PWR_STATUS_VENC,
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.ctl_offs = 0x0304,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = GENMASK(15, 12),
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.bp_smi = {
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BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_VENC,
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MT8183_SMI_COMMON_CLAMP_EN_SET,
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MT8183_SMI_COMMON_CLAMP_EN_CLR,
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MT8183_SMI_COMMON_CLAMP_EN),
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},
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},
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[MT8183_POWER_DOMAIN_VPU_TOP] = {
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.sta_mask = BIT(26),
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.ctl_offs = 0x0324,
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.sram_pdn_bits = GENMASK(8, 8),
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.sram_pdn_ack_bits = GENMASK(12, 12),
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.bp_infracfg = {
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BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP,
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MT8183_TOP_AXI_PROT_EN_MM_SET,
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MT8183_TOP_AXI_PROT_EN_MM_CLR,
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MT8183_TOP_AXI_PROT_EN_MM_STA1),
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BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_VPU_TOP,
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MT8183_TOP_AXI_PROT_EN_SET,
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MT8183_TOP_AXI_PROT_EN_CLR,
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MT8183_TOP_AXI_PROT_EN_STA1),
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BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP_2ND,
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MT8183_TOP_AXI_PROT_EN_MM_SET,
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MT8183_TOP_AXI_PROT_EN_MM_CLR,
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MT8183_TOP_AXI_PROT_EN_MM_STA1),
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},
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.bp_smi = {
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BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_VPU_TOP,
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MT8183_SMI_COMMON_CLAMP_EN_SET,
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MT8183_SMI_COMMON_CLAMP_EN_CLR,
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MT8183_SMI_COMMON_CLAMP_EN),
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},
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},
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[MT8183_POWER_DOMAIN_VPU_CORE0] = {
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.sta_mask = BIT(27),
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.ctl_offs = 0x33c,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = GENMASK(13, 12),
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.bp_infracfg = {
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BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0,
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MT8183_TOP_AXI_PROT_EN_MCU_SET,
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MT8183_TOP_AXI_PROT_EN_MCU_CLR,
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MT8183_TOP_AXI_PROT_EN_MCU_STA1),
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BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0_2ND,
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MT8183_TOP_AXI_PROT_EN_MCU_SET,
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MT8183_TOP_AXI_PROT_EN_MCU_CLR,
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MT8183_TOP_AXI_PROT_EN_MCU_STA1),
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},
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.caps = MTK_SCPD_SRAM_ISO,
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},
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[MT8183_POWER_DOMAIN_VPU_CORE1] = {
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.sta_mask = BIT(28),
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.ctl_offs = 0x0340,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = GENMASK(13, 12),
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.bp_infracfg = {
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BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1,
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MT8183_TOP_AXI_PROT_EN_MCU_SET,
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MT8183_TOP_AXI_PROT_EN_MCU_CLR,
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MT8183_TOP_AXI_PROT_EN_MCU_STA1),
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BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1_2ND,
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MT8183_TOP_AXI_PROT_EN_MCU_SET,
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MT8183_TOP_AXI_PROT_EN_MCU_CLR,
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MT8183_TOP_AXI_PROT_EN_MCU_STA1),
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},
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.caps = MTK_SCPD_SRAM_ISO,
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},
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};
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static const struct scpsys_soc_data mt8183_scpsys_data = {
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.domains_data = scpsys_domain_data_mt8183,
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.num_domains = ARRAY_SIZE(scpsys_domain_data_mt8183),
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.pwr_sta_offs = 0x0180,
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.pwr_sta2nd_offs = 0x0184
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};
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#endif /* __SOC_MEDIATEK_MT8183_PM_DOMAINS_H */
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@ -16,6 +16,7 @@
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#include <linux/soc/mediatek/infracfg.h>
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#include "mt8173-pm-domains.h"
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#include "mt8183-pm-domains.h"
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#define MTK_POLL_DELAY_US 10
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#define MTK_POLL_TIMEOUT USEC_PER_SEC
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@ -505,6 +506,10 @@ static const struct of_device_id scpsys_of_match[] = {
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.compatible = "mediatek,mt8173-power-controller",
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.data = &mt8173_scpsys_data,
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},
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{
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.compatible = "mediatek,mt8183-power-controller",
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.data = &mt8183_scpsys_data,
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},
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{ }
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};
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@ -22,6 +22,7 @@
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#define SPM_PWR_STATUS 0x060c
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#define SPM_PWR_STATUS_2ND 0x0610
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#define PWR_STATUS_CONN BIT(1)
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#define PWR_STATUS_DISP BIT(3)
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#define PWR_STATUS_MFG BIT(4)
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#define PWR_STATUS_ISP BIT(5)
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@ -2,6 +2,52 @@
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#ifndef __SOC_MEDIATEK_INFRACFG_H
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#define __SOC_MEDIATEK_INFRACFG_H
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#define MT8183_TOP_AXI_PROT_EN_STA1 0x228
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#define MT8183_TOP_AXI_PROT_EN_STA1_1 0x258
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#define MT8183_TOP_AXI_PROT_EN_SET 0x2a0
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#define MT8183_TOP_AXI_PROT_EN_CLR 0x2a4
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#define MT8183_TOP_AXI_PROT_EN_1_SET 0x2a8
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#define MT8183_TOP_AXI_PROT_EN_1_CLR 0x2ac
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#define MT8183_TOP_AXI_PROT_EN_MCU_SET 0x2c4
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#define MT8183_TOP_AXI_PROT_EN_MCU_CLR 0x2c8
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#define MT8183_TOP_AXI_PROT_EN_MCU_STA1 0x2e4
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#define MT8183_TOP_AXI_PROT_EN_MM_SET 0x2d4
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#define MT8183_TOP_AXI_PROT_EN_MM_CLR 0x2d8
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#define MT8183_TOP_AXI_PROT_EN_MM_STA1 0x2ec
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#define MT8183_TOP_AXI_PROT_EN_DISP (BIT(10) | BIT(11))
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#define MT8183_TOP_AXI_PROT_EN_CONN (BIT(13) | BIT(14))
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#define MT8183_TOP_AXI_PROT_EN_MFG (BIT(21) | BIT(22))
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#define MT8183_TOP_AXI_PROT_EN_CAM BIT(28)
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#define MT8183_TOP_AXI_PROT_EN_VPU_TOP BIT(27)
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#define MT8183_TOP_AXI_PROT_EN_1_DISP (BIT(16) | BIT(17))
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#define MT8183_TOP_AXI_PROT_EN_1_MFG GENMASK(21, 19)
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#define MT8183_TOP_AXI_PROT_EN_MM_ISP (BIT(3) | BIT(8))
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#define MT8183_TOP_AXI_PROT_EN_MM_ISP_2ND BIT(10)
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#define MT8183_TOP_AXI_PROT_EN_MM_CAM (BIT(4) | BIT(5) | \
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BIT(9) | BIT(13))
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#define MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP (GENMASK(9, 6) | \
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BIT(12))
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#define MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP_2ND (BIT(10) | BIT(11))
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#define MT8183_TOP_AXI_PROT_EN_MM_CAM_2ND BIT(11)
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#define MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0_2ND (BIT(0) | BIT(2) | \
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BIT(4))
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#define MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1_2ND (BIT(1) | BIT(3) | \
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BIT(5))
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#define MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0 BIT(6)
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#define MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1 BIT(7)
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#define MT8183_SMI_COMMON_CLAMP_EN 0x3c0
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#define MT8183_SMI_COMMON_CLAMP_EN_SET 0x3c4
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#define MT8183_SMI_COMMON_CLAMP_EN_CLR 0x3c8
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#define MT8183_SMI_COMMON_SMI_CLAMP_DISP GENMASK(7, 0)
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#define MT8183_SMI_COMMON_SMI_CLAMP_VENC BIT(1)
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#define MT8183_SMI_COMMON_SMI_CLAMP_ISP BIT(2)
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#define MT8183_SMI_COMMON_SMI_CLAMP_CAM (BIT(3) | BIT(4))
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#define MT8183_SMI_COMMON_SMI_CLAMP_VPU_TOP (BIT(5) | BIT(6))
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#define MT8183_SMI_COMMON_SMI_CLAMP_VDEC BIT(7)
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#define MT8173_TOP_AXI_PROT_EN_MCI_M2 BIT(0)
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#define MT8173_TOP_AXI_PROT_EN_MM_M0 BIT(1)
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#define MT8173_TOP_AXI_PROT_EN_MM_M1 BIT(2)
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