Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc
* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (180 commits) powerpc: clean up ssi.txt, add definition for fsl,ssi-asynchronous powerpc/85xx: Add support for the "socrates" board (MPC8544). powerpc: Fix bugs introduced by sysfs changes powerpc: Sanitize stack pointer in signal handling code powerpc: Add write barrier before enabling DTL flags powerpc/83xx: Update ranges in gianfar node to match other dts powerpc/86xx: Move gianfar mdio nodes under the ethernet nodes powerpc/85xx: Move gianfar mdio nodes under the ethernet nodes powerpc/83xx: Move gianfar mdio nodes under the ethernet nodes powerpc/83xx: Add power management support for MPC837x boards powerpc/mm: Introduce early_init_mmu() on 64-bit powerpc/mm: Add option for non-atomic PTE updates to ppc64 powerpc/mm: Fix printk type warning in mmu_context_nohash powerpc/mm: Rename arch/powerpc/kernel/mmap.c to mmap_64.c powerpc/mm: Merge various PTE bits and accessors definitions powerpc/mm: Tweak PTE bit combination definitions powerpc/cell: Fix iommu exception reporting powerpc/mm: e300c2/c3/c4 TLB errata workaround powerpc/mm: Used free register to save a few cycles in SW TLB miss handling powerpc/mm: Remove unused register usage in SW TLB miss handling ...
This commit is contained in:
Linus Torvalds
Коммит
ebc8eca169
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|
@ -35,30 +35,30 @@ Example:
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#address-cells = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
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compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
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reg = <82a8 4>;
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reg = <0x82a8 4>;
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ranges = <0 8100 1a4>;
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ranges = <0 0x8100 0x1a4>;
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interrupt-parent = <&ipic>;
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interrupt-parent = <&ipic>;
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interrupts = <47 8>;
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interrupts = <71 8>;
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cell-index = <0>;
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cell-index = <0>;
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dma-channel@0 {
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dma-channel@0 {
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compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
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compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
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cell-index = <0>;
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cell-index = <0>;
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reg = <0 80>;
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reg = <0 0x80>;
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};
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};
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dma-channel@80 {
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dma-channel@80 {
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compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
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compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
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cell-index = <1>;
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cell-index = <1>;
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reg = <80 80>;
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reg = <0x80 0x80>;
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};
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};
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dma-channel@100 {
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dma-channel@100 {
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compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
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compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
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cell-index = <2>;
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cell-index = <2>;
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reg = <100 80>;
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reg = <0x100 0x80>;
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};
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};
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dma-channel@180 {
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dma-channel@180 {
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compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
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compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
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cell-index = <3>;
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cell-index = <3>;
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reg = <180 80>;
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reg = <0x180 0x80>;
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};
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};
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};
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};
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@ -93,36 +93,36 @@ Example:
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#address-cells = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
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compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
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reg = <21300 4>;
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reg = <0x21300 4>;
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ranges = <0 21100 200>;
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ranges = <0 0x21100 0x200>;
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cell-index = <0>;
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cell-index = <0>;
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dma-channel@0 {
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dma-channel@0 {
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compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
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compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
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reg = <0 80>;
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reg = <0 0x80>;
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cell-index = <0>;
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cell-index = <0>;
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interrupt-parent = <&mpic>;
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interrupt-parent = <&mpic>;
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interrupts = <14 2>;
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interrupts = <20 2>;
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||||||
};
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};
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dma-channel@80 {
|
dma-channel@80 {
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compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
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compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
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reg = <80 80>;
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reg = <0x80 0x80>;
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cell-index = <1>;
|
cell-index = <1>;
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interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
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||||||
interrupts = <15 2>;
|
interrupts = <21 2>;
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||||||
};
|
};
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dma-channel@100 {
|
dma-channel@100 {
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compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
|
compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
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reg = <100 80>;
|
reg = <0x100 0x80>;
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cell-index = <2>;
|
cell-index = <2>;
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||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
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||||||
interrupts = <16 2>;
|
interrupts = <22 2>;
|
||||||
};
|
};
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dma-channel@180 {
|
dma-channel@180 {
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||||||
compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
|
compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
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||||||
reg = <180 80>;
|
reg = <0x180 0x80>;
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||||||
cell-index = <3>;
|
cell-index = <3>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
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interrupts = <17 2>;
|
interrupts = <23 2>;
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||||||
};
|
};
|
||||||
};
|
};
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|
|
||||||
|
|
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|
|
@ -0,0 +1,24 @@
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|
* Freescale Enhanced Secure Digital Host Controller (eSDHC)
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|
|
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|
The Enhanced Secure Digital Host Controller provides an interface
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|
for MMC, SD, and SDIO types of memory cards.
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|
|
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|
Required properties:
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|
- compatible : should be
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|
"fsl,<chip>-esdhc", "fsl,mpc8379-esdhc" for MPC83xx processors.
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|
"fsl,<chip>-esdhc", "fsl,mpc8536-esdhc" for MPC85xx processors.
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|
- reg : should contain eSDHC registers location and length.
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||||||
|
- interrupts : should contain eSDHC interrupt.
|
||||||
|
- interrupt-parent : interrupt source phandle.
|
||||||
|
- clock-frequency : specifies eSDHC base clock frequency.
|
||||||
|
|
||||||
|
Example:
|
||||||
|
|
||||||
|
sdhci@2e000 {
|
||||||
|
compatible = "fsl,mpc8378-esdhc", "fsl,mpc8379-esdhc";
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|
reg = <0x2e000 0x1000>;
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||||||
|
interrupts = <42 0x8>;
|
||||||
|
interrupt-parent = <&ipic>;
|
||||||
|
/* Filled in by U-Boot */
|
||||||
|
clock-frequency = <0>;
|
||||||
|
};
|
||||||
|
|
@ -4,44 +4,56 @@ The SSI is a serial device that communicates with audio codecs. It can
|
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be programmed in AC97, I2S, left-justified, or right-justified modes.
|
be programmed in AC97, I2S, left-justified, or right-justified modes.
|
||||||
|
|
||||||
Required properties:
|
Required properties:
|
||||||
- compatible : compatible list, containing "fsl,ssi"
|
- compatible: Compatible list, contains "fsl,ssi".
|
||||||
- cell-index : the SSI, <0> = SSI1, <1> = SSI2, and so on
|
- cell-index: The SSI, <0> = SSI1, <1> = SSI2, and so on.
|
||||||
- reg : offset and length of the register set for the device
|
- reg: Offset and length of the register set for the device.
|
||||||
- interrupts : <a b> where a is the interrupt number and b is a
|
- interrupts: <a b> where a is the interrupt number and b is a
|
||||||
field that represents an encoding of the sense and
|
field that represents an encoding of the sense and
|
||||||
level information for the interrupt. This should be
|
level information for the interrupt. This should be
|
||||||
encoded based on the information in section 2)
|
encoded based on the information in section 2)
|
||||||
depending on the type of interrupt controller you
|
depending on the type of interrupt controller you
|
||||||
have.
|
have.
|
||||||
- interrupt-parent : the phandle for the interrupt controller that
|
- interrupt-parent: The phandle for the interrupt controller that
|
||||||
services interrupts for this device.
|
services interrupts for this device.
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||||||
- fsl,mode : the operating mode for the SSI interface
|
- fsl,mode: The operating mode for the SSI interface.
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||||||
"i2s-slave" - I2S mode, SSI is clock slave
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"i2s-slave" - I2S mode, SSI is clock slave
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||||||
"i2s-master" - I2S mode, SSI is clock master
|
"i2s-master" - I2S mode, SSI is clock master
|
||||||
"lj-slave" - left-justified mode, SSI is clock slave
|
"lj-slave" - left-justified mode, SSI is clock slave
|
||||||
"lj-master" - l.j. mode, SSI is clock master
|
"lj-master" - l.j. mode, SSI is clock master
|
||||||
"rj-slave" - right-justified mode, SSI is clock slave
|
"rj-slave" - right-justified mode, SSI is clock slave
|
||||||
"rj-master" - r.j., SSI is clock master
|
"rj-master" - r.j., SSI is clock master
|
||||||
"ac97-slave" - AC97 mode, SSI is clock slave
|
"ac97-slave" - AC97 mode, SSI is clock slave
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||||||
"ac97-master" - AC97 mode, SSI is clock master
|
"ac97-master" - AC97 mode, SSI is clock master
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||||||
- fsl,playback-dma: phandle to a node for the DMA channel to use for
|
- fsl,playback-dma: Phandle to a node for the DMA channel to use for
|
||||||
playback of audio. This is typically dictated by SOC
|
playback of audio. This is typically dictated by SOC
|
||||||
design. See the notes below.
|
design. See the notes below.
|
||||||
- fsl,capture-dma: phandle to a node for the DMA channel to use for
|
- fsl,capture-dma: Phandle to a node for the DMA channel to use for
|
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capture (recording) of audio. This is typically dictated
|
capture (recording) of audio. This is typically dictated
|
||||||
by SOC design. See the notes below.
|
by SOC design. See the notes below.
|
||||||
|
- fsl,fifo-depth: The number of elements in the transmit and receive FIFOs.
|
||||||
|
This number is the maximum allowed value for SFCSR[TFWM0].
|
||||||
|
- fsl,ssi-asynchronous:
|
||||||
|
If specified, the SSI is to be programmed in asynchronous
|
||||||
|
mode. In this mode, pins SRCK, STCK, SRFS, and STFS must
|
||||||
|
all be connected to valid signals. In synchronous mode,
|
||||||
|
SRCK and SRFS are ignored. Asynchronous mode allows
|
||||||
|
playback and capture to use different sample sizes and
|
||||||
|
sample rates. Some drivers may require that SRCK and STCK
|
||||||
|
be connected together, and SRFS and STFS be connected
|
||||||
|
together. This would still allow different sample sizes,
|
||||||
|
but not different sample rates.
|
||||||
|
|
||||||
Optional properties:
|
Optional properties:
|
||||||
- codec-handle : phandle to a 'codec' node that defines an audio
|
- codec-handle: Phandle to a 'codec' node that defines an audio
|
||||||
codec connected to this SSI. This node is typically
|
codec connected to this SSI. This node is typically
|
||||||
a child of an I2C or other control node.
|
a child of an I2C or other control node.
|
||||||
|
|
||||||
Child 'codec' node required properties:
|
Child 'codec' node required properties:
|
||||||
- compatible : compatible list, contains the name of the codec
|
- compatible: Compatible list, contains the name of the codec
|
||||||
|
|
||||||
Child 'codec' node optional properties:
|
Child 'codec' node optional properties:
|
||||||
- clock-frequency : The frequency of the input clock, which typically
|
- clock-frequency: The frequency of the input clock, which typically comes
|
||||||
comes from an on-board dedicated oscillator.
|
from an on-board dedicated oscillator.
|
||||||
|
|
||||||
Notes on fsl,playback-dma and fsl,capture-dma:
|
Notes on fsl,playback-dma and fsl,capture-dma:
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -111,6 +111,7 @@ config PPC
|
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select HAVE_FTRACE_MCOUNT_RECORD
|
select HAVE_FTRACE_MCOUNT_RECORD
|
||||||
select HAVE_DYNAMIC_FTRACE
|
select HAVE_DYNAMIC_FTRACE
|
||||||
select HAVE_FUNCTION_TRACER
|
select HAVE_FUNCTION_TRACER
|
||||||
|
select HAVE_FUNCTION_GRAPH_TRACER
|
||||||
select ARCH_WANT_OPTIONAL_GPIOLIB
|
select ARCH_WANT_OPTIONAL_GPIOLIB
|
||||||
select HAVE_IDE
|
select HAVE_IDE
|
||||||
select HAVE_IOREMAP_PROT
|
select HAVE_IOREMAP_PROT
|
||||||
|
|
@ -312,7 +313,7 @@ config ARCH_ENABLE_MEMORY_HOTREMOVE
|
||||||
|
|
||||||
config KEXEC
|
config KEXEC
|
||||||
bool "kexec system call (EXPERIMENTAL)"
|
bool "kexec system call (EXPERIMENTAL)"
|
||||||
depends on (PPC_PRPMC2800 || PPC_MULTIPLATFORM) && EXPERIMENTAL
|
depends on BOOK3S && EXPERIMENTAL
|
||||||
help
|
help
|
||||||
kexec is a system call that implements the ability to shutdown your
|
kexec is a system call that implements the ability to shutdown your
|
||||||
current kernel, and to start another kernel. It is like a reboot
|
current kernel, and to start another kernel. It is like a reboot
|
||||||
|
|
@ -409,6 +410,18 @@ config PPC_HAS_HASH_64K
|
||||||
depends on PPC64
|
depends on PPC64
|
||||||
default n
|
default n
|
||||||
|
|
||||||
|
config STDBINUTILS
|
||||||
|
bool "Using standard binutils settings"
|
||||||
|
depends on 44x
|
||||||
|
default y
|
||||||
|
help
|
||||||
|
Turning this option off allows you to select 256KB PAGE_SIZE on 44x.
|
||||||
|
Note, that kernel will be able to run only those applications,
|
||||||
|
which had been compiled using binutils later than 2.17.50.0.3 with
|
||||||
|
'-zmax-page-size' set to 256K (the default is 64K). Or, if using
|
||||||
|
the older binutils, you can patch them with a trivial patch, which
|
||||||
|
changes the ELF_MAXPAGESIZE definition from 0x10000 to 0x40000.
|
||||||
|
|
||||||
choice
|
choice
|
||||||
prompt "Page size"
|
prompt "Page size"
|
||||||
default PPC_4K_PAGES
|
default PPC_4K_PAGES
|
||||||
|
|
@ -444,6 +457,19 @@ config PPC_64K_PAGES
|
||||||
bool "64k page size" if 44x || PPC_STD_MMU_64
|
bool "64k page size" if 44x || PPC_STD_MMU_64
|
||||||
select PPC_HAS_HASH_64K if PPC_STD_MMU_64
|
select PPC_HAS_HASH_64K if PPC_STD_MMU_64
|
||||||
|
|
||||||
|
config PPC_256K_PAGES
|
||||||
|
bool "256k page size" if 44x
|
||||||
|
depends on !STDBINUTILS && (!SHMEM || BROKEN)
|
||||||
|
help
|
||||||
|
Make the page size 256k.
|
||||||
|
|
||||||
|
As the ELF standard only requires alignment to support page
|
||||||
|
sizes up to 64k, you will need to compile all of your user
|
||||||
|
space applications with a non-standard binutils settings
|
||||||
|
(see the STDBINUTILS description for details).
|
||||||
|
|
||||||
|
Say N unless you know what you are doing.
|
||||||
|
|
||||||
endchoice
|
endchoice
|
||||||
|
|
||||||
config FORCE_MAX_ZONEORDER
|
config FORCE_MAX_ZONEORDER
|
||||||
|
|
@ -456,6 +482,8 @@ config FORCE_MAX_ZONEORDER
|
||||||
default "9" if PPC_STD_MMU_32 && PPC_16K_PAGES
|
default "9" if PPC_STD_MMU_32 && PPC_16K_PAGES
|
||||||
range 7 64 if PPC_STD_MMU_32 && PPC_64K_PAGES
|
range 7 64 if PPC_STD_MMU_32 && PPC_64K_PAGES
|
||||||
default "7" if PPC_STD_MMU_32 && PPC_64K_PAGES
|
default "7" if PPC_STD_MMU_32 && PPC_64K_PAGES
|
||||||
|
range 5 64 if PPC_STD_MMU_32 && PPC_256K_PAGES
|
||||||
|
default "5" if PPC_STD_MMU_32 && PPC_256K_PAGES
|
||||||
range 11 64
|
range 11 64
|
||||||
default "11"
|
default "11"
|
||||||
help
|
help
|
||||||
|
|
@ -594,6 +622,7 @@ config FSL_SOC
|
||||||
config FSL_PCI
|
config FSL_PCI
|
||||||
bool
|
bool
|
||||||
select PPC_INDIRECT_PCI
|
select PPC_INDIRECT_PCI
|
||||||
|
select PCI_QUIRKS
|
||||||
|
|
||||||
config 4xx_SOC
|
config 4xx_SOC
|
||||||
bool
|
bool
|
||||||
|
|
@ -730,6 +759,22 @@ config LOWMEM_SIZE
|
||||||
hex "Maximum low memory size (in bytes)" if LOWMEM_SIZE_BOOL
|
hex "Maximum low memory size (in bytes)" if LOWMEM_SIZE_BOOL
|
||||||
default "0x30000000"
|
default "0x30000000"
|
||||||
|
|
||||||
|
config LOWMEM_CAM_NUM_BOOL
|
||||||
|
bool "Set number of CAMs to use to map low memory"
|
||||||
|
depends on ADVANCED_OPTIONS && FSL_BOOKE
|
||||||
|
help
|
||||||
|
This option allows you to set the maximum number of CAM slots that
|
||||||
|
will be used to map low memory. There are a limited number of slots
|
||||||
|
available and even more limited number that will fit in the L1 MMU.
|
||||||
|
However, using more entries will allow mapping more low memory. This
|
||||||
|
can be useful in optimizing the layout of kernel virtual memory.
|
||||||
|
|
||||||
|
Say N here unless you know what you are doing.
|
||||||
|
|
||||||
|
config LOWMEM_CAM_NUM
|
||||||
|
int "Number of CAMs to use to map low memory" if LOWMEM_CAM_NUM_BOOL
|
||||||
|
default 3
|
||||||
|
|
||||||
config RELOCATABLE
|
config RELOCATABLE
|
||||||
bool "Build a relocatable kernel (EXPERIMENTAL)"
|
bool "Build a relocatable kernel (EXPERIMENTAL)"
|
||||||
depends on EXPERIMENTAL && ADVANCED_OPTIONS && FLATMEM && FSL_BOOKE
|
depends on EXPERIMENTAL && ADVANCED_OPTIONS && FLATMEM && FSL_BOOKE
|
||||||
|
|
@ -794,7 +839,7 @@ config PHYSICAL_START
|
||||||
|
|
||||||
config PHYSICAL_ALIGN
|
config PHYSICAL_ALIGN
|
||||||
hex
|
hex
|
||||||
default "0x10000000" if FSL_BOOKE
|
default "0x04000000" if FSL_BOOKE
|
||||||
help
|
help
|
||||||
This value puts the alignment restrictions on physical address
|
This value puts the alignment restrictions on physical address
|
||||||
where kernel is loaded and run from. Kernel is compiled for an
|
where kernel is loaded and run from. Kernel is compiled for an
|
||||||
|
|
@ -815,31 +860,6 @@ config TASK_SIZE
|
||||||
default "0x80000000" if PPC_PREP || PPC_8xx
|
default "0x80000000" if PPC_PREP || PPC_8xx
|
||||||
default "0xc0000000"
|
default "0xc0000000"
|
||||||
|
|
||||||
config CONSISTENT_START_BOOL
|
|
||||||
bool "Set custom consistent memory pool address"
|
|
||||||
depends on ADVANCED_OPTIONS && NOT_COHERENT_CACHE
|
|
||||||
help
|
|
||||||
This option allows you to set the base virtual address
|
|
||||||
of the consistent memory pool. This pool of virtual
|
|
||||||
memory is used to make consistent memory allocations.
|
|
||||||
|
|
||||||
config CONSISTENT_START
|
|
||||||
hex "Base virtual address of consistent memory pool" if CONSISTENT_START_BOOL
|
|
||||||
default "0xfd000000" if (NOT_COHERENT_CACHE && 8xx)
|
|
||||||
default "0xff100000" if NOT_COHERENT_CACHE
|
|
||||||
|
|
||||||
config CONSISTENT_SIZE_BOOL
|
|
||||||
bool "Set custom consistent memory pool size"
|
|
||||||
depends on ADVANCED_OPTIONS && NOT_COHERENT_CACHE
|
|
||||||
help
|
|
||||||
This option allows you to set the size of the
|
|
||||||
consistent memory pool. This pool of virtual memory
|
|
||||||
is used to make consistent memory allocations.
|
|
||||||
|
|
||||||
config CONSISTENT_SIZE
|
|
||||||
hex "Size of consistent memory pool" if CONSISTENT_SIZE_BOOL
|
|
||||||
default "0x00200000" if NOT_COHERENT_CACHE
|
|
||||||
|
|
||||||
config PIN_TLB
|
config PIN_TLB
|
||||||
bool "Pinned Kernel TLBs (860 ONLY)"
|
bool "Pinned Kernel TLBs (860 ONLY)"
|
||||||
depends on ADVANCED_OPTIONS && 8xx
|
depends on ADVANCED_OPTIONS && 8xx
|
||||||
|
|
|
||||||
|
|
@ -129,7 +129,7 @@ config BDI_SWITCH
|
||||||
|
|
||||||
config BOOTX_TEXT
|
config BOOTX_TEXT
|
||||||
bool "Support for early boot text console (BootX or OpenFirmware only)"
|
bool "Support for early boot text console (BootX or OpenFirmware only)"
|
||||||
depends on PPC_OF && PPC_MULTIPLATFORM
|
depends on PPC_OF && PPC_BOOK3S
|
||||||
help
|
help
|
||||||
Say Y here to see progress messages from the boot firmware in text
|
Say Y here to see progress messages from the boot firmware in text
|
||||||
mode. Requires either BootX or Open Firmware.
|
mode. Requires either BootX or Open Firmware.
|
||||||
|
|
|
||||||
|
|
@ -147,8 +147,8 @@ core-y += arch/powerpc/kernel/ \
|
||||||
arch/powerpc/mm/ \
|
arch/powerpc/mm/ \
|
||||||
arch/powerpc/lib/ \
|
arch/powerpc/lib/ \
|
||||||
arch/powerpc/sysdev/ \
|
arch/powerpc/sysdev/ \
|
||||||
arch/powerpc/platforms/
|
arch/powerpc/platforms/ \
|
||||||
core-$(CONFIG_MATH_EMULATION) += arch/powerpc/math-emu/
|
arch/powerpc/math-emu/
|
||||||
core-$(CONFIG_XMON) += arch/powerpc/xmon/
|
core-$(CONFIG_XMON) += arch/powerpc/xmon/
|
||||||
core-$(CONFIG_KVM) += arch/powerpc/kvm/
|
core-$(CONFIG_KVM) += arch/powerpc/kvm/
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -70,7 +70,7 @@ src-plat := of.c cuboot-52xx.c cuboot-824x.c cuboot-83xx.c cuboot-85xx.c holly.c
|
||||||
cuboot-katmai.c cuboot-rainier.c redboot-8xx.c ep8248e.c \
|
cuboot-katmai.c cuboot-rainier.c redboot-8xx.c ep8248e.c \
|
||||||
cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \
|
cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \
|
||||||
virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \
|
virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \
|
||||||
cuboot-acadia.c
|
cuboot-acadia.c cuboot-amigaone.c
|
||||||
src-boot := $(src-wlib) $(src-plat) empty.c
|
src-boot := $(src-wlib) $(src-plat) empty.c
|
||||||
|
|
||||||
src-boot := $(addprefix $(obj)/, $(src-boot))
|
src-boot := $(addprefix $(obj)/, $(src-boot))
|
||||||
|
|
@ -235,7 +235,9 @@ image-$(CONFIG_PPC_ADDER875) += cuImage.adder875-uboot \
|
||||||
dtbImage.adder875-redboot
|
dtbImage.adder875-redboot
|
||||||
|
|
||||||
# Board ports in arch/powerpc/platform/52xx/Kconfig
|
# Board ports in arch/powerpc/platform/52xx/Kconfig
|
||||||
image-$(CONFIG_PPC_LITE5200) += cuImage.lite5200 cuImage.lite5200b
|
image-$(CONFIG_PPC_LITE5200) += cuImage.lite5200 lite5200.dtb
|
||||||
|
image-$(CONFIG_PPC_LITE5200) += cuImage.lite5200b lite5200b.dtb
|
||||||
|
image-$(CONFIG_PPC_MEDIA5200) += cuImage.media5200 media5200.dtb
|
||||||
|
|
||||||
# Board ports in arch/powerpc/platform/82xx/Kconfig
|
# Board ports in arch/powerpc/platform/82xx/Kconfig
|
||||||
image-$(CONFIG_MPC8272_ADS) += cuImage.mpc8272ads
|
image-$(CONFIG_MPC8272_ADS) += cuImage.mpc8272ads
|
||||||
|
|
@ -274,6 +276,9 @@ image-$(CONFIG_STORCENTER) += cuImage.storcenter
|
||||||
image-$(CONFIG_MPC7448HPC2) += cuImage.mpc7448hpc2
|
image-$(CONFIG_MPC7448HPC2) += cuImage.mpc7448hpc2
|
||||||
image-$(CONFIG_PPC_C2K) += cuImage.c2k
|
image-$(CONFIG_PPC_C2K) += cuImage.c2k
|
||||||
|
|
||||||
|
# Board port in arch/powerpc/platform/amigaone/Kconfig
|
||||||
|
image-$(CONFIG_AMIGAONE) += cuImage.amigaone
|
||||||
|
|
||||||
# For 32-bit powermacs, build the COFF and miboot images
|
# For 32-bit powermacs, build the COFF and miboot images
|
||||||
# as well as the ELF images.
|
# as well as the ELF images.
|
||||||
ifeq ($(CONFIG_PPC32),y)
|
ifeq ($(CONFIG_PPC32),y)
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,35 @@
|
||||||
|
/*
|
||||||
|
* Old U-boot compatibility for AmigaOne
|
||||||
|
*
|
||||||
|
* Author: Gerhard Pircher (gerhard_pircher@gmx.net)
|
||||||
|
*
|
||||||
|
* Based on cuboot-83xx.c
|
||||||
|
* Copyright (c) 2007 Freescale Semiconductor, Inc.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms of the GNU General Public License version 2 as published
|
||||||
|
* by the Free Software Foundation.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "ops.h"
|
||||||
|
#include "stdio.h"
|
||||||
|
#include "cuboot.h"
|
||||||
|
|
||||||
|
#include "ppcboot.h"
|
||||||
|
|
||||||
|
static bd_t bd;
|
||||||
|
|
||||||
|
static void platform_fixups(void)
|
||||||
|
{
|
||||||
|
dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
|
||||||
|
dt_fixup_cpu_clocks(bd.bi_intfreq, bd.bi_busfreq / 4, bd.bi_busfreq);
|
||||||
|
}
|
||||||
|
|
||||||
|
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
|
||||||
|
unsigned long r6, unsigned long r7)
|
||||||
|
{
|
||||||
|
CUBOOT_INIT();
|
||||||
|
fdt_init(_dtb_start);
|
||||||
|
serial_console_init();
|
||||||
|
platform_ops.fixups = platform_fixups;
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,173 @@
|
||||||
|
/*
|
||||||
|
* AmigaOne Device Tree Source
|
||||||
|
*
|
||||||
|
* Copyright 2008 Gerhard Pircher (gerhard_pircher@gmx.net)
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms of the GNU General Public License as published by the
|
||||||
|
* Free Software Foundation; either version 2 of the License, or (at your
|
||||||
|
* option) any later version.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "AmigaOne";
|
||||||
|
compatible = "eyetech,amigaone";
|
||||||
|
coherency-off;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
|
||||||
|
cpus {
|
||||||
|
#cpus = <1>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
cpu@0 {
|
||||||
|
device_type = "cpu";
|
||||||
|
reg = <0>;
|
||||||
|
d-cache-line-size = <32>; // 32 bytes
|
||||||
|
i-cache-line-size = <32>; // 32 bytes
|
||||||
|
d-cache-size = <32768>; // L1, 32K
|
||||||
|
i-cache-size = <32768>; // L1, 32K
|
||||||
|
timebase-frequency = <0>; // 33.3 MHz, from U-boot
|
||||||
|
clock-frequency = <0>; // From U-boot
|
||||||
|
bus-frequency = <0>; // From U-boot
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
memory {
|
||||||
|
device_type = "memory";
|
||||||
|
reg = <0 0>; // From U-boot
|
||||||
|
};
|
||||||
|
|
||||||
|
pci@80000000 {
|
||||||
|
device_type = "pci";
|
||||||
|
compatible = "mai-logic,articia-s";
|
||||||
|
bus-frequency = <33333333>;
|
||||||
|
bus-range = <0 0xff>;
|
||||||
|
ranges = <0x01000000 0 0x00000000 0xfe000000 0 0x00c00000 // PCI I/O
|
||||||
|
0x02000000 0 0x80000000 0x80000000 0 0x7d000000 // PCI memory
|
||||||
|
0x02000000 0 0x00000000 0xfd000000 0 0x01000000>; // PCI alias memory (ISA)
|
||||||
|
// Configuration address and data register.
|
||||||
|
reg = <0xfec00cf8 4
|
||||||
|
0xfee00cfc 4>;
|
||||||
|
8259-interrupt-acknowledge = <0xfef00000>;
|
||||||
|
// Do not define a interrupt-parent here, if there is no
|
||||||
|
// interrupt-map property.
|
||||||
|
#address-cells = <3>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
|
||||||
|
isa@7 {
|
||||||
|
device_type = "isa";
|
||||||
|
compatible = "pciclass,0601";
|
||||||
|
vendor-id = <0x00001106>;
|
||||||
|
device-id = <0x00000686>;
|
||||||
|
revision-id = <0x00000010>;
|
||||||
|
class-code = <0x00060100>;
|
||||||
|
subsystem-id = <0>;
|
||||||
|
subsystem-vendor-id = <0>;
|
||||||
|
devsel-speed = <0x00000001>;
|
||||||
|
min-grant = <0>;
|
||||||
|
max-latency = <0>;
|
||||||
|
/* First 64k for I/O at 0x0 on PCI mapped to 0x0 on ISA. */
|
||||||
|
ranges = <0x00000001 0 0x01000000 0 0x00000000 0x00010000>;
|
||||||
|
interrupt-parent = <&i8259>;
|
||||||
|
#interrupt-cells = <2>;
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
|
||||||
|
dma-controller@0 {
|
||||||
|
compatible = "pnpPNP,200";
|
||||||
|
reg = <1 0x00000000 0x00000020
|
||||||
|
1 0x00000080 0x00000010
|
||||||
|
1 0x000000c0 0x00000020>;
|
||||||
|
};
|
||||||
|
|
||||||
|
i8259: interrupt-controller@20 {
|
||||||
|
device_type = "interrupt-controller";
|
||||||
|
compatible = "pnpPNP,000";
|
||||||
|
interrupt-controller;
|
||||||
|
reg = <1 0x00000020 0x00000002
|
||||||
|
1 0x000000a0 0x00000002
|
||||||
|
1 0x000004d0 0x00000002>;
|
||||||
|
reserved-interrupts = <2>;
|
||||||
|
#interrupt-cells = <2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer@40 {
|
||||||
|
// Also adds pcspkr to platform devices.
|
||||||
|
compatible = "pnpPNP,100";
|
||||||
|
reg = <1 0x00000040 0x00000020>;
|
||||||
|
};
|
||||||
|
|
||||||
|
8042@60 {
|
||||||
|
device_type = "8042";
|
||||||
|
reg = <1 0x00000060 0x00000001
|
||||||
|
1 0x00000064 0x00000001>;
|
||||||
|
interrupts = <1 3 12 3>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
keyboard@0 {
|
||||||
|
compatible = "pnpPNP,303";
|
||||||
|
reg = <0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
mouse@1 {
|
||||||
|
compatible = "pnpPNP,f03";
|
||||||
|
reg = <1>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
rtc@70 {
|
||||||
|
compatible = "pnpPNP,b00";
|
||||||
|
reg = <1 0x00000070 0x00000002>;
|
||||||
|
interrupts = <8 3>;
|
||||||
|
};
|
||||||
|
|
||||||
|
serial@3f8 {
|
||||||
|
device_type = "serial";
|
||||||
|
compatible = "pnpPNP,501","pnpPNP,500";
|
||||||
|
reg = <1 0x000003f8 0x00000008>;
|
||||||
|
interrupts = <4 3>;
|
||||||
|
clock-frequency = <1843200>;
|
||||||
|
current-speed = <115200>;
|
||||||
|
};
|
||||||
|
|
||||||
|
serial@2f8 {
|
||||||
|
device_type = "serial";
|
||||||
|
compatible = "pnpPNP,501","pnpPNP,500";
|
||||||
|
reg = <1 0x000002f8 0x00000008>;
|
||||||
|
interrupts = <3 3>;
|
||||||
|
clock-frequency = <1843200>;
|
||||||
|
current-speed = <115200>;
|
||||||
|
};
|
||||||
|
|
||||||
|
parallel@378 {
|
||||||
|
device_type = "parallel";
|
||||||
|
// No ECP support for now, otherwise add "pnpPNP,401".
|
||||||
|
compatible = "pnpPNP,400";
|
||||||
|
reg = <1 0x00000378 0x00000003
|
||||||
|
1 0x00000778 0x00000003>;
|
||||||
|
};
|
||||||
|
|
||||||
|
fdc@3f0 {
|
||||||
|
device_type = "fdc";
|
||||||
|
compatible = "pnpPNP,700";
|
||||||
|
reg = <1 0x000003f0 0x00000008>;
|
||||||
|
interrupts = <6 3>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
disk@0 {
|
||||||
|
reg = <0>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
chosen {
|
||||||
|
linux,stdout-path = "/pci@80000000/isa@7/serial@3f8";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
@ -181,70 +181,76 @@
|
||||||
phy_type = "ulpi";
|
phy_type = "ulpi";
|
||||||
};
|
};
|
||||||
|
|
||||||
mdio@24520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-mdio";
|
|
||||||
reg = <0x24520 0x20>;
|
|
||||||
|
|
||||||
phy0: ethernet-phy@0 {
|
|
||||||
interrupt-parent = <&ipic>;
|
|
||||||
interrupts = <17 0x8>;
|
|
||||||
reg = <0x1>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
phy1: ethernet-phy@1 {
|
|
||||||
interrupt-parent = <&ipic>;
|
|
||||||
interrupts = <18 0x8>;
|
|
||||||
reg = <0x2>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
|
|
||||||
tbi0: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
mdio@25520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-tbi";
|
|
||||||
reg = <0x25520 0x20>;
|
|
||||||
|
|
||||||
tbi1: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
|
|
||||||
enet0: ethernet@24000 {
|
enet0: ethernet@24000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <0>;
|
cell-index = <0>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "TSEC";
|
model = "TSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x24000 0x1000>;
|
reg = <0x24000 0x1000>;
|
||||||
|
ranges = <0x0 0x24000 0x1000>;
|
||||||
local-mac-address = [ 00 08 e5 11 32 33 ];
|
local-mac-address = [ 00 08 e5 11 32 33 ];
|
||||||
interrupts = <32 0x8 33 0x8 34 0x8>;
|
interrupts = <32 0x8 33 0x8 34 0x8>;
|
||||||
interrupt-parent = <&ipic>;
|
interrupt-parent = <&ipic>;
|
||||||
tbi-handle = <&tbi0>;
|
tbi-handle = <&tbi0>;
|
||||||
phy-handle = <&phy0>;
|
phy-handle = <&phy0>;
|
||||||
linux,network-index = <0>;
|
linux,network-index = <0>;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-mdio";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
phy0: ethernet-phy@0 {
|
||||||
|
interrupt-parent = <&ipic>;
|
||||||
|
interrupts = <17 0x8>;
|
||||||
|
reg = <0x1>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
|
||||||
|
phy1: ethernet-phy@1 {
|
||||||
|
interrupt-parent = <&ipic>;
|
||||||
|
interrupts = <18 0x8>;
|
||||||
|
reg = <0x2>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
|
||||||
|
tbi0: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
enet1: ethernet@25000 {
|
enet1: ethernet@25000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <1>;
|
cell-index = <1>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "TSEC";
|
model = "TSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x25000 0x1000>;
|
reg = <0x25000 0x1000>;
|
||||||
|
ranges = <0x0 0x25000 0x1000>;
|
||||||
local-mac-address = [ 00 08 e5 11 32 34 ];
|
local-mac-address = [ 00 08 e5 11 32 34 ];
|
||||||
interrupts = <35 0x8 36 0x8 37 0x8>;
|
interrupts = <35 0x8 36 0x8 37 0x8>;
|
||||||
interrupt-parent = <&ipic>;
|
interrupt-parent = <&ipic>;
|
||||||
tbi-handle = <&tbi1>;
|
tbi-handle = <&tbi1>;
|
||||||
phy-handle = <&phy1>;
|
phy-handle = <&phy1>;
|
||||||
linux,network-index = <1>;
|
linux,network-index = <1>;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-tbi";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
tbi1: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
serial0: serial@4500 {
|
serial0: serial@4500 {
|
||||||
|
|
|
||||||
|
|
@ -149,6 +149,20 @@
|
||||||
/*RXDE*/ 0x5 0x4>;
|
/*RXDE*/ 0x5 0x4>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
USB0: ehci@bffd0400 {
|
||||||
|
compatible = "ibm,usb-ehci-460ex", "usb-ehci";
|
||||||
|
interrupt-parent = <&UIC2>;
|
||||||
|
interrupts = <0x1d 4>;
|
||||||
|
reg = <4 0xbffd0400 0x90 4 0xbffd0490 0x70>;
|
||||||
|
};
|
||||||
|
|
||||||
|
USB1: usb@bffd0000 {
|
||||||
|
compatible = "ohci-le";
|
||||||
|
reg = <4 0xbffd0000 0x60>;
|
||||||
|
interrupt-parent = <&UIC2>;
|
||||||
|
interrupts = <0x1e 4>;
|
||||||
|
};
|
||||||
|
|
||||||
POB0: opb {
|
POB0: opb {
|
||||||
compatible = "ibm,opb-460ex", "ibm,opb";
|
compatible = "ibm,opb-460ex", "ibm,opb";
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
|
|
@ -252,6 +266,20 @@
|
||||||
reg = <0xef600700 0x00000014>;
|
reg = <0xef600700 0x00000014>;
|
||||||
interrupt-parent = <&UIC0>;
|
interrupt-parent = <&UIC0>;
|
||||||
interrupts = <0x2 0x4>;
|
interrupts = <0x2 0x4>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
rtc@68 {
|
||||||
|
compatible = "stm,m41t80";
|
||||||
|
reg = <0x68>;
|
||||||
|
interrupt-parent = <&UIC2>;
|
||||||
|
interrupts = <0x19 0x8>;
|
||||||
|
};
|
||||||
|
sttm@48 {
|
||||||
|
compatible = "ad,ad7414";
|
||||||
|
reg = <0x48>;
|
||||||
|
interrupt-parent = <&UIC1>;
|
||||||
|
interrupts = <0x14 0x8>;
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
IIC1: i2c@ef600800 {
|
IIC1: i2c@ef600800 {
|
||||||
|
|
|
||||||
|
|
@ -17,6 +17,7 @@
|
||||||
compatible = "schindler,cm5200";
|
compatible = "schindler,cm5200";
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <1>;
|
#size-cells = <1>;
|
||||||
|
interrupt-parent = <&mpc5200_pic>;
|
||||||
|
|
||||||
cpus {
|
cpus {
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
|
|
@ -66,7 +67,6 @@
|
||||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||||
reg = <0x600 0x10>;
|
reg = <0x600 0x10>;
|
||||||
interrupts = <1 9 0>;
|
interrupts = <1 9 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
fsl,has-wdt;
|
fsl,has-wdt;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -74,84 +74,76 @@
|
||||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||||
reg = <0x610 0x10>;
|
reg = <0x610 0x10>;
|
||||||
interrupts = <1 10 0>;
|
interrupts = <1 10 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
timer@620 { // General Purpose Timer
|
timer@620 { // General Purpose Timer
|
||||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||||
reg = <0x620 0x10>;
|
reg = <0x620 0x10>;
|
||||||
interrupts = <1 11 0>;
|
interrupts = <1 11 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
timer@630 { // General Purpose Timer
|
timer@630 { // General Purpose Timer
|
||||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||||
reg = <0x630 0x10>;
|
reg = <0x630 0x10>;
|
||||||
interrupts = <1 12 0>;
|
interrupts = <1 12 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
timer@640 { // General Purpose Timer
|
timer@640 { // General Purpose Timer
|
||||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||||
reg = <0x640 0x10>;
|
reg = <0x640 0x10>;
|
||||||
interrupts = <1 13 0>;
|
interrupts = <1 13 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
timer@650 { // General Purpose Timer
|
timer@650 { // General Purpose Timer
|
||||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||||
reg = <0x650 0x10>;
|
reg = <0x650 0x10>;
|
||||||
interrupts = <1 14 0>;
|
interrupts = <1 14 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
timer@660 { // General Purpose Timer
|
timer@660 { // General Purpose Timer
|
||||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||||
reg = <0x660 0x10>;
|
reg = <0x660 0x10>;
|
||||||
interrupts = <1 15 0>;
|
interrupts = <1 15 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
timer@670 { // General Purpose Timer
|
timer@670 { // General Purpose Timer
|
||||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||||
reg = <0x670 0x10>;
|
reg = <0x670 0x10>;
|
||||||
interrupts = <1 16 0>;
|
interrupts = <1 16 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
rtc@800 { // Real time clock
|
rtc@800 { // Real time clock
|
||||||
compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
|
compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
|
||||||
reg = <0x800 0x100>;
|
reg = <0x800 0x100>;
|
||||||
interrupts = <1 5 0 1 6 0>;
|
interrupts = <1 5 0 1 6 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
gpio@b00 {
|
gpio_simple: gpio@b00 {
|
||||||
compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
|
compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
|
||||||
reg = <0xb00 0x40>;
|
reg = <0xb00 0x40>;
|
||||||
interrupts = <1 7 0>;
|
interrupts = <1 7 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
gpio-controller;
|
||||||
|
#gpio-cells = <2>;
|
||||||
};
|
};
|
||||||
|
|
||||||
gpio@c00 {
|
gpio_wkup: gpio@c00 {
|
||||||
compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
|
compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
|
||||||
reg = <0xc00 0x40>;
|
reg = <0xc00 0x40>;
|
||||||
interrupts = <1 8 0 0 3 0>;
|
interrupts = <1 8 0 0 3 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
gpio-controller;
|
||||||
|
#gpio-cells = <2>;
|
||||||
};
|
};
|
||||||
|
|
||||||
spi@f00 {
|
spi@f00 {
|
||||||
compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
|
compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
|
||||||
reg = <0xf00 0x20>;
|
reg = <0xf00 0x20>;
|
||||||
interrupts = <2 13 0 2 14 0>;
|
interrupts = <2 13 0 2 14 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
usb@1000 {
|
usb@1000 {
|
||||||
compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
|
compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
|
||||||
reg = <0x1000 0xff>;
|
reg = <0x1000 0xff>;
|
||||||
interrupts = <2 6 0>;
|
interrupts = <2 6 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
dma-controller@1200 {
|
dma-controller@1200 {
|
||||||
|
|
@ -161,7 +153,6 @@
|
||||||
3 4 0 3 5 0 3 6 0 3 7 0
|
3 4 0 3 5 0 3 6 0 3 7 0
|
||||||
3 8 0 3 9 0 3 10 0 3 11 0
|
3 8 0 3 9 0 3 10 0 3 11 0
|
||||||
3 12 0 3 13 0 3 14 0 3 15 0>;
|
3 12 0 3 13 0 3 14 0 3 15 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
xlb@1f00 {
|
xlb@1f00 {
|
||||||
|
|
@ -170,48 +161,34 @@
|
||||||
};
|
};
|
||||||
|
|
||||||
serial@2000 { // PSC1
|
serial@2000 { // PSC1
|
||||||
device_type = "serial";
|
|
||||||
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||||
port-number = <0>; // Logical port assignment
|
|
||||||
reg = <0x2000 0x100>;
|
reg = <0x2000 0x100>;
|
||||||
interrupts = <2 1 0>;
|
interrupts = <2 1 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
serial@2200 { // PSC2
|
serial@2200 { // PSC2
|
||||||
device_type = "serial";
|
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||||
compatible = "fsl,mpc5200-psc-uart";
|
|
||||||
port-number = <1>; // Logical port assignment
|
|
||||||
reg = <0x2200 0x100>;
|
reg = <0x2200 0x100>;
|
||||||
interrupts = <2 2 0>;
|
interrupts = <2 2 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
serial@2400 { // PSC3
|
serial@2400 { // PSC3
|
||||||
device_type = "serial";
|
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||||
compatible = "fsl,mpc5200-psc-uart";
|
|
||||||
port-number = <2>; // Logical port assignment
|
|
||||||
reg = <0x2400 0x100>;
|
reg = <0x2400 0x100>;
|
||||||
interrupts = <2 3 0>;
|
interrupts = <2 3 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
serial@2c00 { // PSC6
|
serial@2c00 { // PSC6
|
||||||
device_type = "serial";
|
|
||||||
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||||
port-number = <5>; // Logical port assignment
|
|
||||||
reg = <0x2c00 0x100>;
|
reg = <0x2c00 0x100>;
|
||||||
interrupts = <2 4 0>;
|
interrupts = <2 4 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
ethernet@3000 {
|
ethernet@3000 {
|
||||||
device_type = "network";
|
|
||||||
compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
|
compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
|
||||||
reg = <0x3000 0x400>;
|
reg = <0x3000 0x400>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <2 5 0>;
|
interrupts = <2 5 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
phy-handle = <&phy0>;
|
phy-handle = <&phy0>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -221,10 +198,8 @@
|
||||||
compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
|
compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
|
||||||
reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
|
reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
|
||||||
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
|
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
|
|
||||||
phy0: ethernet-phy@0 {
|
phy0: ethernet-phy@0 {
|
||||||
device_type = "ethernet-phy";
|
|
||||||
reg = <0>;
|
reg = <0>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
@ -235,7 +210,6 @@
|
||||||
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
|
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
|
||||||
reg = <0x3d40 0x40>;
|
reg = <0x3d40 0x40>;
|
||||||
interrupts = <2 16 0>;
|
interrupts = <2 16 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
fsl5200-clocking;
|
fsl5200-clocking;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -245,9 +219,8 @@
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
lpb {
|
localbus {
|
||||||
model = "fsl,lpb";
|
compatible = "fsl,mpc5200b-lpb","simple-bus";
|
||||||
compatible = "fsl,lpb";
|
|
||||||
#address-cells = <2>;
|
#address-cells = <2>;
|
||||||
#size-cells = <1>;
|
#size-cells = <1>;
|
||||||
ranges = <0 0 0xfc000000 0x2000000>;
|
ranges = <0 0 0xfc000000 0x2000000>;
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,254 @@
|
||||||
|
/*
|
||||||
|
* Digsy MTC board Device Tree Source
|
||||||
|
*
|
||||||
|
* Copyright (C) 2009 Semihalf
|
||||||
|
*
|
||||||
|
* Based on the CM5200 by M. Balakowicz
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms of the GNU General Public License as published by the
|
||||||
|
* Free Software Foundation; either version 2 of the License, or (at your
|
||||||
|
* option) any later version.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "intercontrol,digsy-mtc";
|
||||||
|
compatible = "intercontrol,digsy-mtc";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
interrupt-parent = <&mpc5200_pic>;
|
||||||
|
|
||||||
|
cpus {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
PowerPC,5200@0 {
|
||||||
|
device_type = "cpu";
|
||||||
|
reg = <0>;
|
||||||
|
d-cache-line-size = <32>;
|
||||||
|
i-cache-line-size = <32>;
|
||||||
|
d-cache-size = <0x4000>; // L1, 16K
|
||||||
|
i-cache-size = <0x4000>; // L1, 16K
|
||||||
|
timebase-frequency = <0>; // from bootloader
|
||||||
|
bus-frequency = <0>; // from bootloader
|
||||||
|
clock-frequency = <0>; // from bootloader
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
memory {
|
||||||
|
device_type = "memory";
|
||||||
|
reg = <0x00000000 0x02000000>; // 32MB
|
||||||
|
};
|
||||||
|
|
||||||
|
soc5200@f0000000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
compatible = "fsl,mpc5200b-immr";
|
||||||
|
ranges = <0 0xf0000000 0x0000c000>;
|
||||||
|
reg = <0xf0000000 0x00000100>;
|
||||||
|
bus-frequency = <0>; // from bootloader
|
||||||
|
system-frequency = <0>; // from bootloader
|
||||||
|
|
||||||
|
cdm@200 {
|
||||||
|
compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
|
||||||
|
reg = <0x200 0x38>;
|
||||||
|
};
|
||||||
|
|
||||||
|
mpc5200_pic: interrupt-controller@500 {
|
||||||
|
// 5200 interrupts are encoded into two levels;
|
||||||
|
interrupt-controller;
|
||||||
|
#interrupt-cells = <3>;
|
||||||
|
compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
|
||||||
|
reg = <0x500 0x80>;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer@600 { // General Purpose Timer
|
||||||
|
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||||
|
reg = <0x600 0x10>;
|
||||||
|
interrupts = <1 9 0>;
|
||||||
|
fsl,has-wdt;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer@610 { // General Purpose Timer
|
||||||
|
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||||
|
reg = <0x610 0x10>;
|
||||||
|
interrupts = <1 10 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer@620 { // General Purpose Timer
|
||||||
|
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||||
|
reg = <0x620 0x10>;
|
||||||
|
interrupts = <1 11 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer@630 { // General Purpose Timer
|
||||||
|
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||||
|
reg = <0x630 0x10>;
|
||||||
|
interrupts = <1 12 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer@640 { // General Purpose Timer
|
||||||
|
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||||
|
reg = <0x640 0x10>;
|
||||||
|
interrupts = <1 13 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer@650 { // General Purpose Timer
|
||||||
|
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||||
|
reg = <0x650 0x10>;
|
||||||
|
interrupts = <1 14 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer@660 { // General Purpose Timer
|
||||||
|
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||||
|
reg = <0x660 0x10>;
|
||||||
|
interrupts = <1 15 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer@670 { // General Purpose Timer
|
||||||
|
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||||
|
reg = <0x670 0x10>;
|
||||||
|
interrupts = <1 16 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
gpio_simple: gpio@b00 {
|
||||||
|
compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
|
||||||
|
reg = <0xb00 0x40>;
|
||||||
|
interrupts = <1 7 0>;
|
||||||
|
gpio-controller;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
gpio_wkup: gpio@c00 {
|
||||||
|
compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
|
||||||
|
reg = <0xc00 0x40>;
|
||||||
|
interrupts = <1 8 0 0 3 0>;
|
||||||
|
gpio-controller;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
spi@f00 {
|
||||||
|
compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
|
||||||
|
reg = <0xf00 0x20>;
|
||||||
|
interrupts = <2 13 0 2 14 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
usb@1000 {
|
||||||
|
compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
|
||||||
|
reg = <0x1000 0xff>;
|
||||||
|
interrupts = <2 6 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
dma-controller@1200 {
|
||||||
|
compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
|
||||||
|
reg = <0x1200 0x80>;
|
||||||
|
interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
|
||||||
|
3 4 0 3 5 0 3 6 0 3 7 0
|
||||||
|
3 8 0 3 9 0 3 10 0 3 11 0
|
||||||
|
3 12 0 3 13 0 3 14 0 3 15 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
xlb@1f00 {
|
||||||
|
compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
|
||||||
|
reg = <0x1f00 0x100>;
|
||||||
|
};
|
||||||
|
|
||||||
|
serial@2600 { // PSC4
|
||||||
|
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||||
|
reg = <0x2600 0x100>;
|
||||||
|
interrupts = <2 11 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
serial@2800 { // PSC5
|
||||||
|
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||||
|
reg = <0x2800 0x100>;
|
||||||
|
interrupts = <2 12 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
ethernet@3000 {
|
||||||
|
compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
|
||||||
|
reg = <0x3000 0x400>;
|
||||||
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
|
interrupts = <2 5 0>;
|
||||||
|
phy-handle = <&phy0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
mdio@3000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
|
||||||
|
reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
|
||||||
|
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
|
||||||
|
|
||||||
|
phy0: ethernet-phy@0 {
|
||||||
|
reg = <0>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
ata@3a00 {
|
||||||
|
compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
|
||||||
|
reg = <0x3a00 0x100>;
|
||||||
|
interrupts = <2 7 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
i2c@3d00 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
|
||||||
|
reg = <0x3d00 0x40>;
|
||||||
|
interrupts = <2 15 0>;
|
||||||
|
fsl5200-clocking;
|
||||||
|
|
||||||
|
rtc@50 {
|
||||||
|
compatible = "at,24c08";
|
||||||
|
reg = <0x50>;
|
||||||
|
};
|
||||||
|
|
||||||
|
rtc@68 {
|
||||||
|
compatible = "dallas,ds1339";
|
||||||
|
reg = <0x68>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
sram@8000 {
|
||||||
|
compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
|
||||||
|
reg = <0x8000 0x4000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
lpb {
|
||||||
|
compatible = "fsl,mpc5200b-lpb","simple-bus";
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
ranges = <0 0 0xff000000 0x1000000>;
|
||||||
|
|
||||||
|
// 16-bit flash device at LocalPlus Bus CS0
|
||||||
|
flash@0,0 {
|
||||||
|
compatible = "cfi-flash";
|
||||||
|
reg = <0 0 0x1000000>;
|
||||||
|
bank-width = <2>;
|
||||||
|
device-width = <2>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
|
||||||
|
partition@0 {
|
||||||
|
label = "kernel";
|
||||||
|
reg = <0x0 0x00200000>;
|
||||||
|
};
|
||||||
|
partition@200000 {
|
||||||
|
label = "root";
|
||||||
|
reg = <0x00200000 0x00300000>;
|
||||||
|
};
|
||||||
|
partition@500000 {
|
||||||
|
label = "user";
|
||||||
|
reg = <0x00500000 0x00a00000>;
|
||||||
|
};
|
||||||
|
partition@f00000 {
|
||||||
|
label = "u-boot";
|
||||||
|
reg = <0x00f00000 0x100000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,367 @@
|
||||||
|
/*
|
||||||
|
* GE Fanuc PPC9A Device Tree Source
|
||||||
|
*
|
||||||
|
* Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms of the GNU General Public License as published by the
|
||||||
|
* Free Software Foundation; either version 2 of the License, or (at your
|
||||||
|
* option) any later version.
|
||||||
|
*
|
||||||
|
* Based on: SBS CM6 Device Tree Source
|
||||||
|
* Copyright 2007 SBS Technologies GmbH & Co. KG
|
||||||
|
* And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source)
|
||||||
|
* Copyright 2006 Freescale Semiconductor Inc.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Compiled with dtc -I dts -O dtb -o gef_ppc9a.dtb gef_ppc9a.dts
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "GEF_PPC9A";
|
||||||
|
compatible = "gef,ppc9a";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
|
||||||
|
aliases {
|
||||||
|
ethernet0 = &enet0;
|
||||||
|
ethernet1 = &enet1;
|
||||||
|
serial0 = &serial0;
|
||||||
|
serial1 = &serial1;
|
||||||
|
pci0 = &pci0;
|
||||||
|
};
|
||||||
|
|
||||||
|
cpus {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
PowerPC,8641@0 {
|
||||||
|
device_type = "cpu";
|
||||||
|
reg = <0>;
|
||||||
|
d-cache-line-size = <32>; // 32 bytes
|
||||||
|
i-cache-line-size = <32>; // 32 bytes
|
||||||
|
d-cache-size = <32768>; // L1, 32K
|
||||||
|
i-cache-size = <32768>; // L1, 32K
|
||||||
|
timebase-frequency = <0>; // From uboot
|
||||||
|
bus-frequency = <0>; // From uboot
|
||||||
|
clock-frequency = <0>; // From uboot
|
||||||
|
};
|
||||||
|
PowerPC,8641@1 {
|
||||||
|
device_type = "cpu";
|
||||||
|
reg = <1>;
|
||||||
|
d-cache-line-size = <32>; // 32 bytes
|
||||||
|
i-cache-line-size = <32>; // 32 bytes
|
||||||
|
d-cache-size = <32768>; // L1, 32K
|
||||||
|
i-cache-size = <32768>; // L1, 32K
|
||||||
|
timebase-frequency = <0>; // From uboot
|
||||||
|
bus-frequency = <0>; // From uboot
|
||||||
|
clock-frequency = <0>; // From uboot
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
memory {
|
||||||
|
device_type = "memory";
|
||||||
|
reg = <0x0 0x40000000>; // set by uboot
|
||||||
|
};
|
||||||
|
|
||||||
|
localbus@fef05000 {
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
compatible = "fsl,mpc8641-localbus", "simple-bus";
|
||||||
|
reg = <0xfef05000 0x1000>;
|
||||||
|
interrupts = <19 2>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
|
||||||
|
ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
|
||||||
|
1 0 0xe8000000 0x08000000 // Paged Flash 0
|
||||||
|
2 0 0xe0000000 0x08000000 // Paged Flash 1
|
||||||
|
3 0 0xfc100000 0x00020000 // NVRAM
|
||||||
|
4 0 0xfc000000 0x00008000 // FPGA
|
||||||
|
5 0 0xfc008000 0x00008000 // AFIX FPGA
|
||||||
|
6 0 0xfd000000 0x00800000 // IO FPGA (8-bit)
|
||||||
|
7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit)
|
||||||
|
|
||||||
|
/* flash@0,0 is a mirror of part of the memory in flash@1,0
|
||||||
|
flash@0,0 {
|
||||||
|
compatible = "gef,ppc9a-firmware-mirror", "cfi-flash";
|
||||||
|
reg = <0x0 0x0 0x1000000>;
|
||||||
|
bank-width = <4>;
|
||||||
|
device-width = <2>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
partition@0 {
|
||||||
|
label = "firmware";
|
||||||
|
reg = <0x0 0x1000000>;
|
||||||
|
read-only;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
*/
|
||||||
|
|
||||||
|
flash@1,0 {
|
||||||
|
compatible = "gef,ppc9a-paged-flash", "cfi-flash";
|
||||||
|
reg = <0x1 0x0 0x8000000>;
|
||||||
|
bank-width = <4>;
|
||||||
|
device-width = <2>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
partition@0 {
|
||||||
|
label = "user";
|
||||||
|
reg = <0x0 0x7800000>;
|
||||||
|
};
|
||||||
|
partition@7800000 {
|
||||||
|
label = "firmware";
|
||||||
|
reg = <0x7800000 0x800000>;
|
||||||
|
read-only;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
fpga@4,0 {
|
||||||
|
compatible = "gef,ppc9a-fpga-regs";
|
||||||
|
reg = <0x4 0x0 0x40>;
|
||||||
|
};
|
||||||
|
|
||||||
|
wdt@4,2000 {
|
||||||
|
compatible = "gef,ppc9a-fpga-wdt", "gef,fpga-wdt-1.00",
|
||||||
|
"gef,fpga-wdt";
|
||||||
|
reg = <0x4 0x2000 0x8>;
|
||||||
|
interrupts = <0x1a 0x4>;
|
||||||
|
interrupt-parent = <&gef_pic>;
|
||||||
|
};
|
||||||
|
/* Second watchdog available, driver currently supports one.
|
||||||
|
wdt@4,2010 {
|
||||||
|
compatible = "gef,ppc9a-fpga-wdt", "gef,fpga-wdt-1.00",
|
||||||
|
"gef,fpga-wdt";
|
||||||
|
reg = <0x4 0x2010 0x8>;
|
||||||
|
interrupts = <0x1b 0x4>;
|
||||||
|
interrupt-parent = <&gef_pic>;
|
||||||
|
};
|
||||||
|
*/
|
||||||
|
gef_pic: pic@4,4000 {
|
||||||
|
#interrupt-cells = <1>;
|
||||||
|
interrupt-controller;
|
||||||
|
compatible = "gef,ppc9a-fpga-pic", "gef,fpga-pic-1.00";
|
||||||
|
reg = <0x4 0x4000 0x20>;
|
||||||
|
interrupts = <0x8
|
||||||
|
0x9>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
|
||||||
|
};
|
||||||
|
gef_gpio: gpio@7,14000 {
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
compatible = "gef,ppc9a-gpio", "gef,sbc610-gpio";
|
||||||
|
reg = <0x7 0x14000 0x24>;
|
||||||
|
gpio-controller;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
soc@fef00000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
#interrupt-cells = <2>;
|
||||||
|
compatible = "fsl,mpc8641-soc", "simple-bus";
|
||||||
|
ranges = <0x0 0xfef00000 0x00100000>;
|
||||||
|
reg = <0xfef00000 0x100000>; // CCSRBAR 1M
|
||||||
|
bus-frequency = <33333333>;
|
||||||
|
|
||||||
|
i2c1: i2c@3000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl-i2c";
|
||||||
|
reg = <0x3000 0x100>;
|
||||||
|
interrupts = <0x2b 0x2>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
dfsrr;
|
||||||
|
|
||||||
|
hwmon@48 {
|
||||||
|
compatible = "national,lm92";
|
||||||
|
reg = <0x48>;
|
||||||
|
};
|
||||||
|
|
||||||
|
hwmon@4c {
|
||||||
|
compatible = "adi,adt7461";
|
||||||
|
reg = <0x4c>;
|
||||||
|
};
|
||||||
|
|
||||||
|
rtc@51 {
|
||||||
|
compatible = "epson,rx8581";
|
||||||
|
reg = <0x00000051>;
|
||||||
|
};
|
||||||
|
|
||||||
|
eti@6b {
|
||||||
|
compatible = "dallas,ds1682";
|
||||||
|
reg = <0x6b>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
i2c2: i2c@3100 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl-i2c";
|
||||||
|
reg = <0x3100 0x100>;
|
||||||
|
interrupts = <0x2b 0x2>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
dfsrr;
|
||||||
|
};
|
||||||
|
|
||||||
|
dma@21300 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
|
||||||
|
reg = <0x21300 0x4>;
|
||||||
|
ranges = <0x0 0x21100 0x200>;
|
||||||
|
cell-index = <0>;
|
||||||
|
dma-channel@0 {
|
||||||
|
compatible = "fsl,mpc8641-dma-channel",
|
||||||
|
"fsl,eloplus-dma-channel";
|
||||||
|
reg = <0x0 0x80>;
|
||||||
|
cell-index = <0>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <20 2>;
|
||||||
|
};
|
||||||
|
dma-channel@80 {
|
||||||
|
compatible = "fsl,mpc8641-dma-channel",
|
||||||
|
"fsl,eloplus-dma-channel";
|
||||||
|
reg = <0x80 0x80>;
|
||||||
|
cell-index = <1>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <21 2>;
|
||||||
|
};
|
||||||
|
dma-channel@100 {
|
||||||
|
compatible = "fsl,mpc8641-dma-channel",
|
||||||
|
"fsl,eloplus-dma-channel";
|
||||||
|
reg = <0x100 0x80>;
|
||||||
|
cell-index = <2>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <22 2>;
|
||||||
|
};
|
||||||
|
dma-channel@180 {
|
||||||
|
compatible = "fsl,mpc8641-dma-channel",
|
||||||
|
"fsl,eloplus-dma-channel";
|
||||||
|
reg = <0x180 0x80>;
|
||||||
|
cell-index = <3>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <23 2>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
enet0: ethernet@24000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
device_type = "network";
|
||||||
|
model = "eTSEC";
|
||||||
|
compatible = "gianfar";
|
||||||
|
reg = <0x24000 0x1000>;
|
||||||
|
ranges = <0x0 0x24000 0x1000>;
|
||||||
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
|
interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
phy-handle = <&phy0>;
|
||||||
|
phy-connection-type = "gmii";
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-mdio";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
phy0: ethernet-phy@0 {
|
||||||
|
interrupt-parent = <&gef_pic>;
|
||||||
|
interrupts = <0x9 0x4>;
|
||||||
|
reg = <1>;
|
||||||
|
};
|
||||||
|
phy2: ethernet-phy@2 {
|
||||||
|
interrupt-parent = <&gef_pic>;
|
||||||
|
interrupts = <0x8 0x4>;
|
||||||
|
reg = <3>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
enet1: ethernet@26000 {
|
||||||
|
device_type = "network";
|
||||||
|
model = "eTSEC";
|
||||||
|
compatible = "gianfar";
|
||||||
|
reg = <0x26000 0x1000>;
|
||||||
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
|
interrupts = <0x1f 0x2 0x20 0x2 0x21 0x2>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
phy-handle = <&phy2>;
|
||||||
|
phy-connection-type = "gmii";
|
||||||
|
};
|
||||||
|
|
||||||
|
serial0: serial@4500 {
|
||||||
|
cell-index = <0>;
|
||||||
|
device_type = "serial";
|
||||||
|
compatible = "ns16550";
|
||||||
|
reg = <0x4500 0x100>;
|
||||||
|
clock-frequency = <0>;
|
||||||
|
interrupts = <0x2a 0x2>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
};
|
||||||
|
|
||||||
|
serial1: serial@4600 {
|
||||||
|
cell-index = <1>;
|
||||||
|
device_type = "serial";
|
||||||
|
compatible = "ns16550";
|
||||||
|
reg = <0x4600 0x100>;
|
||||||
|
clock-frequency = <0>;
|
||||||
|
interrupts = <0x1c 0x2>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
};
|
||||||
|
|
||||||
|
mpic: pic@40000 {
|
||||||
|
clock-frequency = <0>;
|
||||||
|
interrupt-controller;
|
||||||
|
#address-cells = <0>;
|
||||||
|
#interrupt-cells = <2>;
|
||||||
|
reg = <0x40000 0x40000>;
|
||||||
|
compatible = "chrp,open-pic";
|
||||||
|
device_type = "open-pic";
|
||||||
|
};
|
||||||
|
|
||||||
|
global-utilities@e0000 {
|
||||||
|
compatible = "fsl,mpc8641-guts";
|
||||||
|
reg = <0xe0000 0x1000>;
|
||||||
|
fsl,has-rstcr;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
pci0: pcie@fef08000 {
|
||||||
|
compatible = "fsl,mpc8641-pcie";
|
||||||
|
device_type = "pci";
|
||||||
|
#interrupt-cells = <1>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
#address-cells = <3>;
|
||||||
|
reg = <0xfef08000 0x1000>;
|
||||||
|
bus-range = <0x0 0xff>;
|
||||||
|
ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
|
||||||
|
0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
|
||||||
|
clock-frequency = <33333333>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <0x18 0x2>;
|
||||||
|
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||||
|
interrupt-map = <
|
||||||
|
0x0000 0x0 0x0 0x1 &mpic 0x0 0x1
|
||||||
|
0x0000 0x0 0x0 0x2 &mpic 0x1 0x1
|
||||||
|
0x0000 0x0 0x0 0x3 &mpic 0x2 0x1
|
||||||
|
0x0000 0x0 0x0 0x4 &mpic 0x3 0x1
|
||||||
|
>;
|
||||||
|
|
||||||
|
pcie@0 {
|
||||||
|
reg = <0 0 0 0 0>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
#address-cells = <3>;
|
||||||
|
device_type = "pci";
|
||||||
|
ranges = <0x02000000 0x0 0x80000000
|
||||||
|
0x02000000 0x0 0x80000000
|
||||||
|
0x0 0x40000000
|
||||||
|
|
||||||
|
0x01000000 0x0 0x00000000
|
||||||
|
0x01000000 0x0 0x00000000
|
||||||
|
0x0 0x00400000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,367 @@
|
||||||
|
/*
|
||||||
|
* GE Fanuc SBC310 Device Tree Source
|
||||||
|
*
|
||||||
|
* Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms of the GNU General Public License as published by the
|
||||||
|
* Free Software Foundation; either version 2 of the License, or (at your
|
||||||
|
* option) any later version.
|
||||||
|
*
|
||||||
|
* Based on: SBS CM6 Device Tree Source
|
||||||
|
* Copyright 2007 SBS Technologies GmbH & Co. KG
|
||||||
|
* And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source)
|
||||||
|
* Copyright 2006 Freescale Semiconductor Inc.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Compiled with dtc -I dts -O dtb -o gef_sbc310.dtb gef_sbc310.dts
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "GEF_SBC310";
|
||||||
|
compatible = "gef,sbc310";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
|
||||||
|
aliases {
|
||||||
|
ethernet0 = &enet0;
|
||||||
|
ethernet1 = &enet1;
|
||||||
|
serial0 = &serial0;
|
||||||
|
serial1 = &serial1;
|
||||||
|
pci0 = &pci0;
|
||||||
|
};
|
||||||
|
|
||||||
|
cpus {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
PowerPC,8641@0 {
|
||||||
|
device_type = "cpu";
|
||||||
|
reg = <0>;
|
||||||
|
d-cache-line-size = <32>; // 32 bytes
|
||||||
|
i-cache-line-size = <32>; // 32 bytes
|
||||||
|
d-cache-size = <32768>; // L1, 32K
|
||||||
|
i-cache-size = <32768>; // L1, 32K
|
||||||
|
timebase-frequency = <0>; // From uboot
|
||||||
|
bus-frequency = <0>; // From uboot
|
||||||
|
clock-frequency = <0>; // From uboot
|
||||||
|
};
|
||||||
|
PowerPC,8641@1 {
|
||||||
|
device_type = "cpu";
|
||||||
|
reg = <1>;
|
||||||
|
d-cache-line-size = <32>; // 32 bytes
|
||||||
|
i-cache-line-size = <32>; // 32 bytes
|
||||||
|
d-cache-size = <32768>; // L1, 32K
|
||||||
|
i-cache-size = <32768>; // L1, 32K
|
||||||
|
timebase-frequency = <0>; // From uboot
|
||||||
|
bus-frequency = <0>; // From uboot
|
||||||
|
clock-frequency = <0>; // From uboot
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
memory {
|
||||||
|
device_type = "memory";
|
||||||
|
reg = <0x0 0x40000000>; // set by uboot
|
||||||
|
};
|
||||||
|
|
||||||
|
localbus@fef05000 {
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
compatible = "fsl,mpc8641-localbus", "simple-bus";
|
||||||
|
reg = <0xfef05000 0x1000>;
|
||||||
|
interrupts = <19 2>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
|
||||||
|
ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
|
||||||
|
1 0 0xe0000000 0x08000000 // Paged Flash 0
|
||||||
|
2 0 0xe8000000 0x08000000 // Paged Flash 1
|
||||||
|
3 0 0xfc100000 0x00020000 // NVRAM
|
||||||
|
4 0 0xfc000000 0x00010000>; // FPGA
|
||||||
|
|
||||||
|
/* flash@0,0 is a mirror of part of the memory in flash@1,0
|
||||||
|
flash@0,0 {
|
||||||
|
compatible = "cfi-flash";
|
||||||
|
reg = <0 0 0x01000000>;
|
||||||
|
bank-width = <2>;
|
||||||
|
device-width = <2>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
partition@0 {
|
||||||
|
label = "firmware";
|
||||||
|
reg = <0x00000000 0x01000000>;
|
||||||
|
read-only;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
*/
|
||||||
|
|
||||||
|
flash@1,0 {
|
||||||
|
compatible = "cfi-flash";
|
||||||
|
reg = <1 0 0x8000000>;
|
||||||
|
bank-width = <2>;
|
||||||
|
device-width = <2>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
partition@0 {
|
||||||
|
label = "user";
|
||||||
|
reg = <0x00000000 0x07800000>;
|
||||||
|
};
|
||||||
|
partition@7800000 {
|
||||||
|
label = "firmware";
|
||||||
|
reg = <0x07800000 0x00800000>;
|
||||||
|
read-only;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
fpga@4,0 {
|
||||||
|
compatible = "gef,fpga-regs";
|
||||||
|
reg = <0x4 0x0 0x40>;
|
||||||
|
};
|
||||||
|
|
||||||
|
wdt@4,2000 {
|
||||||
|
#interrupt-cells = <2>;
|
||||||
|
device_type = "watchdog";
|
||||||
|
compatible = "gef,fpga-wdt";
|
||||||
|
reg = <0x4 0x2000 0x8>;
|
||||||
|
interrupts = <0x1a 0x4>;
|
||||||
|
interrupt-parent = <&gef_pic>;
|
||||||
|
};
|
||||||
|
/*
|
||||||
|
wdt@4,2010 {
|
||||||
|
#interrupt-cells = <2>;
|
||||||
|
device_type = "watchdog";
|
||||||
|
compatible = "gef,fpga-wdt";
|
||||||
|
reg = <0x4 0x2010 0x8>;
|
||||||
|
interrupts = <0x1b 0x4>;
|
||||||
|
interrupt-parent = <&gef_pic>;
|
||||||
|
};
|
||||||
|
*/
|
||||||
|
gef_pic: pic@4,4000 {
|
||||||
|
#interrupt-cells = <1>;
|
||||||
|
interrupt-controller;
|
||||||
|
compatible = "gef,fpga-pic";
|
||||||
|
reg = <0x4 0x4000 0x20>;
|
||||||
|
interrupts = <0x8
|
||||||
|
0x9>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
|
||||||
|
};
|
||||||
|
gef_gpio: gpio@4,8000 {
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
compatible = "gef,sbc310-gpio";
|
||||||
|
reg = <0x4 0x8000 0x24>;
|
||||||
|
gpio-controller;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
soc@fef00000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
#interrupt-cells = <2>;
|
||||||
|
device_type = "soc";
|
||||||
|
compatible = "simple-bus";
|
||||||
|
ranges = <0x0 0xfef00000 0x00100000>;
|
||||||
|
reg = <0xfef00000 0x100000>; // CCSRBAR 1M
|
||||||
|
bus-frequency = <33333333>;
|
||||||
|
|
||||||
|
i2c1: i2c@3000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl-i2c";
|
||||||
|
reg = <0x3000 0x100>;
|
||||||
|
interrupts = <0x2b 0x2>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
dfsrr;
|
||||||
|
|
||||||
|
rtc@51 {
|
||||||
|
compatible = "epson,rx8581";
|
||||||
|
reg = <0x00000051>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
i2c2: i2c@3100 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl-i2c";
|
||||||
|
reg = <0x3100 0x100>;
|
||||||
|
interrupts = <0x2b 0x2>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
dfsrr;
|
||||||
|
|
||||||
|
hwmon@48 {
|
||||||
|
compatible = "national,lm92";
|
||||||
|
reg = <0x48>;
|
||||||
|
};
|
||||||
|
|
||||||
|
hwmon@4c {
|
||||||
|
compatible = "adi,adt7461";
|
||||||
|
reg = <0x4c>;
|
||||||
|
};
|
||||||
|
|
||||||
|
eti@6b {
|
||||||
|
compatible = "dallas,ds1682";
|
||||||
|
reg = <0x6b>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
dma@21300 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
|
||||||
|
reg = <0x21300 0x4>;
|
||||||
|
ranges = <0x0 0x21100 0x200>;
|
||||||
|
cell-index = <0>;
|
||||||
|
dma-channel@0 {
|
||||||
|
compatible = "fsl,mpc8641-dma-channel",
|
||||||
|
"fsl,eloplus-dma-channel";
|
||||||
|
reg = <0x0 0x80>;
|
||||||
|
cell-index = <0>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <20 2>;
|
||||||
|
};
|
||||||
|
dma-channel@80 {
|
||||||
|
compatible = "fsl,mpc8641-dma-channel",
|
||||||
|
"fsl,eloplus-dma-channel";
|
||||||
|
reg = <0x80 0x80>;
|
||||||
|
cell-index = <1>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <21 2>;
|
||||||
|
};
|
||||||
|
dma-channel@100 {
|
||||||
|
compatible = "fsl,mpc8641-dma-channel",
|
||||||
|
"fsl,eloplus-dma-channel";
|
||||||
|
reg = <0x100 0x80>;
|
||||||
|
cell-index = <2>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <22 2>;
|
||||||
|
};
|
||||||
|
dma-channel@180 {
|
||||||
|
compatible = "fsl,mpc8641-dma-channel",
|
||||||
|
"fsl,eloplus-dma-channel";
|
||||||
|
reg = <0x180 0x80>;
|
||||||
|
cell-index = <3>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <23 2>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
enet0: ethernet@24000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
device_type = "network";
|
||||||
|
model = "eTSEC";
|
||||||
|
compatible = "gianfar";
|
||||||
|
reg = <0x24000 0x1000>;
|
||||||
|
ranges = <0x0 0x24000 0x1000>;
|
||||||
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
|
interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
phy-handle = <&phy0>;
|
||||||
|
phy-connection-type = "gmii";
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-mdio";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
phy0: ethernet-phy@0 {
|
||||||
|
interrupt-parent = <&gef_pic>;
|
||||||
|
interrupts = <0x9 0x4>;
|
||||||
|
reg = <1>;
|
||||||
|
};
|
||||||
|
phy2: ethernet-phy@2 {
|
||||||
|
interrupt-parent = <&gef_pic>;
|
||||||
|
interrupts = <0x8 0x4>;
|
||||||
|
reg = <3>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
enet1: ethernet@26000 {
|
||||||
|
device_type = "network";
|
||||||
|
model = "eTSEC";
|
||||||
|
compatible = "gianfar";
|
||||||
|
reg = <0x26000 0x1000>;
|
||||||
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
|
interrupts = <0x1f 0x2 0x20 0x2 0x21 0x2>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
phy-handle = <&phy2>;
|
||||||
|
phy-connection-type = "gmii";
|
||||||
|
};
|
||||||
|
|
||||||
|
serial0: serial@4500 {
|
||||||
|
cell-index = <0>;
|
||||||
|
device_type = "serial";
|
||||||
|
compatible = "ns16550";
|
||||||
|
reg = <0x4500 0x100>;
|
||||||
|
clock-frequency = <0>;
|
||||||
|
interrupts = <0x2a 0x2>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
};
|
||||||
|
|
||||||
|
serial1: serial@4600 {
|
||||||
|
cell-index = <1>;
|
||||||
|
device_type = "serial";
|
||||||
|
compatible = "ns16550";
|
||||||
|
reg = <0x4600 0x100>;
|
||||||
|
clock-frequency = <0>;
|
||||||
|
interrupts = <0x1c 0x2>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
};
|
||||||
|
|
||||||
|
mpic: pic@40000 {
|
||||||
|
clock-frequency = <0>;
|
||||||
|
interrupt-controller;
|
||||||
|
#address-cells = <0>;
|
||||||
|
#interrupt-cells = <2>;
|
||||||
|
reg = <0x40000 0x40000>;
|
||||||
|
compatible = "chrp,open-pic";
|
||||||
|
device_type = "open-pic";
|
||||||
|
};
|
||||||
|
|
||||||
|
global-utilities@e0000 {
|
||||||
|
compatible = "fsl,mpc8641-guts";
|
||||||
|
reg = <0xe0000 0x1000>;
|
||||||
|
fsl,has-rstcr;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
pci0: pcie@fef08000 {
|
||||||
|
compatible = "fsl,mpc8641-pcie";
|
||||||
|
device_type = "pci";
|
||||||
|
#interrupt-cells = <1>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
#address-cells = <3>;
|
||||||
|
reg = <0xfef08000 0x1000>;
|
||||||
|
bus-range = <0x0 0xff>;
|
||||||
|
ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
|
||||||
|
0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
|
||||||
|
clock-frequency = <33333333>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <0x18 0x2>;
|
||||||
|
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||||
|
interrupt-map = <
|
||||||
|
0x0000 0x0 0x0 0x1 &mpic 0x0 0x2
|
||||||
|
0x0000 0x0 0x0 0x2 &mpic 0x1 0x2
|
||||||
|
0x0000 0x0 0x0 0x3 &mpic 0x2 0x2
|
||||||
|
0x0000 0x0 0x0 0x4 &mpic 0x3 0x2
|
||||||
|
>;
|
||||||
|
|
||||||
|
pcie@0 {
|
||||||
|
reg = <0 0 0 0 0>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
#address-cells = <3>;
|
||||||
|
device_type = "pci";
|
||||||
|
ranges = <0x02000000 0x0 0x80000000
|
||||||
|
0x02000000 0x0 0x80000000
|
||||||
|
0x0 0x40000000
|
||||||
|
|
||||||
|
0x01000000 0x0 0x00000000
|
||||||
|
0x01000000 0x0 0x00000000
|
||||||
|
0x0 0x00400000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
@ -71,7 +71,7 @@
|
||||||
#address-cells = <2>;
|
#address-cells = <2>;
|
||||||
#size-cells = <1>;
|
#size-cells = <1>;
|
||||||
compatible = "fsl,mpc8641-localbus", "simple-bus";
|
compatible = "fsl,mpc8641-localbus", "simple-bus";
|
||||||
reg = <0xf8005000 0x1000>;
|
reg = <0xfef05000 0x1000>;
|
||||||
interrupts = <19 2>;
|
interrupts = <19 2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
|
|
||||||
|
|
@ -202,34 +202,37 @@
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
mdio@24520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-mdio";
|
|
||||||
reg = <0x24520 0x20>;
|
|
||||||
|
|
||||||
phy0: ethernet-phy@0 {
|
|
||||||
interrupt-parent = <&gef_pic>;
|
|
||||||
interrupts = <0x9 0x4>;
|
|
||||||
reg = <1>;
|
|
||||||
};
|
|
||||||
phy2: ethernet-phy@2 {
|
|
||||||
interrupt-parent = <&gef_pic>;
|
|
||||||
interrupts = <0x8 0x4>;
|
|
||||||
reg = <3>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
enet0: ethernet@24000 {
|
enet0: ethernet@24000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "eTSEC";
|
model = "eTSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x24000 0x1000>;
|
reg = <0x24000 0x1000>;
|
||||||
|
ranges = <0x0 0x24000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
|
interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
phy-handle = <&phy0>;
|
phy-handle = <&phy0>;
|
||||||
phy-connection-type = "gmii";
|
phy-connection-type = "gmii";
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-mdio";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
phy0: ethernet-phy@0 {
|
||||||
|
interrupt-parent = <&gef_pic>;
|
||||||
|
interrupts = <0x9 0x4>;
|
||||||
|
reg = <1>;
|
||||||
|
};
|
||||||
|
phy2: ethernet-phy@2 {
|
||||||
|
interrupt-parent = <&gef_pic>;
|
||||||
|
interrupts = <0x8 0x4>;
|
||||||
|
reg = <3>;
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
enet1: ethernet@26000 {
|
enet1: ethernet@26000 {
|
||||||
|
|
|
||||||
|
|
@ -124,67 +124,72 @@
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
mdio@24520 { /* For TSECs */
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-mdio";
|
|
||||||
reg = <0x24520 0x20>;
|
|
||||||
|
|
||||||
PHY1: ethernet-phy@1 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
reg = <0x1>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
|
|
||||||
PHY2: ethernet-phy@2 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
reg = <0x2>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
|
|
||||||
tbi0: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
mdio@25520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-tbi";
|
|
||||||
reg = <0x25520 0x20>;
|
|
||||||
|
|
||||||
tbi1: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
|
|
||||||
enet0: ethernet@24000 {
|
enet0: ethernet@24000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "TSEC";
|
model = "TSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x24000 0x1000>;
|
reg = <0x24000 0x1000>;
|
||||||
|
ranges = <0x0 0x24000 0x1000>;
|
||||||
/* Mac address filled in by bootwrapper */
|
/* Mac address filled in by bootwrapper */
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
|
interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
tbi-handle = <&tbi0>;
|
tbi-handle = <&tbi0>;
|
||||||
phy-handle = <&PHY1>;
|
phy-handle = <&PHY1>;
|
||||||
|
|
||||||
|
mdio@520 { /* For TSECs */
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-mdio";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
PHY1: ethernet-phy@1 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
reg = <0x1>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
|
||||||
|
PHY2: ethernet-phy@2 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
reg = <0x2>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
|
||||||
|
tbi0: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
enet1: ethernet@25000 {
|
enet1: ethernet@25000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "TSEC";
|
model = "TSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x25000 0x1000>;
|
reg = <0x25000 0x1000>;
|
||||||
|
ranges = <0x0 0x25000 0x1000>;
|
||||||
/* Mac address filled in by bootwrapper */
|
/* Mac address filled in by bootwrapper */
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>;
|
interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
tbi-handle = <&tbi1>;
|
tbi-handle = <&tbi1>;
|
||||||
phy-handle = <&PHY2>;
|
phy-handle = <&PHY2>;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-tbi";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
tbi1: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
mpic: pic@40000 {
|
mpic: pic@40000 {
|
||||||
|
|
|
||||||
|
|
@ -17,6 +17,7 @@
|
||||||
compatible = "fsl,lite5200";
|
compatible = "fsl,lite5200";
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <1>;
|
#size-cells = <1>;
|
||||||
|
interrupt-parent = <&mpc5200_pic>;
|
||||||
|
|
||||||
cpus {
|
cpus {
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
|
|
@ -58,96 +59,74 @@
|
||||||
// 5200 interrupts are encoded into two levels;
|
// 5200 interrupts are encoded into two levels;
|
||||||
interrupt-controller;
|
interrupt-controller;
|
||||||
#interrupt-cells = <3>;
|
#interrupt-cells = <3>;
|
||||||
device_type = "interrupt-controller";
|
|
||||||
compatible = "fsl,mpc5200-pic";
|
compatible = "fsl,mpc5200-pic";
|
||||||
reg = <0x500 0x80>;
|
reg = <0x500 0x80>;
|
||||||
};
|
};
|
||||||
|
|
||||||
timer@600 { // General Purpose Timer
|
timer@600 { // General Purpose Timer
|
||||||
compatible = "fsl,mpc5200-gpt";
|
compatible = "fsl,mpc5200-gpt";
|
||||||
cell-index = <0>;
|
|
||||||
reg = <0x600 0x10>;
|
reg = <0x600 0x10>;
|
||||||
interrupts = <1 9 0>;
|
interrupts = <1 9 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
fsl,has-wdt;
|
fsl,has-wdt;
|
||||||
};
|
};
|
||||||
|
|
||||||
timer@610 { // General Purpose Timer
|
timer@610 { // General Purpose Timer
|
||||||
compatible = "fsl,mpc5200-gpt";
|
compatible = "fsl,mpc5200-gpt";
|
||||||
cell-index = <1>;
|
|
||||||
reg = <0x610 0x10>;
|
reg = <0x610 0x10>;
|
||||||
interrupts = <1 10 0>;
|
interrupts = <1 10 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
timer@620 { // General Purpose Timer
|
timer@620 { // General Purpose Timer
|
||||||
compatible = "fsl,mpc5200-gpt";
|
compatible = "fsl,mpc5200-gpt";
|
||||||
cell-index = <2>;
|
|
||||||
reg = <0x620 0x10>;
|
reg = <0x620 0x10>;
|
||||||
interrupts = <1 11 0>;
|
interrupts = <1 11 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
timer@630 { // General Purpose Timer
|
timer@630 { // General Purpose Timer
|
||||||
compatible = "fsl,mpc5200-gpt";
|
compatible = "fsl,mpc5200-gpt";
|
||||||
cell-index = <3>;
|
|
||||||
reg = <0x630 0x10>;
|
reg = <0x630 0x10>;
|
||||||
interrupts = <1 12 0>;
|
interrupts = <1 12 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
timer@640 { // General Purpose Timer
|
timer@640 { // General Purpose Timer
|
||||||
compatible = "fsl,mpc5200-gpt";
|
compatible = "fsl,mpc5200-gpt";
|
||||||
cell-index = <4>;
|
|
||||||
reg = <0x640 0x10>;
|
reg = <0x640 0x10>;
|
||||||
interrupts = <1 13 0>;
|
interrupts = <1 13 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
timer@650 { // General Purpose Timer
|
timer@650 { // General Purpose Timer
|
||||||
compatible = "fsl,mpc5200-gpt";
|
compatible = "fsl,mpc5200-gpt";
|
||||||
cell-index = <5>;
|
|
||||||
reg = <0x650 0x10>;
|
reg = <0x650 0x10>;
|
||||||
interrupts = <1 14 0>;
|
interrupts = <1 14 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
timer@660 { // General Purpose Timer
|
timer@660 { // General Purpose Timer
|
||||||
compatible = "fsl,mpc5200-gpt";
|
compatible = "fsl,mpc5200-gpt";
|
||||||
cell-index = <6>;
|
|
||||||
reg = <0x660 0x10>;
|
reg = <0x660 0x10>;
|
||||||
interrupts = <1 15 0>;
|
interrupts = <1 15 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
timer@670 { // General Purpose Timer
|
timer@670 { // General Purpose Timer
|
||||||
compatible = "fsl,mpc5200-gpt";
|
compatible = "fsl,mpc5200-gpt";
|
||||||
cell-index = <7>;
|
|
||||||
reg = <0x670 0x10>;
|
reg = <0x670 0x10>;
|
||||||
interrupts = <1 16 0>;
|
interrupts = <1 16 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
rtc@800 { // Real time clock
|
rtc@800 { // Real time clock
|
||||||
compatible = "fsl,mpc5200-rtc";
|
compatible = "fsl,mpc5200-rtc";
|
||||||
reg = <0x800 0x100>;
|
reg = <0x800 0x100>;
|
||||||
interrupts = <1 5 0 1 6 0>;
|
interrupts = <1 5 0 1 6 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
can@900 {
|
can@900 {
|
||||||
compatible = "fsl,mpc5200-mscan";
|
compatible = "fsl,mpc5200-mscan";
|
||||||
cell-index = <0>;
|
|
||||||
interrupts = <2 17 0>;
|
interrupts = <2 17 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
reg = <0x900 0x80>;
|
reg = <0x900 0x80>;
|
||||||
};
|
};
|
||||||
|
|
||||||
can@980 {
|
can@980 {
|
||||||
compatible = "fsl,mpc5200-mscan";
|
compatible = "fsl,mpc5200-mscan";
|
||||||
cell-index = <1>;
|
|
||||||
interrupts = <2 18 0>;
|
interrupts = <2 18 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
reg = <0x980 0x80>;
|
reg = <0x980 0x80>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -155,39 +134,33 @@
|
||||||
compatible = "fsl,mpc5200-gpio";
|
compatible = "fsl,mpc5200-gpio";
|
||||||
reg = <0xb00 0x40>;
|
reg = <0xb00 0x40>;
|
||||||
interrupts = <1 7 0>;
|
interrupts = <1 7 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
gpio@c00 {
|
gpio@c00 {
|
||||||
compatible = "fsl,mpc5200-gpio-wkup";
|
compatible = "fsl,mpc5200-gpio-wkup";
|
||||||
reg = <0xc00 0x40>;
|
reg = <0xc00 0x40>;
|
||||||
interrupts = <1 8 0 0 3 0>;
|
interrupts = <1 8 0 0 3 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
spi@f00 {
|
spi@f00 {
|
||||||
compatible = "fsl,mpc5200-spi";
|
compatible = "fsl,mpc5200-spi";
|
||||||
reg = <0xf00 0x20>;
|
reg = <0xf00 0x20>;
|
||||||
interrupts = <2 13 0 2 14 0>;
|
interrupts = <2 13 0 2 14 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
usb@1000 {
|
usb@1000 {
|
||||||
compatible = "fsl,mpc5200-ohci","ohci-be";
|
compatible = "fsl,mpc5200-ohci","ohci-be";
|
||||||
reg = <0x1000 0xff>;
|
reg = <0x1000 0xff>;
|
||||||
interrupts = <2 6 0>;
|
interrupts = <2 6 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
dma-controller@1200 {
|
dma-controller@1200 {
|
||||||
device_type = "dma-controller";
|
|
||||||
compatible = "fsl,mpc5200-bestcomm";
|
compatible = "fsl,mpc5200-bestcomm";
|
||||||
reg = <0x1200 0x80>;
|
reg = <0x1200 0x80>;
|
||||||
interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
|
interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
|
||||||
3 4 0 3 5 0 3 6 0 3 7 0
|
3 4 0 3 5 0 3 6 0 3 7 0
|
||||||
3 8 0 3 9 0 3 10 0 3 11 0
|
3 8 0 3 9 0 3 10 0 3 11 0
|
||||||
3 12 0 3 13 0 3 14 0 3 15 0>;
|
3 12 0 3 13 0 3 14 0 3 15 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
xlb@1f00 {
|
xlb@1f00 {
|
||||||
|
|
@ -196,13 +169,10 @@
|
||||||
};
|
};
|
||||||
|
|
||||||
serial@2000 { // PSC1
|
serial@2000 { // PSC1
|
||||||
device_type = "serial";
|
|
||||||
compatible = "fsl,mpc5200-psc-uart";
|
compatible = "fsl,mpc5200-psc-uart";
|
||||||
port-number = <0>; // Logical port assignment
|
|
||||||
cell-index = <0>;
|
cell-index = <0>;
|
||||||
reg = <0x2000 0x100>;
|
reg = <0x2000 0x100>;
|
||||||
interrupts = <2 1 0>;
|
interrupts = <2 1 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
// PSC2 in ac97 mode example
|
// PSC2 in ac97 mode example
|
||||||
|
|
@ -211,7 +181,6 @@
|
||||||
// cell-index = <1>;
|
// cell-index = <1>;
|
||||||
// reg = <0x2200 0x100>;
|
// reg = <0x2200 0x100>;
|
||||||
// interrupts = <2 2 0>;
|
// interrupts = <2 2 0>;
|
||||||
// interrupt-parent = <&mpc5200_pic>;
|
|
||||||
//};
|
//};
|
||||||
|
|
||||||
// PSC3 in CODEC mode example
|
// PSC3 in CODEC mode example
|
||||||
|
|
@ -220,27 +189,22 @@
|
||||||
// cell-index = <2>;
|
// cell-index = <2>;
|
||||||
// reg = <0x2400 0x100>;
|
// reg = <0x2400 0x100>;
|
||||||
// interrupts = <2 3 0>;
|
// interrupts = <2 3 0>;
|
||||||
// interrupt-parent = <&mpc5200_pic>;
|
|
||||||
//};
|
//};
|
||||||
|
|
||||||
// PSC4 in uart mode example
|
// PSC4 in uart mode example
|
||||||
//serial@2600 { // PSC4
|
//serial@2600 { // PSC4
|
||||||
// device_type = "serial";
|
|
||||||
// compatible = "fsl,mpc5200-psc-uart";
|
// compatible = "fsl,mpc5200-psc-uart";
|
||||||
// cell-index = <3>;
|
// cell-index = <3>;
|
||||||
// reg = <0x2600 0x100>;
|
// reg = <0x2600 0x100>;
|
||||||
// interrupts = <2 11 0>;
|
// interrupts = <2 11 0>;
|
||||||
// interrupt-parent = <&mpc5200_pic>;
|
|
||||||
//};
|
//};
|
||||||
|
|
||||||
// PSC5 in uart mode example
|
// PSC5 in uart mode example
|
||||||
//serial@2800 { // PSC5
|
//serial@2800 { // PSC5
|
||||||
// device_type = "serial";
|
|
||||||
// compatible = "fsl,mpc5200-psc-uart";
|
// compatible = "fsl,mpc5200-psc-uart";
|
||||||
// cell-index = <4>;
|
// cell-index = <4>;
|
||||||
// reg = <0x2800 0x100>;
|
// reg = <0x2800 0x100>;
|
||||||
// interrupts = <2 12 0>;
|
// interrupts = <2 12 0>;
|
||||||
// interrupt-parent = <&mpc5200_pic>;
|
|
||||||
//};
|
//};
|
||||||
|
|
||||||
// PSC6 in spi mode example
|
// PSC6 in spi mode example
|
||||||
|
|
@ -249,16 +213,13 @@
|
||||||
// cell-index = <5>;
|
// cell-index = <5>;
|
||||||
// reg = <0x2c00 0x100>;
|
// reg = <0x2c00 0x100>;
|
||||||
// interrupts = <2 4 0>;
|
// interrupts = <2 4 0>;
|
||||||
// interrupt-parent = <&mpc5200_pic>;
|
|
||||||
//};
|
//};
|
||||||
|
|
||||||
ethernet@3000 {
|
ethernet@3000 {
|
||||||
device_type = "network";
|
|
||||||
compatible = "fsl,mpc5200-fec";
|
compatible = "fsl,mpc5200-fec";
|
||||||
reg = <0x3000 0x400>;
|
reg = <0x3000 0x400>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <2 5 0>;
|
interrupts = <2 5 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
phy-handle = <&phy0>;
|
phy-handle = <&phy0>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -268,30 +229,24 @@
|
||||||
compatible = "fsl,mpc5200-mdio";
|
compatible = "fsl,mpc5200-mdio";
|
||||||
reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
|
reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
|
||||||
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
|
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
|
|
||||||
phy0: ethernet-phy@1 {
|
phy0: ethernet-phy@1 {
|
||||||
device_type = "ethernet-phy";
|
|
||||||
reg = <1>;
|
reg = <1>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
ata@3a00 {
|
ata@3a00 {
|
||||||
device_type = "ata";
|
|
||||||
compatible = "fsl,mpc5200-ata";
|
compatible = "fsl,mpc5200-ata";
|
||||||
reg = <0x3a00 0x100>;
|
reg = <0x3a00 0x100>;
|
||||||
interrupts = <2 7 0>;
|
interrupts = <2 7 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
i2c@3d00 {
|
i2c@3d00 {
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <0>;
|
#size-cells = <0>;
|
||||||
compatible = "fsl,mpc5200-i2c","fsl-i2c";
|
compatible = "fsl,mpc5200-i2c","fsl-i2c";
|
||||||
cell-index = <0>;
|
|
||||||
reg = <0x3d00 0x40>;
|
reg = <0x3d00 0x40>;
|
||||||
interrupts = <2 15 0>;
|
interrupts = <2 15 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
fsl5200-clocking;
|
fsl5200-clocking;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -299,14 +254,12 @@
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <0>;
|
#size-cells = <0>;
|
||||||
compatible = "fsl,mpc5200-i2c","fsl-i2c";
|
compatible = "fsl,mpc5200-i2c","fsl-i2c";
|
||||||
cell-index = <1>;
|
|
||||||
reg = <0x3d40 0x40>;
|
reg = <0x3d40 0x40>;
|
||||||
interrupts = <2 16 0>;
|
interrupts = <2 16 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
fsl5200-clocking;
|
fsl5200-clocking;
|
||||||
};
|
};
|
||||||
sram@8000 {
|
sram@8000 {
|
||||||
compatible = "fsl,mpc5200-sram","sram";
|
compatible = "fsl,mpc5200-sram";
|
||||||
reg = <0x8000 0x4000>;
|
reg = <0x8000 0x4000>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
@ -325,7 +278,6 @@
|
||||||
0xc000 0 0 4 &mpc5200_pic 0 0 3>;
|
0xc000 0 0 4 &mpc5200_pic 0 0 3>;
|
||||||
clock-frequency = <0>; // From boot loader
|
clock-frequency = <0>; // From boot loader
|
||||||
interrupts = <2 8 0 2 9 0 2 10 0>;
|
interrupts = <2 8 0 2 9 0 2 10 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
bus-range = <0 0>;
|
bus-range = <0 0>;
|
||||||
ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
|
ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
|
||||||
0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
|
0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
|
||||||
|
|
|
||||||
|
|
@ -17,6 +17,7 @@
|
||||||
compatible = "fsl,lite5200b";
|
compatible = "fsl,lite5200b";
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <1>;
|
#size-cells = <1>;
|
||||||
|
interrupt-parent = <&mpc5200_pic>;
|
||||||
|
|
||||||
cpus {
|
cpus {
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
|
|
@ -58,136 +59,112 @@
|
||||||
// 5200 interrupts are encoded into two levels;
|
// 5200 interrupts are encoded into two levels;
|
||||||
interrupt-controller;
|
interrupt-controller;
|
||||||
#interrupt-cells = <3>;
|
#interrupt-cells = <3>;
|
||||||
device_type = "interrupt-controller";
|
|
||||||
compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
|
compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
|
||||||
reg = <0x500 0x80>;
|
reg = <0x500 0x80>;
|
||||||
};
|
};
|
||||||
|
|
||||||
timer@600 { // General Purpose Timer
|
timer@600 { // General Purpose Timer
|
||||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||||
cell-index = <0>;
|
|
||||||
reg = <0x600 0x10>;
|
reg = <0x600 0x10>;
|
||||||
interrupts = <1 9 0>;
|
interrupts = <1 9 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
fsl,has-wdt;
|
fsl,has-wdt;
|
||||||
};
|
};
|
||||||
|
|
||||||
timer@610 { // General Purpose Timer
|
timer@610 { // General Purpose Timer
|
||||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||||
cell-index = <1>;
|
|
||||||
reg = <0x610 0x10>;
|
reg = <0x610 0x10>;
|
||||||
interrupts = <1 10 0>;
|
interrupts = <1 10 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
timer@620 { // General Purpose Timer
|
timer@620 { // General Purpose Timer
|
||||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||||
cell-index = <2>;
|
|
||||||
reg = <0x620 0x10>;
|
reg = <0x620 0x10>;
|
||||||
interrupts = <1 11 0>;
|
interrupts = <1 11 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
timer@630 { // General Purpose Timer
|
timer@630 { // General Purpose Timer
|
||||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||||
cell-index = <3>;
|
|
||||||
reg = <0x630 0x10>;
|
reg = <0x630 0x10>;
|
||||||
interrupts = <1 12 0>;
|
interrupts = <1 12 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
timer@640 { // General Purpose Timer
|
timer@640 { // General Purpose Timer
|
||||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||||
cell-index = <4>;
|
|
||||||
reg = <0x640 0x10>;
|
reg = <0x640 0x10>;
|
||||||
interrupts = <1 13 0>;
|
interrupts = <1 13 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
timer@650 { // General Purpose Timer
|
timer@650 { // General Purpose Timer
|
||||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||||
cell-index = <5>;
|
|
||||||
reg = <0x650 0x10>;
|
reg = <0x650 0x10>;
|
||||||
interrupts = <1 14 0>;
|
interrupts = <1 14 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
timer@660 { // General Purpose Timer
|
timer@660 { // General Purpose Timer
|
||||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||||
cell-index = <6>;
|
|
||||||
reg = <0x660 0x10>;
|
reg = <0x660 0x10>;
|
||||||
interrupts = <1 15 0>;
|
interrupts = <1 15 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
timer@670 { // General Purpose Timer
|
timer@670 { // General Purpose Timer
|
||||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||||
cell-index = <7>;
|
|
||||||
reg = <0x670 0x10>;
|
reg = <0x670 0x10>;
|
||||||
interrupts = <1 16 0>;
|
interrupts = <1 16 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
rtc@800 { // Real time clock
|
rtc@800 { // Real time clock
|
||||||
compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
|
compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
|
||||||
reg = <0x800 0x100>;
|
reg = <0x800 0x100>;
|
||||||
interrupts = <1 5 0 1 6 0>;
|
interrupts = <1 5 0 1 6 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
can@900 {
|
can@900 {
|
||||||
compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
|
compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
|
||||||
cell-index = <0>;
|
|
||||||
interrupts = <2 17 0>;
|
interrupts = <2 17 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
reg = <0x900 0x80>;
|
reg = <0x900 0x80>;
|
||||||
};
|
};
|
||||||
|
|
||||||
can@980 {
|
can@980 {
|
||||||
compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
|
compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
|
||||||
cell-index = <1>;
|
|
||||||
interrupts = <2 18 0>;
|
interrupts = <2 18 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
reg = <0x980 0x80>;
|
reg = <0x980 0x80>;
|
||||||
};
|
};
|
||||||
|
|
||||||
gpio@b00 {
|
gpio_simple: gpio@b00 {
|
||||||
compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
|
compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
|
||||||
reg = <0xb00 0x40>;
|
reg = <0xb00 0x40>;
|
||||||
interrupts = <1 7 0>;
|
interrupts = <1 7 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
gpio-controller;
|
||||||
|
#gpio-cells = <2>;
|
||||||
};
|
};
|
||||||
|
|
||||||
gpio@c00 {
|
gpio_wkup: gpio@c00 {
|
||||||
compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
|
compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
|
||||||
reg = <0xc00 0x40>;
|
reg = <0xc00 0x40>;
|
||||||
interrupts = <1 8 0 0 3 0>;
|
interrupts = <1 8 0 0 3 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
gpio-controller;
|
||||||
|
#gpio-cells = <2>;
|
||||||
};
|
};
|
||||||
|
|
||||||
spi@f00 {
|
spi@f00 {
|
||||||
compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
|
compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
|
||||||
reg = <0xf00 0x20>;
|
reg = <0xf00 0x20>;
|
||||||
interrupts = <2 13 0 2 14 0>;
|
interrupts = <2 13 0 2 14 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
usb@1000 {
|
usb@1000 {
|
||||||
compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
|
compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
|
||||||
reg = <0x1000 0xff>;
|
reg = <0x1000 0xff>;
|
||||||
interrupts = <2 6 0>;
|
interrupts = <2 6 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
dma-controller@1200 {
|
dma-controller@1200 {
|
||||||
device_type = "dma-controller";
|
|
||||||
compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
|
compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
|
||||||
reg = <0x1200 0x80>;
|
reg = <0x1200 0x80>;
|
||||||
interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
|
interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
|
||||||
3 4 0 3 5 0 3 6 0 3 7 0
|
3 4 0 3 5 0 3 6 0 3 7 0
|
||||||
3 8 0 3 9 0 3 10 0 3 11 0
|
3 8 0 3 9 0 3 10 0 3 11 0
|
||||||
3 12 0 3 13 0 3 14 0 3 15 0>;
|
3 12 0 3 13 0 3 14 0 3 15 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
xlb@1f00 {
|
xlb@1f00 {
|
||||||
|
|
@ -196,13 +173,10 @@
|
||||||
};
|
};
|
||||||
|
|
||||||
serial@2000 { // PSC1
|
serial@2000 { // PSC1
|
||||||
device_type = "serial";
|
|
||||||
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||||
port-number = <0>; // Logical port assignment
|
|
||||||
cell-index = <0>;
|
cell-index = <0>;
|
||||||
reg = <0x2000 0x100>;
|
reg = <0x2000 0x100>;
|
||||||
interrupts = <2 1 0>;
|
interrupts = <2 1 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
// PSC2 in ac97 mode example
|
// PSC2 in ac97 mode example
|
||||||
|
|
@ -211,7 +185,6 @@
|
||||||
// cell-index = <1>;
|
// cell-index = <1>;
|
||||||
// reg = <0x2200 0x100>;
|
// reg = <0x2200 0x100>;
|
||||||
// interrupts = <2 2 0>;
|
// interrupts = <2 2 0>;
|
||||||
// interrupt-parent = <&mpc5200_pic>;
|
|
||||||
//};
|
//};
|
||||||
|
|
||||||
// PSC3 in CODEC mode example
|
// PSC3 in CODEC mode example
|
||||||
|
|
@ -220,27 +193,22 @@
|
||||||
// cell-index = <2>;
|
// cell-index = <2>;
|
||||||
// reg = <0x2400 0x100>;
|
// reg = <0x2400 0x100>;
|
||||||
// interrupts = <2 3 0>;
|
// interrupts = <2 3 0>;
|
||||||
// interrupt-parent = <&mpc5200_pic>;
|
|
||||||
//};
|
//};
|
||||||
|
|
||||||
// PSC4 in uart mode example
|
// PSC4 in uart mode example
|
||||||
//serial@2600 { // PSC4
|
//serial@2600 { // PSC4
|
||||||
// device_type = "serial";
|
|
||||||
// compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
// compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||||
// cell-index = <3>;
|
// cell-index = <3>;
|
||||||
// reg = <0x2600 0x100>;
|
// reg = <0x2600 0x100>;
|
||||||
// interrupts = <2 11 0>;
|
// interrupts = <2 11 0>;
|
||||||
// interrupt-parent = <&mpc5200_pic>;
|
|
||||||
//};
|
//};
|
||||||
|
|
||||||
// PSC5 in uart mode example
|
// PSC5 in uart mode example
|
||||||
//serial@2800 { // PSC5
|
//serial@2800 { // PSC5
|
||||||
// device_type = "serial";
|
|
||||||
// compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
// compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||||
// cell-index = <4>;
|
// cell-index = <4>;
|
||||||
// reg = <0x2800 0x100>;
|
// reg = <0x2800 0x100>;
|
||||||
// interrupts = <2 12 0>;
|
// interrupts = <2 12 0>;
|
||||||
// interrupt-parent = <&mpc5200_pic>;
|
|
||||||
//};
|
//};
|
||||||
|
|
||||||
// PSC6 in spi mode example
|
// PSC6 in spi mode example
|
||||||
|
|
@ -249,49 +217,40 @@
|
||||||
// cell-index = <5>;
|
// cell-index = <5>;
|
||||||
// reg = <0x2c00 0x100>;
|
// reg = <0x2c00 0x100>;
|
||||||
// interrupts = <2 4 0>;
|
// interrupts = <2 4 0>;
|
||||||
// interrupt-parent = <&mpc5200_pic>;
|
|
||||||
//};
|
//};
|
||||||
|
|
||||||
ethernet@3000 {
|
ethernet@3000 {
|
||||||
device_type = "network";
|
|
||||||
compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
|
compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
|
||||||
reg = <0x3000 0x400>;
|
reg = <0x3000 0x400>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <2 5 0>;
|
interrupts = <2 5 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
phy-handle = <&phy0>;
|
phy-handle = <&phy0>;
|
||||||
};
|
};
|
||||||
|
|
||||||
mdio@3000 {
|
mdio@3000 {
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <0>;
|
#size-cells = <0>;
|
||||||
compatible = "fsl,mpc5200b-mdio", "fsl,mpc5200-mdio";
|
compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
|
||||||
reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
|
reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
|
||||||
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
|
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
|
|
||||||
phy0: ethernet-phy@0 {
|
phy0: ethernet-phy@0 {
|
||||||
device_type = "ethernet-phy";
|
|
||||||
reg = <0>;
|
reg = <0>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
ata@3a00 {
|
ata@3a00 {
|
||||||
device_type = "ata";
|
|
||||||
compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
|
compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
|
||||||
reg = <0x3a00 0x100>;
|
reg = <0x3a00 0x100>;
|
||||||
interrupts = <2 7 0>;
|
interrupts = <2 7 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
i2c@3d00 {
|
i2c@3d00 {
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <0>;
|
#size-cells = <0>;
|
||||||
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
|
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
|
||||||
cell-index = <0>;
|
|
||||||
reg = <0x3d00 0x40>;
|
reg = <0x3d00 0x40>;
|
||||||
interrupts = <2 15 0>;
|
interrupts = <2 15 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
fsl5200-clocking;
|
fsl5200-clocking;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -299,14 +258,13 @@
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <0>;
|
#size-cells = <0>;
|
||||||
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
|
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
|
||||||
cell-index = <1>;
|
|
||||||
reg = <0x3d40 0x40>;
|
reg = <0x3d40 0x40>;
|
||||||
interrupts = <2 16 0>;
|
interrupts = <2 16 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
fsl5200-clocking;
|
fsl5200-clocking;
|
||||||
};
|
};
|
||||||
|
|
||||||
sram@8000 {
|
sram@8000 {
|
||||||
compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram","sram";
|
compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
|
||||||
reg = <0x8000 0x4000>;
|
reg = <0x8000 0x4000>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
@ -330,7 +288,6 @@
|
||||||
0xc800 0 0 4 &mpc5200_pic 0 0 3>;
|
0xc800 0 0 4 &mpc5200_pic 0 0 3>;
|
||||||
clock-frequency = <0>; // From boot loader
|
clock-frequency = <0>; // From boot loader
|
||||||
interrupts = <2 8 0 2 9 0 2 10 0>;
|
interrupts = <2 8 0 2 9 0 2 10 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
bus-range = <0 0>;
|
bus-range = <0 0>;
|
||||||
ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
|
ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
|
||||||
0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
|
0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,318 @@
|
||||||
|
/*
|
||||||
|
* Freescale Media5200 board Device Tree Source
|
||||||
|
*
|
||||||
|
* Copyright 2009 Secret Lab Technologies Ltd.
|
||||||
|
* Grant Likely <grant.likely@secretlab.ca>
|
||||||
|
* Steven Cavanagh <scavanagh@secretlab.ca>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms of the GNU General Public License as published by the
|
||||||
|
* Free Software Foundation; either version 2 of the License, or (at your
|
||||||
|
* option) any later version.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "fsl,media5200";
|
||||||
|
compatible = "fsl,media5200";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
interrupt-parent = <&mpc5200_pic>;
|
||||||
|
|
||||||
|
aliases {
|
||||||
|
console = &console;
|
||||||
|
ethernet0 = ð0;
|
||||||
|
};
|
||||||
|
|
||||||
|
chosen {
|
||||||
|
linux,stdout-path = &console;
|
||||||
|
};
|
||||||
|
|
||||||
|
cpus {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
PowerPC,5200@0 {
|
||||||
|
device_type = "cpu";
|
||||||
|
reg = <0>;
|
||||||
|
d-cache-line-size = <32>;
|
||||||
|
i-cache-line-size = <32>;
|
||||||
|
d-cache-size = <0x4000>; // L1, 16K
|
||||||
|
i-cache-size = <0x4000>; // L1, 16K
|
||||||
|
timebase-frequency = <33000000>; // 33 MHz, these were configured by U-Boot
|
||||||
|
bus-frequency = <132000000>; // 132 MHz
|
||||||
|
clock-frequency = <396000000>; // 396 MHz
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
memory {
|
||||||
|
device_type = "memory";
|
||||||
|
reg = <0x00000000 0x08000000>; // 128MB RAM
|
||||||
|
};
|
||||||
|
|
||||||
|
soc@f0000000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
compatible = "fsl,mpc5200b-immr";
|
||||||
|
ranges = <0 0xf0000000 0x0000c000>;
|
||||||
|
reg = <0xf0000000 0x00000100>;
|
||||||
|
bus-frequency = <132000000>;// 132 MHz
|
||||||
|
system-frequency = <0>; // from bootloader
|
||||||
|
|
||||||
|
cdm@200 {
|
||||||
|
compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
|
||||||
|
reg = <0x200 0x38>;
|
||||||
|
};
|
||||||
|
|
||||||
|
mpc5200_pic: interrupt-controller@500 {
|
||||||
|
// 5200 interrupts are encoded into two levels;
|
||||||
|
interrupt-controller;
|
||||||
|
#interrupt-cells = <3>;
|
||||||
|
compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
|
||||||
|
reg = <0x500 0x80>;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer@600 { // General Purpose Timer
|
||||||
|
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||||
|
reg = <0x600 0x10>;
|
||||||
|
interrupts = <1 9 0>;
|
||||||
|
fsl,has-wdt;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer@610 { // General Purpose Timer
|
||||||
|
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||||
|
reg = <0x610 0x10>;
|
||||||
|
interrupts = <1 10 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer@620 { // General Purpose Timer
|
||||||
|
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||||
|
reg = <0x620 0x10>;
|
||||||
|
interrupts = <1 11 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer@630 { // General Purpose Timer
|
||||||
|
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||||
|
reg = <0x630 0x10>;
|
||||||
|
interrupts = <1 12 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer@640 { // General Purpose Timer
|
||||||
|
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||||
|
reg = <0x640 0x10>;
|
||||||
|
interrupts = <1 13 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer@650 { // General Purpose Timer
|
||||||
|
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||||
|
reg = <0x650 0x10>;
|
||||||
|
interrupts = <1 14 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer@660 { // General Purpose Timer
|
||||||
|
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||||
|
reg = <0x660 0x10>;
|
||||||
|
interrupts = <1 15 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer@670 { // General Purpose Timer
|
||||||
|
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||||
|
reg = <0x670 0x10>;
|
||||||
|
interrupts = <1 16 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
rtc@800 { // Real time clock
|
||||||
|
compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
|
||||||
|
reg = <0x800 0x100>;
|
||||||
|
interrupts = <1 5 0 1 6 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
can@900 {
|
||||||
|
compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
|
||||||
|
interrupts = <2 17 0>;
|
||||||
|
reg = <0x900 0x80>;
|
||||||
|
};
|
||||||
|
|
||||||
|
can@980 {
|
||||||
|
compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
|
||||||
|
interrupts = <2 18 0>;
|
||||||
|
reg = <0x980 0x80>;
|
||||||
|
};
|
||||||
|
|
||||||
|
gpio_simple: gpio@b00 {
|
||||||
|
compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
|
||||||
|
reg = <0xb00 0x40>;
|
||||||
|
interrupts = <1 7 0>;
|
||||||
|
gpio-controller;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
gpio_wkup: gpio@c00 {
|
||||||
|
compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
|
||||||
|
reg = <0xc00 0x40>;
|
||||||
|
interrupts = <1 8 0 0 3 0>;
|
||||||
|
gpio-controller;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
spi@f00 {
|
||||||
|
compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
|
||||||
|
reg = <0xf00 0x20>;
|
||||||
|
interrupts = <2 13 0 2 14 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
usb@1000 {
|
||||||
|
compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
|
||||||
|
reg = <0x1000 0x100>;
|
||||||
|
interrupts = <2 6 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
dma-controller@1200 {
|
||||||
|
compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
|
||||||
|
reg = <0x1200 0x80>;
|
||||||
|
interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
|
||||||
|
3 4 0 3 5 0 3 6 0 3 7 0
|
||||||
|
3 8 0 3 9 0 3 10 0 3 11 0
|
||||||
|
3 12 0 3 13 0 3 14 0 3 15 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
xlb@1f00 {
|
||||||
|
compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
|
||||||
|
reg = <0x1f00 0x100>;
|
||||||
|
};
|
||||||
|
|
||||||
|
// PSC6 in uart mode
|
||||||
|
console: serial@2c00 { // PSC6
|
||||||
|
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||||
|
cell-index = <5>;
|
||||||
|
port-number = <0>; // Logical port assignment
|
||||||
|
reg = <0x2c00 0x100>;
|
||||||
|
interrupts = <2 4 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
eth0: ethernet@3000 {
|
||||||
|
compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
|
||||||
|
reg = <0x3000 0x400>;
|
||||||
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
|
interrupts = <2 5 0>;
|
||||||
|
phy-handle = <&phy0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
mdio@3000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
|
||||||
|
reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
|
||||||
|
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
|
||||||
|
|
||||||
|
phy0: ethernet-phy@0 {
|
||||||
|
reg = <0>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
ata@3a00 {
|
||||||
|
compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
|
||||||
|
reg = <0x3a00 0x100>;
|
||||||
|
interrupts = <2 7 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
i2c@3d00 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
|
||||||
|
reg = <0x3d00 0x40>;
|
||||||
|
interrupts = <2 15 0>;
|
||||||
|
fsl5200-clocking;
|
||||||
|
};
|
||||||
|
|
||||||
|
i2c@3d40 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
|
||||||
|
reg = <0x3d40 0x40>;
|
||||||
|
interrupts = <2 16 0>;
|
||||||
|
fsl5200-clocking;
|
||||||
|
};
|
||||||
|
|
||||||
|
sram@8000 {
|
||||||
|
compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
|
||||||
|
reg = <0x8000 0x4000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
pci@f0000d00 {
|
||||||
|
#interrupt-cells = <1>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
#address-cells = <3>;
|
||||||
|
device_type = "pci";
|
||||||
|
compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
|
||||||
|
reg = <0xf0000d00 0x100>;
|
||||||
|
interrupt-map-mask = <0xf800 0 0 7>;
|
||||||
|
interrupt-map = <0xc000 0 0 1 &media5200_fpga 0 2 // 1st slot
|
||||||
|
0xc000 0 0 2 &media5200_fpga 0 3
|
||||||
|
0xc000 0 0 3 &media5200_fpga 0 4
|
||||||
|
0xc000 0 0 4 &media5200_fpga 0 5
|
||||||
|
|
||||||
|
0xc800 0 0 1 &media5200_fpga 0 3 // 2nd slot
|
||||||
|
0xc800 0 0 2 &media5200_fpga 0 4
|
||||||
|
0xc800 0 0 3 &media5200_fpga 0 5
|
||||||
|
0xc800 0 0 4 &media5200_fpga 0 2
|
||||||
|
|
||||||
|
0xd000 0 0 1 &media5200_fpga 0 4 // miniPCI
|
||||||
|
0xd000 0 0 2 &media5200_fpga 0 5
|
||||||
|
|
||||||
|
0xe000 0 0 1 &media5200_fpga 0 5 // CoralIP
|
||||||
|
>;
|
||||||
|
clock-frequency = <0>; // From boot loader
|
||||||
|
interrupts = <2 8 0 2 9 0 2 10 0>;
|
||||||
|
interrupt-parent = <&mpc5200_pic>;
|
||||||
|
bus-range = <0 0>;
|
||||||
|
ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
|
||||||
|
0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
|
||||||
|
0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
localbus {
|
||||||
|
compatible = "fsl,mpc5200b-lpb","simple-bus";
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
|
||||||
|
ranges = < 0 0 0xfc000000 0x02000000
|
||||||
|
1 0 0xfe000000 0x02000000
|
||||||
|
2 0 0xf0010000 0x00010000
|
||||||
|
3 0 0xf0020000 0x00010000 >;
|
||||||
|
|
||||||
|
flash@0,0 {
|
||||||
|
compatible = "amd,am29lv28ml", "cfi-flash";
|
||||||
|
reg = <0 0x0 0x2000000>; // 32 MB
|
||||||
|
bank-width = <4>; // Width in bytes of the flash bank
|
||||||
|
device-width = <2>; // Two devices on each bank
|
||||||
|
};
|
||||||
|
|
||||||
|
flash@1,0 {
|
||||||
|
compatible = "amd,am29lv28ml", "cfi-flash";
|
||||||
|
reg = <1 0 0x2000000>; // 32 MB
|
||||||
|
bank-width = <4>; // Width in bytes of the flash bank
|
||||||
|
device-width = <2>; // Two devices on each bank
|
||||||
|
};
|
||||||
|
|
||||||
|
media5200_fpga: fpga@2,0 {
|
||||||
|
compatible = "fsl,media5200-fpga";
|
||||||
|
interrupt-controller;
|
||||||
|
#interrupt-cells = <2>; // 0:bank 1:id; no type field
|
||||||
|
reg = <2 0 0x10000>;
|
||||||
|
|
||||||
|
interrupt-parent = <&mpc5200_pic>;
|
||||||
|
interrupts = <0 0 3 // IRQ bank 0
|
||||||
|
1 1 3>; // IRQ bank 1
|
||||||
|
};
|
||||||
|
|
||||||
|
uart@3,0 {
|
||||||
|
compatible = "ti,tl16c752bpt";
|
||||||
|
reg = <3 0 0x10000>;
|
||||||
|
interrupt-parent = <&media5200_fpga>;
|
||||||
|
interrupts = <0 0 0 1>; // 2 irqs
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
@ -17,6 +17,7 @@
|
||||||
compatible = "promess,motionpro";
|
compatible = "promess,motionpro";
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <1>;
|
#size-cells = <1>;
|
||||||
|
interrupt-parent = <&mpc5200_pic>;
|
||||||
|
|
||||||
cpus {
|
cpus {
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
|
|
@ -66,7 +67,6 @@
|
||||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||||
reg = <0x600 0x10>;
|
reg = <0x600 0x10>;
|
||||||
interrupts = <1 9 0>;
|
interrupts = <1 9 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
fsl,has-wdt;
|
fsl,has-wdt;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -74,35 +74,30 @@
|
||||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||||
reg = <0x610 0x10>;
|
reg = <0x610 0x10>;
|
||||||
interrupts = <1 10 0>;
|
interrupts = <1 10 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
timer@620 { // General Purpose Timer
|
timer@620 { // General Purpose Timer
|
||||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||||
reg = <0x620 0x10>;
|
reg = <0x620 0x10>;
|
||||||
interrupts = <1 11 0>;
|
interrupts = <1 11 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
timer@630 { // General Purpose Timer
|
timer@630 { // General Purpose Timer
|
||||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||||
reg = <0x630 0x10>;
|
reg = <0x630 0x10>;
|
||||||
interrupts = <1 12 0>;
|
interrupts = <1 12 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
timer@640 { // General Purpose Timer
|
timer@640 { // General Purpose Timer
|
||||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||||
reg = <0x640 0x10>;
|
reg = <0x640 0x10>;
|
||||||
interrupts = <1 13 0>;
|
interrupts = <1 13 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
timer@650 { // General Purpose Timer
|
timer@650 { // General Purpose Timer
|
||||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||||
reg = <0x650 0x10>;
|
reg = <0x650 0x10>;
|
||||||
interrupts = <1 14 0>;
|
interrupts = <1 14 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
motionpro-led@660 { // Motion-PRO status LED
|
motionpro-led@660 { // Motion-PRO status LED
|
||||||
|
|
@ -110,7 +105,6 @@
|
||||||
label = "motionpro-statusled";
|
label = "motionpro-statusled";
|
||||||
reg = <0x660 0x10>;
|
reg = <0x660 0x10>;
|
||||||
interrupts = <1 15 0>;
|
interrupts = <1 15 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
blink-delay = <100>; // 100 msec
|
blink-delay = <100>; // 100 msec
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -119,49 +113,46 @@
|
||||||
label = "motionpro-readyled";
|
label = "motionpro-readyled";
|
||||||
reg = <0x670 0x10>;
|
reg = <0x670 0x10>;
|
||||||
interrupts = <1 16 0>;
|
interrupts = <1 16 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
rtc@800 { // Real time clock
|
rtc@800 { // Real time clock
|
||||||
compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
|
compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
|
||||||
reg = <0x800 0x100>;
|
reg = <0x800 0x100>;
|
||||||
interrupts = <1 5 0 1 6 0>;
|
interrupts = <1 5 0 1 6 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
can@980 {
|
can@980 {
|
||||||
compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
|
compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
|
||||||
interrupts = <2 18 0>;
|
interrupts = <2 18 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
reg = <0x980 0x80>;
|
reg = <0x980 0x80>;
|
||||||
};
|
};
|
||||||
|
|
||||||
gpio@b00 {
|
gpio_simple: gpio@b00 {
|
||||||
compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
|
compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
|
||||||
reg = <0xb00 0x40>;
|
reg = <0xb00 0x40>;
|
||||||
interrupts = <1 7 0>;
|
interrupts = <1 7 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
gpio-controller;
|
||||||
|
#gpio-cells = <2>;
|
||||||
};
|
};
|
||||||
|
|
||||||
gpio@c00 {
|
gpio_wkup: gpio@c00 {
|
||||||
compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
|
compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
|
||||||
reg = <0xc00 0x40>;
|
reg = <0xc00 0x40>;
|
||||||
interrupts = <1 8 0 0 3 0>;
|
interrupts = <1 8 0 0 3 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
gpio-controller;
|
||||||
|
#gpio-cells = <2>;
|
||||||
};
|
};
|
||||||
|
|
||||||
spi@f00 {
|
spi@f00 {
|
||||||
compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
|
compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
|
||||||
reg = <0xf00 0x20>;
|
reg = <0xf00 0x20>;
|
||||||
interrupts = <2 13 0 2 14 0>;
|
interrupts = <2 13 0 2 14 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
usb@1000 {
|
usb@1000 {
|
||||||
compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
|
compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
|
||||||
reg = <0x1000 0xff>;
|
reg = <0x1000 0xff>;
|
||||||
interrupts = <2 6 0>;
|
interrupts = <2 6 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
dma-controller@1200 {
|
dma-controller@1200 {
|
||||||
|
|
@ -171,7 +162,6 @@
|
||||||
3 4 0 3 5 0 3 6 0 3 7 0
|
3 4 0 3 5 0 3 6 0 3 7 0
|
||||||
3 8 0 3 9 0 3 10 0 3 11 0
|
3 8 0 3 9 0 3 10 0 3 11 0
|
||||||
3 12 0 3 13 0 3 14 0 3 15 0>;
|
3 12 0 3 13 0 3 14 0 3 15 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
xlb@1f00 {
|
xlb@1f00 {
|
||||||
|
|
@ -180,12 +170,9 @@
|
||||||
};
|
};
|
||||||
|
|
||||||
serial@2000 { // PSC1
|
serial@2000 { // PSC1
|
||||||
device_type = "serial";
|
|
||||||
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||||
port-number = <0>; // Logical port assignment
|
|
||||||
reg = <0x2000 0x100>;
|
reg = <0x2000 0x100>;
|
||||||
interrupts = <2 1 0>;
|
interrupts = <2 1 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
// PSC2 in spi master mode
|
// PSC2 in spi master mode
|
||||||
|
|
@ -194,26 +181,20 @@
|
||||||
cell-index = <1>;
|
cell-index = <1>;
|
||||||
reg = <0x2200 0x100>;
|
reg = <0x2200 0x100>;
|
||||||
interrupts = <2 2 0>;
|
interrupts = <2 2 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
// PSC5 in uart mode
|
// PSC5 in uart mode
|
||||||
serial@2800 { // PSC5
|
serial@2800 { // PSC5
|
||||||
device_type = "serial";
|
|
||||||
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||||
port-number = <4>; // Logical port assignment
|
|
||||||
reg = <0x2800 0x100>;
|
reg = <0x2800 0x100>;
|
||||||
interrupts = <2 12 0>;
|
interrupts = <2 12 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
ethernet@3000 {
|
ethernet@3000 {
|
||||||
device_type = "network";
|
|
||||||
compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
|
compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
|
||||||
reg = <0x3000 0x400>;
|
reg = <0x3000 0x400>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <2 5 0>;
|
interrupts = <2 5 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
phy-handle = <&phy0>;
|
phy-handle = <&phy0>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -223,10 +204,8 @@
|
||||||
compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
|
compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
|
||||||
reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
|
reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
|
||||||
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
|
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
|
|
||||||
phy0: ethernet-phy@2 {
|
phy0: ethernet-phy@2 {
|
||||||
device_type = "ethernet-phy";
|
|
||||||
reg = <2>;
|
reg = <2>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
@ -235,7 +214,6 @@
|
||||||
compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
|
compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
|
||||||
reg = <0x3a00 0x100>;
|
reg = <0x3a00 0x100>;
|
||||||
interrupts = <2 7 0>;
|
interrupts = <2 7 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
i2c@3d40 {
|
i2c@3d40 {
|
||||||
|
|
@ -244,7 +222,6 @@
|
||||||
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
|
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
|
||||||
reg = <0x3d40 0x40>;
|
reg = <0x3d40 0x40>;
|
||||||
interrupts = <2 16 0>;
|
interrupts = <2 16 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
fsl5200-clocking;
|
fsl5200-clocking;
|
||||||
|
|
||||||
rtc@68 {
|
rtc@68 {
|
||||||
|
|
@ -259,8 +236,8 @@
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
lpb {
|
localbus {
|
||||||
compatible = "fsl,lpb";
|
compatible = "fsl,mpc5200b-lpb","simple-bus";
|
||||||
#address-cells = <2>;
|
#address-cells = <2>;
|
||||||
#size-cells = <1>;
|
#size-cells = <1>;
|
||||||
ranges = <0 0 0xff000000 0x01000000
|
ranges = <0 0 0xff000000 0x01000000
|
||||||
|
|
@ -273,7 +250,6 @@
|
||||||
compatible = "promess,motionpro-kollmorgen";
|
compatible = "promess,motionpro-kollmorgen";
|
||||||
reg = <1 0 0x10000>;
|
reg = <1 0 0x10000>;
|
||||||
interrupts = <1 1 0>;
|
interrupts = <1 1 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
// 8-bit board CPLD on LocalPlus Bus CS2
|
// 8-bit board CPLD on LocalPlus Bus CS2
|
||||||
|
|
|
||||||
|
|
@ -180,7 +180,7 @@
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <1>;
|
#size-cells = <1>;
|
||||||
sleep = <&pmc 0x20000000>;
|
sleep = <&pmc 0x20000000>;
|
||||||
ranges;
|
ranges = <0x0 0x24000 0x1000>;
|
||||||
|
|
||||||
cell-index = <0>;
|
cell-index = <0>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
|
|
@ -195,11 +195,11 @@
|
||||||
fixed-link = <1 1 1000 0 0>;
|
fixed-link = <1 1 1000 0 0>;
|
||||||
fsl,magic-packet;
|
fsl,magic-packet;
|
||||||
|
|
||||||
mdio@24520 {
|
mdio@520 {
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <0>;
|
#size-cells = <0>;
|
||||||
compatible = "fsl,gianfar-mdio";
|
compatible = "fsl,gianfar-mdio";
|
||||||
reg = <0x24520 0x20>;
|
reg = <0x520 0x20>;
|
||||||
phy4: ethernet-phy@4 {
|
phy4: ethernet-phy@4 {
|
||||||
interrupt-parent = <&ipic>;
|
interrupt-parent = <&ipic>;
|
||||||
interrupts = <20 0x8>;
|
interrupts = <20 0x8>;
|
||||||
|
|
@ -221,6 +221,7 @@
|
||||||
model = "eTSEC";
|
model = "eTSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x25000 0x1000>;
|
reg = <0x25000 0x1000>;
|
||||||
|
ranges = <0x0 0x25000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <34 0x8 33 0x8 32 0x8>;
|
interrupts = <34 0x8 33 0x8 32 0x8>;
|
||||||
interrupt-parent = <&ipic>;
|
interrupt-parent = <&ipic>;
|
||||||
|
|
@ -229,11 +230,11 @@
|
||||||
sleep = <&pmc 0x10000000>;
|
sleep = <&pmc 0x10000000>;
|
||||||
fsl,magic-packet;
|
fsl,magic-packet;
|
||||||
|
|
||||||
mdio@25520 {
|
mdio@520 {
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <0>;
|
#size-cells = <0>;
|
||||||
compatible = "fsl,gianfar-tbi";
|
compatible = "fsl,gianfar-tbi";
|
||||||
reg = <0x25520 0x20>;
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
tbi1: tbi-phy@11 {
|
tbi1: tbi-phy@11 {
|
||||||
reg = <0x11>;
|
reg = <0x11>;
|
||||||
|
|
|
||||||
|
|
@ -22,6 +22,8 @@
|
||||||
serial0 = &serial0;
|
serial0 = &serial0;
|
||||||
serial1 = &serial1;
|
serial1 = &serial1;
|
||||||
pci0 = &pci0;
|
pci0 = &pci0;
|
||||||
|
pci1 = &pci1;
|
||||||
|
pci2 = &pci2;
|
||||||
};
|
};
|
||||||
|
|
||||||
cpus {
|
cpus {
|
||||||
|
|
@ -188,66 +190,74 @@
|
||||||
phy_type = "utmi";
|
phy_type = "utmi";
|
||||||
};
|
};
|
||||||
|
|
||||||
mdio@24520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-mdio";
|
|
||||||
reg = <0x24520 0x20>;
|
|
||||||
phy0: ethernet-phy@0 {
|
|
||||||
interrupt-parent = <&ipic>;
|
|
||||||
interrupts = <20 0x8>;
|
|
||||||
reg = <0x0>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
phy1: ethernet-phy@1 {
|
|
||||||
interrupt-parent = <&ipic>;
|
|
||||||
interrupts = <19 0x8>;
|
|
||||||
reg = <0x1>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
tbi0: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
mdio@25520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-tbi";
|
|
||||||
reg = <0x25520 0x20>;
|
|
||||||
|
|
||||||
tbi1: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
|
|
||||||
enet0: ethernet@24000 {
|
enet0: ethernet@24000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <0>;
|
cell-index = <0>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "eTSEC";
|
model = "eTSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x24000 0x1000>;
|
reg = <0x24000 0x1000>;
|
||||||
|
ranges = <0x0 0x24000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <32 0x8 33 0x8 34 0x8>;
|
interrupts = <32 0x8 33 0x8 34 0x8>;
|
||||||
interrupt-parent = <&ipic>;
|
interrupt-parent = <&ipic>;
|
||||||
tbi-handle = <&tbi0>;
|
tbi-handle = <&tbi0>;
|
||||||
phy-handle = < &phy0 >;
|
phy-handle = < &phy0 >;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-mdio";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
phy0: ethernet-phy@0 {
|
||||||
|
interrupt-parent = <&ipic>;
|
||||||
|
interrupts = <20 0x8>;
|
||||||
|
reg = <0x0>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
|
||||||
|
phy1: ethernet-phy@1 {
|
||||||
|
interrupt-parent = <&ipic>;
|
||||||
|
interrupts = <19 0x8>;
|
||||||
|
reg = <0x1>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
|
||||||
|
tbi0: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
enet1: ethernet@25000 {
|
enet1: ethernet@25000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <1>;
|
cell-index = <1>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "eTSEC";
|
model = "eTSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x25000 0x1000>;
|
reg = <0x25000 0x1000>;
|
||||||
|
ranges = <0x0 0x25000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <35 0x8 36 0x8 37 0x8>;
|
interrupts = <35 0x8 36 0x8 37 0x8>;
|
||||||
interrupt-parent = <&ipic>;
|
interrupt-parent = <&ipic>;
|
||||||
tbi-handle = <&tbi1>;
|
tbi-handle = <&tbi1>;
|
||||||
phy-handle = < &phy1 >;
|
phy-handle = < &phy1 >;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-tbi";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
tbi1: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
serial0: serial@4500 {
|
serial0: serial@4500 {
|
||||||
|
|
@ -349,4 +359,66 @@
|
||||||
compatible = "fsl,mpc8349-pci";
|
compatible = "fsl,mpc8349-pci";
|
||||||
device_type = "pci";
|
device_type = "pci";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
pci1: pcie@e0009000 {
|
||||||
|
#address-cells = <3>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
#interrupt-cells = <1>;
|
||||||
|
device_type = "pci";
|
||||||
|
compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie";
|
||||||
|
reg = <0xe0009000 0x00001000>;
|
||||||
|
ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
|
||||||
|
0x01000000 0 0x00000000 0xb1000000 0 0x00800000>;
|
||||||
|
bus-range = <0 255>;
|
||||||
|
interrupt-map-mask = <0xf800 0 0 7>;
|
||||||
|
interrupt-map = <0 0 0 1 &ipic 1 8
|
||||||
|
0 0 0 2 &ipic 1 8
|
||||||
|
0 0 0 3 &ipic 1 8
|
||||||
|
0 0 0 4 &ipic 1 8>;
|
||||||
|
clock-frequency = <0>;
|
||||||
|
|
||||||
|
pcie@0 {
|
||||||
|
#address-cells = <3>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
device_type = "pci";
|
||||||
|
reg = <0 0 0 0 0>;
|
||||||
|
ranges = <0x02000000 0 0xa0000000
|
||||||
|
0x02000000 0 0xa0000000
|
||||||
|
0 0x10000000
|
||||||
|
0x01000000 0 0x00000000
|
||||||
|
0x01000000 0 0x00000000
|
||||||
|
0 0x00800000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
pci2: pcie@e000a000 {
|
||||||
|
#address-cells = <3>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
#interrupt-cells = <1>;
|
||||||
|
device_type = "pci";
|
||||||
|
compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie";
|
||||||
|
reg = <0xe000a000 0x00001000>;
|
||||||
|
ranges = <0x02000000 0 0xc0000000 0xc0000000 0 0x10000000
|
||||||
|
0x01000000 0 0x00000000 0xd1000000 0 0x00800000>;
|
||||||
|
bus-range = <0 255>;
|
||||||
|
interrupt-map-mask = <0xf800 0 0 7>;
|
||||||
|
interrupt-map = <0 0 0 1 &ipic 2 8
|
||||||
|
0 0 0 2 &ipic 2 8
|
||||||
|
0 0 0 3 &ipic 2 8
|
||||||
|
0 0 0 4 &ipic 2 8>;
|
||||||
|
clock-frequency = <0>;
|
||||||
|
|
||||||
|
pcie@0 {
|
||||||
|
#address-cells = <3>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
device_type = "pci";
|
||||||
|
reg = <0 0 0 0 0>;
|
||||||
|
ranges = <0x02000000 0 0xc0000000
|
||||||
|
0x02000000 0 0xc0000000
|
||||||
|
0 0x10000000
|
||||||
|
0x01000000 0 0x00000000
|
||||||
|
0x01000000 0 0x00000000
|
||||||
|
0 0x00800000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
|
||||||
|
|
@ -170,57 +170,52 @@
|
||||||
phy_type = "ulpi";
|
phy_type = "ulpi";
|
||||||
};
|
};
|
||||||
|
|
||||||
mdio@24520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-mdio";
|
|
||||||
reg = <0x24520 0x20>;
|
|
||||||
|
|
||||||
/* Vitesse 8201 */
|
|
||||||
phy1c: ethernet-phy@1c {
|
|
||||||
interrupt-parent = <&ipic>;
|
|
||||||
interrupts = <18 0x8>;
|
|
||||||
reg = <0x1c>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
tbi0: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
mdio@25520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-tbi";
|
|
||||||
reg = <0x25520 0x20>;
|
|
||||||
|
|
||||||
tbi1: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
enet0: ethernet@24000 {
|
enet0: ethernet@24000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <0>;
|
cell-index = <0>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "TSEC";
|
model = "TSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x24000 0x1000>;
|
reg = <0x24000 0x1000>;
|
||||||
|
ranges = <0x0 0x24000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <32 0x8 33 0x8 34 0x8>;
|
interrupts = <32 0x8 33 0x8 34 0x8>;
|
||||||
interrupt-parent = <&ipic>;
|
interrupt-parent = <&ipic>;
|
||||||
tbi-handle = <&tbi0>;
|
tbi-handle = <&tbi0>;
|
||||||
phy-handle = <&phy1c>;
|
phy-handle = <&phy1c>;
|
||||||
linux,network-index = <0>;
|
linux,network-index = <0>;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-mdio";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
/* Vitesse 8201 */
|
||||||
|
phy1c: ethernet-phy@1c {
|
||||||
|
interrupt-parent = <&ipic>;
|
||||||
|
interrupts = <18 0x8>;
|
||||||
|
reg = <0x1c>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
|
||||||
|
tbi0: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
enet1: ethernet@25000 {
|
enet1: ethernet@25000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <1>;
|
cell-index = <1>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "TSEC";
|
model = "TSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x25000 0x1000>;
|
reg = <0x25000 0x1000>;
|
||||||
|
ranges = <0x0 0x25000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <35 0x8 36 0x8 37 0x8>;
|
interrupts = <35 0x8 36 0x8 37 0x8>;
|
||||||
interrupt-parent = <&ipic>;
|
interrupt-parent = <&ipic>;
|
||||||
|
|
@ -228,6 +223,18 @@
|
||||||
fixed-link = <1 1 1000 0 0>;
|
fixed-link = <1 1 1000 0 0>;
|
||||||
linux,network-index = <1>;
|
linux,network-index = <1>;
|
||||||
tbi-handle = <&tbi1>;
|
tbi-handle = <&tbi1>;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-tbi";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
tbi1: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
serial0: serial@4500 {
|
serial0: serial@4500 {
|
||||||
|
|
|
||||||
|
|
@ -149,37 +149,41 @@
|
||||||
phy_type = "ulpi";
|
phy_type = "ulpi";
|
||||||
};
|
};
|
||||||
|
|
||||||
mdio@24520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-mdio";
|
|
||||||
reg = <0x24520 0x20>;
|
|
||||||
|
|
||||||
/* Vitesse 8201 */
|
|
||||||
phy1c: ethernet-phy@1c {
|
|
||||||
interrupt-parent = <&ipic>;
|
|
||||||
interrupts = <18 0x8>;
|
|
||||||
reg = <0x1c>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
tbi0: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
enet0: ethernet@24000 {
|
enet0: ethernet@24000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <0>;
|
cell-index = <0>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "TSEC";
|
model = "TSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x24000 0x1000>;
|
reg = <0x24000 0x1000>;
|
||||||
|
ranges = <0x0 0x24000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <32 0x8 33 0x8 34 0x8>;
|
interrupts = <32 0x8 33 0x8 34 0x8>;
|
||||||
interrupt-parent = <&ipic>;
|
interrupt-parent = <&ipic>;
|
||||||
tbi-handle = <&tbi0>;
|
tbi-handle = <&tbi0>;
|
||||||
phy-handle = <&phy1c>;
|
phy-handle = <&phy1c>;
|
||||||
linux,network-index = <0>;
|
linux,network-index = <0>;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-mdio";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
/* Vitesse 8201 */
|
||||||
|
phy1c: ethernet-phy@1c {
|
||||||
|
interrupt-parent = <&ipic>;
|
||||||
|
interrupts = <18 0x8>;
|
||||||
|
reg = <0x1c>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
|
||||||
|
tbi0: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
serial0: serial@4500 {
|
serial0: serial@4500 {
|
||||||
|
|
|
||||||
|
|
@ -167,69 +167,76 @@
|
||||||
phy_type = "ulpi";
|
phy_type = "ulpi";
|
||||||
};
|
};
|
||||||
|
|
||||||
mdio@24520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-mdio";
|
|
||||||
reg = <0x24520 0x20>;
|
|
||||||
|
|
||||||
phy0: ethernet-phy@0 {
|
|
||||||
interrupt-parent = <&ipic>;
|
|
||||||
interrupts = <17 0x8>;
|
|
||||||
reg = <0x0>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
phy1: ethernet-phy@1 {
|
|
||||||
interrupt-parent = <&ipic>;
|
|
||||||
interrupts = <18 0x8>;
|
|
||||||
reg = <0x1>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
tbi0: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
mdio@25520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-tbi";
|
|
||||||
reg = <0x25520 0x20>;
|
|
||||||
|
|
||||||
tbi1: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
|
|
||||||
enet0: ethernet@24000 {
|
enet0: ethernet@24000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <0>;
|
cell-index = <0>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "TSEC";
|
model = "TSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x24000 0x1000>;
|
reg = <0x24000 0x1000>;
|
||||||
|
ranges = <0x0 0x24000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <32 0x8 33 0x8 34 0x8>;
|
interrupts = <32 0x8 33 0x8 34 0x8>;
|
||||||
interrupt-parent = <&ipic>;
|
interrupt-parent = <&ipic>;
|
||||||
tbi-handle = <&tbi0>;
|
tbi-handle = <&tbi0>;
|
||||||
phy-handle = <&phy0>;
|
phy-handle = <&phy0>;
|
||||||
linux,network-index = <0>;
|
linux,network-index = <0>;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-mdio";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
phy0: ethernet-phy@0 {
|
||||||
|
interrupt-parent = <&ipic>;
|
||||||
|
interrupts = <17 0x8>;
|
||||||
|
reg = <0x0>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
|
||||||
|
phy1: ethernet-phy@1 {
|
||||||
|
interrupt-parent = <&ipic>;
|
||||||
|
interrupts = <18 0x8>;
|
||||||
|
reg = <0x1>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
|
||||||
|
tbi0: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
enet1: ethernet@25000 {
|
enet1: ethernet@25000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <1>;
|
cell-index = <1>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "TSEC";
|
model = "TSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x25000 0x1000>;
|
reg = <0x25000 0x1000>;
|
||||||
|
ranges = <0x0 0x25000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <35 0x8 36 0x8 37 0x8>;
|
interrupts = <35 0x8 36 0x8 37 0x8>;
|
||||||
interrupt-parent = <&ipic>;
|
interrupt-parent = <&ipic>;
|
||||||
tbi-handle = <&tbi1>;
|
tbi-handle = <&tbi1>;
|
||||||
phy-handle = <&phy1>;
|
phy-handle = <&phy1>;
|
||||||
linux,network-index = <1>;
|
linux,network-index = <1>;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-tbi";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
tbi1: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
serial0: serial@4500 {
|
serial0: serial@4500 {
|
||||||
|
|
|
||||||
|
|
@ -23,6 +23,8 @@
|
||||||
serial0 = &serial0;
|
serial0 = &serial0;
|
||||||
serial1 = &serial1;
|
serial1 = &serial1;
|
||||||
pci0 = &pci0;
|
pci0 = &pci0;
|
||||||
|
pci1 = &pci1;
|
||||||
|
pci2 = &pci2;
|
||||||
};
|
};
|
||||||
|
|
||||||
cpus {
|
cpus {
|
||||||
|
|
@ -127,21 +129,38 @@
|
||||||
reg = <0x200 0x100>;
|
reg = <0x200 0x100>;
|
||||||
};
|
};
|
||||||
|
|
||||||
i2c@3000 {
|
sleep-nexus {
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <0>;
|
#size-cells = <1>;
|
||||||
cell-index = <0>;
|
compatible = "simple-bus";
|
||||||
compatible = "fsl-i2c";
|
sleep = <&pmc 0x0c000000>;
|
||||||
reg = <0x3000 0x100>;
|
ranges;
|
||||||
interrupts = <14 0x8>;
|
|
||||||
interrupt-parent = <&ipic>;
|
|
||||||
dfsrr;
|
|
||||||
|
|
||||||
rtc@68 {
|
i2c@3000 {
|
||||||
compatible = "dallas,ds1374";
|
#address-cells = <1>;
|
||||||
reg = <0x68>;
|
#size-cells = <0>;
|
||||||
interrupts = <19 0x8>;
|
cell-index = <0>;
|
||||||
|
compatible = "fsl-i2c";
|
||||||
|
reg = <0x3000 0x100>;
|
||||||
|
interrupts = <14 0x8>;
|
||||||
interrupt-parent = <&ipic>;
|
interrupt-parent = <&ipic>;
|
||||||
|
dfsrr;
|
||||||
|
|
||||||
|
rtc@68 {
|
||||||
|
compatible = "dallas,ds1374";
|
||||||
|
reg = <0x68>;
|
||||||
|
interrupts = <19 0x8>;
|
||||||
|
interrupt-parent = <&ipic>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
sdhci@2e000 {
|
||||||
|
compatible = "fsl,mpc8377-esdhc", "fsl,mpc8379-esdhc";
|
||||||
|
reg = <0x2e000 0x1000>;
|
||||||
|
interrupts = <42 0x8>;
|
||||||
|
interrupt-parent = <&ipic>;
|
||||||
|
/* Filled in by U-Boot */
|
||||||
|
clock-frequency = <0>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -174,70 +193,83 @@
|
||||||
interrupts = <38 0x8>;
|
interrupts = <38 0x8>;
|
||||||
dr_mode = "host";
|
dr_mode = "host";
|
||||||
phy_type = "ulpi";
|
phy_type = "ulpi";
|
||||||
|
sleep = <&pmc 0x00c00000>;
|
||||||
};
|
};
|
||||||
|
|
||||||
mdio@24520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-mdio";
|
|
||||||
reg = <0x24520 0x20>;
|
|
||||||
phy2: ethernet-phy@2 {
|
|
||||||
interrupt-parent = <&ipic>;
|
|
||||||
interrupts = <17 0x8>;
|
|
||||||
reg = <0x2>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
phy3: ethernet-phy@3 {
|
|
||||||
interrupt-parent = <&ipic>;
|
|
||||||
interrupts = <18 0x8>;
|
|
||||||
reg = <0x3>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
tbi0: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
mdio@25520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-tbi";
|
|
||||||
reg = <0x25520 0x20>;
|
|
||||||
|
|
||||||
tbi1: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
|
|
||||||
enet0: ethernet@24000 {
|
enet0: ethernet@24000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <0>;
|
cell-index = <0>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "eTSEC";
|
model = "eTSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x24000 0x1000>;
|
reg = <0x24000 0x1000>;
|
||||||
|
ranges = <0x0 0x24000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <32 0x8 33 0x8 34 0x8>;
|
interrupts = <32 0x8 33 0x8 34 0x8>;
|
||||||
phy-connection-type = "mii";
|
phy-connection-type = "mii";
|
||||||
interrupt-parent = <&ipic>;
|
interrupt-parent = <&ipic>;
|
||||||
tbi-handle = <&tbi0>;
|
tbi-handle = <&tbi0>;
|
||||||
phy-handle = <&phy2>;
|
phy-handle = <&phy2>;
|
||||||
|
sleep = <&pmc 0xc0000000>;
|
||||||
|
fsl,magic-packet;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-mdio";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
phy2: ethernet-phy@2 {
|
||||||
|
interrupt-parent = <&ipic>;
|
||||||
|
interrupts = <17 0x8>;
|
||||||
|
reg = <0x2>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
|
||||||
|
phy3: ethernet-phy@3 {
|
||||||
|
interrupt-parent = <&ipic>;
|
||||||
|
interrupts = <18 0x8>;
|
||||||
|
reg = <0x3>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
|
||||||
|
tbi0: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
enet1: ethernet@25000 {
|
enet1: ethernet@25000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <1>;
|
cell-index = <1>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "eTSEC";
|
model = "eTSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x25000 0x1000>;
|
reg = <0x25000 0x1000>;
|
||||||
|
ranges = <0x0 0x25000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <35 0x8 36 0x8 37 0x8>;
|
interrupts = <35 0x8 36 0x8 37 0x8>;
|
||||||
phy-connection-type = "mii";
|
phy-connection-type = "mii";
|
||||||
interrupt-parent = <&ipic>;
|
interrupt-parent = <&ipic>;
|
||||||
tbi-handle = <&tbi1>;
|
tbi-handle = <&tbi1>;
|
||||||
phy-handle = <&phy3>;
|
phy-handle = <&phy3>;
|
||||||
|
sleep = <&pmc 0x30000000>;
|
||||||
|
fsl,magic-packet;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-tbi";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
tbi1: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
serial0: serial@4500 {
|
serial0: serial@4500 {
|
||||||
|
|
@ -309,14 +341,7 @@
|
||||||
fsl,channel-fifo-len = <24>;
|
fsl,channel-fifo-len = <24>;
|
||||||
fsl,exec-units-mask = <0x9fe>;
|
fsl,exec-units-mask = <0x9fe>;
|
||||||
fsl,descriptor-types-mask = <0x3ab0ebf>;
|
fsl,descriptor-types-mask = <0x3ab0ebf>;
|
||||||
};
|
sleep = <&pmc 0x03000000>;
|
||||||
|
|
||||||
sdhc@2e000 {
|
|
||||||
model = "eSDHC";
|
|
||||||
compatible = "fsl,esdhc";
|
|
||||||
reg = <0x2e000 0x1000>;
|
|
||||||
interrupts = <42 0x8>;
|
|
||||||
interrupt-parent = <&ipic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
sata@18000 {
|
sata@18000 {
|
||||||
|
|
@ -324,6 +349,7 @@
|
||||||
reg = <0x18000 0x1000>;
|
reg = <0x18000 0x1000>;
|
||||||
interrupts = <44 0x8>;
|
interrupts = <44 0x8>;
|
||||||
interrupt-parent = <&ipic>;
|
interrupt-parent = <&ipic>;
|
||||||
|
sleep = <&pmc 0x000000c0>;
|
||||||
};
|
};
|
||||||
|
|
||||||
sata@19000 {
|
sata@19000 {
|
||||||
|
|
@ -331,6 +357,7 @@
|
||||||
reg = <0x19000 0x1000>;
|
reg = <0x19000 0x1000>;
|
||||||
interrupts = <45 0x8>;
|
interrupts = <45 0x8>;
|
||||||
interrupt-parent = <&ipic>;
|
interrupt-parent = <&ipic>;
|
||||||
|
sleep = <&pmc 0x00000030>;
|
||||||
};
|
};
|
||||||
|
|
||||||
/* IPIC
|
/* IPIC
|
||||||
|
|
@ -346,6 +373,13 @@
|
||||||
#interrupt-cells = <2>;
|
#interrupt-cells = <2>;
|
||||||
reg = <0x700 0x100>;
|
reg = <0x700 0x100>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
pmc: power@b00 {
|
||||||
|
compatible = "fsl,mpc8377-pmc", "fsl,mpc8349-pmc";
|
||||||
|
reg = <0xb00 0x100 0xa00 0x100>;
|
||||||
|
interrupts = <80 0x8>;
|
||||||
|
interrupt-parent = <&ipic>;
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
pci0: pci@e0008500 {
|
pci0: pci@e0008500 {
|
||||||
|
|
@ -400,6 +434,7 @@
|
||||||
ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
|
ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
|
||||||
0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
|
0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
|
||||||
0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
|
0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
|
||||||
|
sleep = <&pmc 0x00010000>;
|
||||||
clock-frequency = <0>;
|
clock-frequency = <0>;
|
||||||
#interrupt-cells = <1>;
|
#interrupt-cells = <1>;
|
||||||
#size-cells = <2>;
|
#size-cells = <2>;
|
||||||
|
|
@ -409,4 +444,68 @@
|
||||||
compatible = "fsl,mpc8349-pci";
|
compatible = "fsl,mpc8349-pci";
|
||||||
device_type = "pci";
|
device_type = "pci";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
pci1: pcie@e0009000 {
|
||||||
|
#address-cells = <3>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
#interrupt-cells = <1>;
|
||||||
|
device_type = "pci";
|
||||||
|
compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
|
||||||
|
reg = <0xe0009000 0x00001000>;
|
||||||
|
ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
|
||||||
|
0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
|
||||||
|
bus-range = <0 255>;
|
||||||
|
interrupt-map-mask = <0xf800 0 0 7>;
|
||||||
|
interrupt-map = <0 0 0 1 &ipic 1 8
|
||||||
|
0 0 0 2 &ipic 1 8
|
||||||
|
0 0 0 3 &ipic 1 8
|
||||||
|
0 0 0 4 &ipic 1 8>;
|
||||||
|
sleep = <&pmc 0x00300000>;
|
||||||
|
clock-frequency = <0>;
|
||||||
|
|
||||||
|
pcie@0 {
|
||||||
|
#address-cells = <3>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
device_type = "pci";
|
||||||
|
reg = <0 0 0 0 0>;
|
||||||
|
ranges = <0x02000000 0 0xa8000000
|
||||||
|
0x02000000 0 0xa8000000
|
||||||
|
0 0x10000000
|
||||||
|
0x01000000 0 0x00000000
|
||||||
|
0x01000000 0 0x00000000
|
||||||
|
0 0x00800000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
pci2: pcie@e000a000 {
|
||||||
|
#address-cells = <3>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
#interrupt-cells = <1>;
|
||||||
|
device_type = "pci";
|
||||||
|
compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
|
||||||
|
reg = <0xe000a000 0x00001000>;
|
||||||
|
ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
|
||||||
|
0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
|
||||||
|
bus-range = <0 255>;
|
||||||
|
interrupt-map-mask = <0xf800 0 0 7>;
|
||||||
|
interrupt-map = <0 0 0 1 &ipic 2 8
|
||||||
|
0 0 0 2 &ipic 2 8
|
||||||
|
0 0 0 3 &ipic 2 8
|
||||||
|
0 0 0 4 &ipic 2 8>;
|
||||||
|
sleep = <&pmc 0x000c0000>;
|
||||||
|
clock-frequency = <0>;
|
||||||
|
|
||||||
|
pcie@0 {
|
||||||
|
#address-cells = <3>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
device_type = "pci";
|
||||||
|
reg = <0 0 0 0 0>;
|
||||||
|
ranges = <0x02000000 0 0xc8000000
|
||||||
|
0x02000000 0 0xc8000000
|
||||||
|
0 0x10000000
|
||||||
|
0x01000000 0 0x00000000
|
||||||
|
0x01000000 0 0x00000000
|
||||||
|
0 0x00800000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
|
||||||
|
|
@ -22,6 +22,8 @@
|
||||||
serial0 = &serial0;
|
serial0 = &serial0;
|
||||||
serial1 = &serial1;
|
serial1 = &serial1;
|
||||||
pci0 = &pci0;
|
pci0 = &pci0;
|
||||||
|
pci1 = &pci1;
|
||||||
|
pci2 = &pci2;
|
||||||
};
|
};
|
||||||
|
|
||||||
cpus {
|
cpus {
|
||||||
|
|
@ -107,26 +109,72 @@
|
||||||
reg = <0x200 0x100>;
|
reg = <0x200 0x100>;
|
||||||
};
|
};
|
||||||
|
|
||||||
i2c@3000 {
|
gpio1: gpio-controller@c00 {
|
||||||
#address-cells = <1>;
|
#gpio-cells = <2>;
|
||||||
#size-cells = <0>;
|
compatible = "fsl,mpc8377-gpio", "fsl,mpc8349-gpio";
|
||||||
cell-index = <0>;
|
reg = <0xc00 0x100>;
|
||||||
compatible = "fsl-i2c";
|
interrupts = <74 0x8>;
|
||||||
reg = <0x3000 0x100>;
|
|
||||||
interrupts = <14 0x8>;
|
|
||||||
interrupt-parent = <&ipic>;
|
interrupt-parent = <&ipic>;
|
||||||
dfsrr;
|
gpio-controller;
|
||||||
rtc@68 {
|
};
|
||||||
compatible = "dallas,ds1339";
|
|
||||||
reg = <0x68>;
|
gpio2: gpio-controller@d00 {
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
compatible = "fsl,mpc8377-gpio", "fsl,mpc8349-gpio";
|
||||||
|
reg = <0xd00 0x100>;
|
||||||
|
interrupts = <75 0x8>;
|
||||||
|
interrupt-parent = <&ipic>;
|
||||||
|
gpio-controller;
|
||||||
|
};
|
||||||
|
|
||||||
|
sleep-nexus {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
compatible = "simple-bus";
|
||||||
|
sleep = <&pmc 0x0c000000>;
|
||||||
|
ranges;
|
||||||
|
|
||||||
|
i2c@3000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
cell-index = <0>;
|
||||||
|
compatible = "fsl-i2c";
|
||||||
|
reg = <0x3000 0x100>;
|
||||||
|
interrupts = <14 0x8>;
|
||||||
|
interrupt-parent = <&ipic>;
|
||||||
|
dfsrr;
|
||||||
|
|
||||||
|
dtt@48 {
|
||||||
|
compatible = "national,lm75";
|
||||||
|
reg = <0x48>;
|
||||||
|
};
|
||||||
|
|
||||||
|
at24@50 {
|
||||||
|
compatible = "at24,24c256";
|
||||||
|
reg = <0x50>;
|
||||||
|
};
|
||||||
|
|
||||||
|
rtc@68 {
|
||||||
|
compatible = "dallas,ds1339";
|
||||||
|
reg = <0x68>;
|
||||||
|
};
|
||||||
|
|
||||||
|
mcu_pio: mcu@a {
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
compatible = "fsl,mc9s08qg8-mpc8377erdb",
|
||||||
|
"fsl,mcu-mpc8349emitx";
|
||||||
|
reg = <0x0a>;
|
||||||
|
gpio-controller;
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
mcu_pio: mcu@a {
|
sdhci@2e000 {
|
||||||
#gpio-cells = <2>;
|
compatible = "fsl,mpc8377-esdhc", "fsl,mpc8379-esdhc";
|
||||||
compatible = "fsl,mc9s08qg8-mpc8377erdb",
|
reg = <0x2e000 0x1000>;
|
||||||
"fsl,mcu-mpc8349emitx";
|
interrupts = <42 0x8>;
|
||||||
reg = <0x0a>;
|
interrupt-parent = <&ipic>;
|
||||||
gpio-controller;
|
/* Filled in by U-Boot */
|
||||||
|
clock-frequency = <0>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -197,64 +245,76 @@
|
||||||
interrupt-parent = <&ipic>;
|
interrupt-parent = <&ipic>;
|
||||||
interrupts = <38 0x8>;
|
interrupts = <38 0x8>;
|
||||||
phy_type = "ulpi";
|
phy_type = "ulpi";
|
||||||
|
sleep = <&pmc 0x00c00000>;
|
||||||
};
|
};
|
||||||
|
|
||||||
mdio@24520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-mdio";
|
|
||||||
reg = <0x24520 0x20>;
|
|
||||||
phy2: ethernet-phy@2 {
|
|
||||||
interrupt-parent = <&ipic>;
|
|
||||||
interrupts = <17 0x8>;
|
|
||||||
reg = <0x2>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
tbi0: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
mdio@25520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-tbi";
|
|
||||||
reg = <0x25520 0x20>;
|
|
||||||
|
|
||||||
tbi1: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
|
|
||||||
enet0: ethernet@24000 {
|
enet0: ethernet@24000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <0>;
|
cell-index = <0>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "eTSEC";
|
model = "eTSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x24000 0x1000>;
|
reg = <0x24000 0x1000>;
|
||||||
|
ranges = <0x0 0x24000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <32 0x8 33 0x8 34 0x8>;
|
interrupts = <32 0x8 33 0x8 34 0x8>;
|
||||||
phy-connection-type = "mii";
|
phy-connection-type = "mii";
|
||||||
interrupt-parent = <&ipic>;
|
interrupt-parent = <&ipic>;
|
||||||
tbi-handle = <&tbi0>;
|
tbi-handle = <&tbi0>;
|
||||||
phy-handle = <&phy2>;
|
phy-handle = <&phy2>;
|
||||||
|
sleep = <&pmc 0xc0000000>;
|
||||||
|
fsl,magic-packet;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-mdio";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
phy2: ethernet-phy@2 {
|
||||||
|
interrupt-parent = <&ipic>;
|
||||||
|
interrupts = <17 0x8>;
|
||||||
|
reg = <0x2>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
|
||||||
|
tbi0: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
enet1: ethernet@25000 {
|
enet1: ethernet@25000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <1>;
|
cell-index = <1>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "eTSEC";
|
model = "eTSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x25000 0x1000>;
|
reg = <0x25000 0x1000>;
|
||||||
|
ranges = <0x0 0x25000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <35 0x8 36 0x8 37 0x8>;
|
interrupts = <35 0x8 36 0x8 37 0x8>;
|
||||||
phy-connection-type = "mii";
|
phy-connection-type = "mii";
|
||||||
interrupt-parent = <&ipic>;
|
interrupt-parent = <&ipic>;
|
||||||
fixed-link = <1 1 1000 0 0>;
|
fixed-link = <1 1 1000 0 0>;
|
||||||
tbi-handle = <&tbi1>;
|
tbi-handle = <&tbi1>;
|
||||||
|
sleep = <&pmc 0x30000000>;
|
||||||
|
fsl,magic-packet;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-tbi";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
tbi1: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
serial0: serial@4500 {
|
serial0: serial@4500 {
|
||||||
|
|
@ -287,6 +347,7 @@
|
||||||
fsl,channel-fifo-len = <24>;
|
fsl,channel-fifo-len = <24>;
|
||||||
fsl,exec-units-mask = <0x9fe>;
|
fsl,exec-units-mask = <0x9fe>;
|
||||||
fsl,descriptor-types-mask = <0x3ab0ebf>;
|
fsl,descriptor-types-mask = <0x3ab0ebf>;
|
||||||
|
sleep = <&pmc 0x03000000>;
|
||||||
};
|
};
|
||||||
|
|
||||||
sata@18000 {
|
sata@18000 {
|
||||||
|
|
@ -294,6 +355,7 @@
|
||||||
reg = <0x18000 0x1000>;
|
reg = <0x18000 0x1000>;
|
||||||
interrupts = <44 0x8>;
|
interrupts = <44 0x8>;
|
||||||
interrupt-parent = <&ipic>;
|
interrupt-parent = <&ipic>;
|
||||||
|
sleep = <&pmc 0x000000c0>;
|
||||||
};
|
};
|
||||||
|
|
||||||
sata@19000 {
|
sata@19000 {
|
||||||
|
|
@ -301,6 +363,7 @@
|
||||||
reg = <0x19000 0x1000>;
|
reg = <0x19000 0x1000>;
|
||||||
interrupts = <45 0x8>;
|
interrupts = <45 0x8>;
|
||||||
interrupt-parent = <&ipic>;
|
interrupt-parent = <&ipic>;
|
||||||
|
sleep = <&pmc 0x00000030>;
|
||||||
};
|
};
|
||||||
|
|
||||||
/* IPIC
|
/* IPIC
|
||||||
|
|
@ -316,6 +379,13 @@
|
||||||
#interrupt-cells = <2>;
|
#interrupt-cells = <2>;
|
||||||
reg = <0x700 0x100>;
|
reg = <0x700 0x100>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
pmc: power@b00 {
|
||||||
|
compatible = "fsl,mpc8377-pmc", "fsl,mpc8349-pmc";
|
||||||
|
reg = <0xb00 0x100 0xa00 0x100>;
|
||||||
|
interrupts = <80 0x8>;
|
||||||
|
interrupt-parent = <&ipic>;
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
pci0: pci@e0008500 {
|
pci0: pci@e0008500 {
|
||||||
|
|
@ -341,6 +411,7 @@
|
||||||
ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
|
ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
|
||||||
0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
|
0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
|
||||||
0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
|
0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
|
||||||
|
sleep = <&pmc 0x00010000>;
|
||||||
clock-frequency = <66666666>;
|
clock-frequency = <66666666>;
|
||||||
#interrupt-cells = <1>;
|
#interrupt-cells = <1>;
|
||||||
#size-cells = <2>;
|
#size-cells = <2>;
|
||||||
|
|
@ -350,4 +421,68 @@
|
||||||
compatible = "fsl,mpc8349-pci";
|
compatible = "fsl,mpc8349-pci";
|
||||||
device_type = "pci";
|
device_type = "pci";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
pci1: pcie@e0009000 {
|
||||||
|
#address-cells = <3>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
#interrupt-cells = <1>;
|
||||||
|
device_type = "pci";
|
||||||
|
compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
|
||||||
|
reg = <0xe0009000 0x00001000>;
|
||||||
|
ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
|
||||||
|
0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
|
||||||
|
bus-range = <0 255>;
|
||||||
|
interrupt-map-mask = <0xf800 0 0 7>;
|
||||||
|
interrupt-map = <0 0 0 1 &ipic 1 8
|
||||||
|
0 0 0 2 &ipic 1 8
|
||||||
|
0 0 0 3 &ipic 1 8
|
||||||
|
0 0 0 4 &ipic 1 8>;
|
||||||
|
sleep = <&pmc 0x00300000>;
|
||||||
|
clock-frequency = <0>;
|
||||||
|
|
||||||
|
pcie@0 {
|
||||||
|
#address-cells = <3>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
device_type = "pci";
|
||||||
|
reg = <0 0 0 0 0>;
|
||||||
|
ranges = <0x02000000 0 0xa8000000
|
||||||
|
0x02000000 0 0xa8000000
|
||||||
|
0 0x10000000
|
||||||
|
0x01000000 0 0x00000000
|
||||||
|
0x01000000 0 0x00000000
|
||||||
|
0 0x00800000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
pci2: pcie@e000a000 {
|
||||||
|
#address-cells = <3>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
#interrupt-cells = <1>;
|
||||||
|
device_type = "pci";
|
||||||
|
compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
|
||||||
|
reg = <0xe000a000 0x00001000>;
|
||||||
|
ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
|
||||||
|
0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
|
||||||
|
bus-range = <0 255>;
|
||||||
|
interrupt-map-mask = <0xf800 0 0 7>;
|
||||||
|
interrupt-map = <0 0 0 1 &ipic 2 8
|
||||||
|
0 0 0 2 &ipic 2 8
|
||||||
|
0 0 0 3 &ipic 2 8
|
||||||
|
0 0 0 4 &ipic 2 8>;
|
||||||
|
sleep = <&pmc 0x000c0000>;
|
||||||
|
clock-frequency = <0>;
|
||||||
|
|
||||||
|
pcie@0 {
|
||||||
|
#address-cells = <3>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
device_type = "pci";
|
||||||
|
reg = <0 0 0 0 0>;
|
||||||
|
ranges = <0x02000000 0 0xc8000000
|
||||||
|
0x02000000 0 0xc8000000
|
||||||
|
0 0x10000000
|
||||||
|
0x01000000 0 0x00000000
|
||||||
|
0x01000000 0 0x00000000
|
||||||
|
0 0x00800000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
|
||||||
|
|
@ -23,6 +23,8 @@
|
||||||
serial0 = &serial0;
|
serial0 = &serial0;
|
||||||
serial1 = &serial1;
|
serial1 = &serial1;
|
||||||
pci0 = &pci0;
|
pci0 = &pci0;
|
||||||
|
pci1 = &pci1;
|
||||||
|
pci2 = &pci2;
|
||||||
};
|
};
|
||||||
|
|
||||||
cpus {
|
cpus {
|
||||||
|
|
@ -127,21 +129,38 @@
|
||||||
reg = <0x200 0x100>;
|
reg = <0x200 0x100>;
|
||||||
};
|
};
|
||||||
|
|
||||||
i2c@3000 {
|
sleep-nexus {
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <0>;
|
#size-cells = <1>;
|
||||||
cell-index = <0>;
|
compatible = "simple-bus";
|
||||||
compatible = "fsl-i2c";
|
sleep = <&pmc 0x0c000000>;
|
||||||
reg = <0x3000 0x100>;
|
ranges;
|
||||||
interrupts = <14 0x8>;
|
|
||||||
interrupt-parent = <&ipic>;
|
|
||||||
dfsrr;
|
|
||||||
|
|
||||||
rtc@68 {
|
i2c@3000 {
|
||||||
compatible = "dallas,ds1374";
|
#address-cells = <1>;
|
||||||
reg = <0x68>;
|
#size-cells = <0>;
|
||||||
interrupts = <19 0x8>;
|
cell-index = <0>;
|
||||||
|
compatible = "fsl-i2c";
|
||||||
|
reg = <0x3000 0x100>;
|
||||||
|
interrupts = <14 0x8>;
|
||||||
interrupt-parent = <&ipic>;
|
interrupt-parent = <&ipic>;
|
||||||
|
dfsrr;
|
||||||
|
|
||||||
|
rtc@68 {
|
||||||
|
compatible = "dallas,ds1374";
|
||||||
|
reg = <0x68>;
|
||||||
|
interrupts = <19 0x8>;
|
||||||
|
interrupt-parent = <&ipic>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
sdhci@2e000 {
|
||||||
|
compatible = "fsl,mpc8378-esdhc", "fsl,mpc8379-esdhc";
|
||||||
|
reg = <0x2e000 0x1000>;
|
||||||
|
interrupts = <42 0x8>;
|
||||||
|
interrupt-parent = <&ipic>;
|
||||||
|
/* Filled in by U-Boot */
|
||||||
|
clock-frequency = <0>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -213,70 +232,83 @@
|
||||||
interrupts = <38 0x8>;
|
interrupts = <38 0x8>;
|
||||||
dr_mode = "host";
|
dr_mode = "host";
|
||||||
phy_type = "ulpi";
|
phy_type = "ulpi";
|
||||||
|
sleep = <&pmc 0x00c00000>;
|
||||||
};
|
};
|
||||||
|
|
||||||
mdio@24520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-mdio";
|
|
||||||
reg = <0x24520 0x20>;
|
|
||||||
phy2: ethernet-phy@2 {
|
|
||||||
interrupt-parent = <&ipic>;
|
|
||||||
interrupts = <17 0x8>;
|
|
||||||
reg = <0x2>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
phy3: ethernet-phy@3 {
|
|
||||||
interrupt-parent = <&ipic>;
|
|
||||||
interrupts = <18 0x8>;
|
|
||||||
reg = <0x3>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
tbi0: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
mdio@25520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-tbi";
|
|
||||||
reg = <0x25520 0x20>;
|
|
||||||
|
|
||||||
tbi1: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
|
|
||||||
enet0: ethernet@24000 {
|
enet0: ethernet@24000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <0>;
|
cell-index = <0>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "eTSEC";
|
model = "eTSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x24000 0x1000>;
|
reg = <0x24000 0x1000>;
|
||||||
|
ranges = <0x0 0x24000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <32 0x8 33 0x8 34 0x8>;
|
interrupts = <32 0x8 33 0x8 34 0x8>;
|
||||||
phy-connection-type = "mii";
|
phy-connection-type = "mii";
|
||||||
interrupt-parent = <&ipic>;
|
interrupt-parent = <&ipic>;
|
||||||
tbi-handle = <&tbi0>;
|
tbi-handle = <&tbi0>;
|
||||||
phy-handle = <&phy2>;
|
phy-handle = <&phy2>;
|
||||||
|
sleep = <&pmc 0xc0000000>;
|
||||||
|
fsl,magic-packet;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-mdio";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
phy2: ethernet-phy@2 {
|
||||||
|
interrupt-parent = <&ipic>;
|
||||||
|
interrupts = <17 0x8>;
|
||||||
|
reg = <0x2>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
|
||||||
|
phy3: ethernet-phy@3 {
|
||||||
|
interrupt-parent = <&ipic>;
|
||||||
|
interrupts = <18 0x8>;
|
||||||
|
reg = <0x3>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
|
||||||
|
tbi0: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
enet1: ethernet@25000 {
|
enet1: ethernet@25000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <1>;
|
cell-index = <1>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "eTSEC";
|
model = "eTSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x25000 0x1000>;
|
reg = <0x25000 0x1000>;
|
||||||
|
ranges = <0x0 0x25000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <35 0x8 36 0x8 37 0x8>;
|
interrupts = <35 0x8 36 0x8 37 0x8>;
|
||||||
phy-connection-type = "mii";
|
phy-connection-type = "mii";
|
||||||
interrupt-parent = <&ipic>;
|
interrupt-parent = <&ipic>;
|
||||||
tbi-handle = <&tbi1>;
|
tbi-handle = <&tbi1>;
|
||||||
phy-handle = <&phy3>;
|
phy-handle = <&phy3>;
|
||||||
|
sleep = <&pmc 0x30000000>;
|
||||||
|
fsl,magic-packet;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-tbi";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
tbi1: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
serial0: serial@4500 {
|
serial0: serial@4500 {
|
||||||
|
|
@ -309,14 +341,7 @@
|
||||||
fsl,channel-fifo-len = <24>;
|
fsl,channel-fifo-len = <24>;
|
||||||
fsl,exec-units-mask = <0x9fe>;
|
fsl,exec-units-mask = <0x9fe>;
|
||||||
fsl,descriptor-types-mask = <0x3ab0ebf>;
|
fsl,descriptor-types-mask = <0x3ab0ebf>;
|
||||||
};
|
sleep = <&pmc 0x03000000>;
|
||||||
|
|
||||||
sdhc@2e000 {
|
|
||||||
model = "eSDHC";
|
|
||||||
compatible = "fsl,esdhc";
|
|
||||||
reg = <0x2e000 0x1000>;
|
|
||||||
interrupts = <42 0x8>;
|
|
||||||
interrupt-parent = <&ipic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
/* IPIC
|
/* IPIC
|
||||||
|
|
@ -332,6 +357,13 @@
|
||||||
#interrupt-cells = <2>;
|
#interrupt-cells = <2>;
|
||||||
reg = <0x700 0x100>;
|
reg = <0x700 0x100>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
pmc: power@b00 {
|
||||||
|
compatible = "fsl,mpc8378-pmc", "fsl,mpc8349-pmc";
|
||||||
|
reg = <0xb00 0x100 0xa00 0x100>;
|
||||||
|
interrupts = <80 0x8>;
|
||||||
|
interrupt-parent = <&ipic>;
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
pci0: pci@e0008500 {
|
pci0: pci@e0008500 {
|
||||||
|
|
@ -387,6 +419,7 @@
|
||||||
0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
|
0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
|
||||||
0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
|
0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
|
||||||
clock-frequency = <0>;
|
clock-frequency = <0>;
|
||||||
|
sleep = <&pmc 0x00010000>;
|
||||||
#interrupt-cells = <1>;
|
#interrupt-cells = <1>;
|
||||||
#size-cells = <2>;
|
#size-cells = <2>;
|
||||||
#address-cells = <3>;
|
#address-cells = <3>;
|
||||||
|
|
@ -395,4 +428,68 @@
|
||||||
compatible = "fsl,mpc8349-pci";
|
compatible = "fsl,mpc8349-pci";
|
||||||
device_type = "pci";
|
device_type = "pci";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
pci1: pcie@e0009000 {
|
||||||
|
#address-cells = <3>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
#interrupt-cells = <1>;
|
||||||
|
device_type = "pci";
|
||||||
|
compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie";
|
||||||
|
reg = <0xe0009000 0x00001000>;
|
||||||
|
ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
|
||||||
|
0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
|
||||||
|
bus-range = <0 255>;
|
||||||
|
interrupt-map-mask = <0xf800 0 0 7>;
|
||||||
|
interrupt-map = <0 0 0 1 &ipic 1 8
|
||||||
|
0 0 0 2 &ipic 1 8
|
||||||
|
0 0 0 3 &ipic 1 8
|
||||||
|
0 0 0 4 &ipic 1 8>;
|
||||||
|
sleep = <&pmc 0x00300000>;
|
||||||
|
clock-frequency = <0>;
|
||||||
|
|
||||||
|
pcie@0 {
|
||||||
|
#address-cells = <3>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
device_type = "pci";
|
||||||
|
reg = <0 0 0 0 0>;
|
||||||
|
ranges = <0x02000000 0 0xa8000000
|
||||||
|
0x02000000 0 0xa8000000
|
||||||
|
0 0x10000000
|
||||||
|
0x01000000 0 0x00000000
|
||||||
|
0x01000000 0 0x00000000
|
||||||
|
0 0x00800000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
pci2: pcie@e000a000 {
|
||||||
|
#address-cells = <3>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
#interrupt-cells = <1>;
|
||||||
|
device_type = "pci";
|
||||||
|
compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie";
|
||||||
|
reg = <0xe000a000 0x00001000>;
|
||||||
|
ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
|
||||||
|
0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
|
||||||
|
bus-range = <0 255>;
|
||||||
|
interrupt-map-mask = <0xf800 0 0 7>;
|
||||||
|
interrupt-map = <0 0 0 1 &ipic 2 8
|
||||||
|
0 0 0 2 &ipic 2 8
|
||||||
|
0 0 0 3 &ipic 2 8
|
||||||
|
0 0 0 4 &ipic 2 8>;
|
||||||
|
sleep = <&pmc 0x000c0000>;
|
||||||
|
clock-frequency = <0>;
|
||||||
|
|
||||||
|
pcie@0 {
|
||||||
|
#address-cells = <3>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
device_type = "pci";
|
||||||
|
reg = <0 0 0 0 0>;
|
||||||
|
ranges = <0x02000000 0 0xc8000000
|
||||||
|
0x02000000 0 0xc8000000
|
||||||
|
0 0x10000000
|
||||||
|
0x01000000 0 0x00000000
|
||||||
|
0x01000000 0 0x00000000
|
||||||
|
0 0x00800000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
|
||||||
|
|
@ -22,6 +22,8 @@
|
||||||
serial0 = &serial0;
|
serial0 = &serial0;
|
||||||
serial1 = &serial1;
|
serial1 = &serial1;
|
||||||
pci0 = &pci0;
|
pci0 = &pci0;
|
||||||
|
pci1 = &pci1;
|
||||||
|
pci2 = &pci2;
|
||||||
};
|
};
|
||||||
|
|
||||||
cpus {
|
cpus {
|
||||||
|
|
@ -107,26 +109,72 @@
|
||||||
reg = <0x200 0x100>;
|
reg = <0x200 0x100>;
|
||||||
};
|
};
|
||||||
|
|
||||||
i2c@3000 {
|
gpio1: gpio-controller@c00 {
|
||||||
#address-cells = <1>;
|
#gpio-cells = <2>;
|
||||||
#size-cells = <0>;
|
compatible = "fsl,mpc8378-gpio", "fsl,mpc8349-gpio";
|
||||||
cell-index = <0>;
|
reg = <0xc00 0x100>;
|
||||||
compatible = "fsl-i2c";
|
interrupts = <74 0x8>;
|
||||||
reg = <0x3000 0x100>;
|
|
||||||
interrupts = <14 0x8>;
|
|
||||||
interrupt-parent = <&ipic>;
|
interrupt-parent = <&ipic>;
|
||||||
dfsrr;
|
gpio-controller;
|
||||||
rtc@68 {
|
};
|
||||||
compatible = "dallas,ds1339";
|
|
||||||
reg = <0x68>;
|
gpio2: gpio-controller@d00 {
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
compatible = "fsl,mpc8378-gpio", "fsl,mpc8349-gpio";
|
||||||
|
reg = <0xd00 0x100>;
|
||||||
|
interrupts = <75 0x8>;
|
||||||
|
interrupt-parent = <&ipic>;
|
||||||
|
gpio-controller;
|
||||||
|
};
|
||||||
|
|
||||||
|
sleep-nexus {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
compatible = "simple-bus";
|
||||||
|
sleep = <&pmc 0x0c000000>;
|
||||||
|
ranges;
|
||||||
|
|
||||||
|
i2c@3000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
cell-index = <0>;
|
||||||
|
compatible = "fsl-i2c";
|
||||||
|
reg = <0x3000 0x100>;
|
||||||
|
interrupts = <14 0x8>;
|
||||||
|
interrupt-parent = <&ipic>;
|
||||||
|
dfsrr;
|
||||||
|
|
||||||
|
dtt@48 {
|
||||||
|
compatible = "national,lm75";
|
||||||
|
reg = <0x48>;
|
||||||
|
};
|
||||||
|
|
||||||
|
at24@50 {
|
||||||
|
compatible = "at24,24c256";
|
||||||
|
reg = <0x50>;
|
||||||
|
};
|
||||||
|
|
||||||
|
rtc@68 {
|
||||||
|
compatible = "dallas,ds1339";
|
||||||
|
reg = <0x68>;
|
||||||
|
};
|
||||||
|
|
||||||
|
mcu_pio: mcu@a {
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
compatible = "fsl,mc9s08qg8-mpc8378erdb",
|
||||||
|
"fsl,mcu-mpc8349emitx";
|
||||||
|
reg = <0x0a>;
|
||||||
|
gpio-controller;
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
mcu_pio: mcu@a {
|
sdhci@2e000 {
|
||||||
#gpio-cells = <2>;
|
compatible = "fsl,mpc8378-esdhc", "fsl,mpc8379-esdhc";
|
||||||
compatible = "fsl,mc9s08qg8-mpc8378erdb",
|
reg = <0x2e000 0x1000>;
|
||||||
"fsl,mcu-mpc8349emitx";
|
interrupts = <42 0x8>;
|
||||||
reg = <0x0a>;
|
interrupt-parent = <&ipic>;
|
||||||
gpio-controller;
|
/* Filled in by U-Boot */
|
||||||
|
clock-frequency = <0>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -197,62 +245,76 @@
|
||||||
interrupt-parent = <&ipic>;
|
interrupt-parent = <&ipic>;
|
||||||
interrupts = <38 0x8>;
|
interrupts = <38 0x8>;
|
||||||
phy_type = "ulpi";
|
phy_type = "ulpi";
|
||||||
|
sleep = <&pmc 0x00c00000>;
|
||||||
};
|
};
|
||||||
|
|
||||||
mdio@24520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-mdio";
|
|
||||||
reg = <0x24520 0x20>;
|
|
||||||
phy2: ethernet-phy@2 {
|
|
||||||
interrupt-parent = <&ipic>;
|
|
||||||
interrupts = <17 0x8>;
|
|
||||||
reg = <0x2>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
tbi0: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
mdio@25520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-tbi";
|
|
||||||
reg = <0x25520 0x20>;
|
|
||||||
|
|
||||||
tbi1: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
|
|
||||||
enet0: ethernet@24000 {
|
enet0: ethernet@24000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <0>;
|
cell-index = <0>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "eTSEC";
|
model = "eTSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x24000 0x1000>;
|
reg = <0x24000 0x1000>;
|
||||||
|
ranges = <0x0 0x24000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <32 0x8 33 0x8 34 0x8>;
|
interrupts = <32 0x8 33 0x8 34 0x8>;
|
||||||
phy-connection-type = "mii";
|
phy-connection-type = "mii";
|
||||||
interrupt-parent = <&ipic>;
|
interrupt-parent = <&ipic>;
|
||||||
|
tbi-handle = <&tbi0>;
|
||||||
phy-handle = <&phy2>;
|
phy-handle = <&phy2>;
|
||||||
|
sleep = <&pmc 0xc0000000>;
|
||||||
|
fsl,magic-packet;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-mdio";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
phy2: ethernet-phy@2 {
|
||||||
|
interrupt-parent = <&ipic>;
|
||||||
|
interrupts = <17 0x8>;
|
||||||
|
reg = <0x2>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
|
||||||
|
tbi0: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
enet1: ethernet@25000 {
|
enet1: ethernet@25000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <1>;
|
cell-index = <1>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "eTSEC";
|
model = "eTSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x25000 0x1000>;
|
reg = <0x25000 0x1000>;
|
||||||
|
ranges = <0x0 0x25000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <35 0x8 36 0x8 37 0x8>;
|
interrupts = <35 0x8 36 0x8 37 0x8>;
|
||||||
phy-connection-type = "mii";
|
phy-connection-type = "mii";
|
||||||
interrupt-parent = <&ipic>;
|
interrupt-parent = <&ipic>;
|
||||||
fixed-link = <1 1 1000 0 0>;
|
fixed-link = <1 1 1000 0 0>;
|
||||||
|
tbi-handle = <&tbi1>;
|
||||||
|
sleep = <&pmc 0x30000000>;
|
||||||
|
fsl,magic-packet;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-tbi";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
tbi1: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
serial0: serial@4500 {
|
serial0: serial@4500 {
|
||||||
|
|
@ -285,6 +347,7 @@
|
||||||
fsl,channel-fifo-len = <24>;
|
fsl,channel-fifo-len = <24>;
|
||||||
fsl,exec-units-mask = <0x9fe>;
|
fsl,exec-units-mask = <0x9fe>;
|
||||||
fsl,descriptor-types-mask = <0x3ab0ebf>;
|
fsl,descriptor-types-mask = <0x3ab0ebf>;
|
||||||
|
sleep = <&pmc 0x03000000>;
|
||||||
};
|
};
|
||||||
|
|
||||||
/* IPIC
|
/* IPIC
|
||||||
|
|
@ -300,6 +363,13 @@
|
||||||
#interrupt-cells = <2>;
|
#interrupt-cells = <2>;
|
||||||
reg = <0x700 0x100>;
|
reg = <0x700 0x100>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
pmc: power@b00 {
|
||||||
|
compatible = "fsl,mpc8378-pmc", "fsl,mpc8349-pmc";
|
||||||
|
reg = <0xb00 0x100 0xa00 0x100>;
|
||||||
|
interrupts = <80 0x8>;
|
||||||
|
interrupt-parent = <&ipic>;
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
pci0: pci@e0008500 {
|
pci0: pci@e0008500 {
|
||||||
|
|
@ -325,6 +395,7 @@
|
||||||
ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
|
ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
|
||||||
0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
|
0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
|
||||||
0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
|
0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
|
||||||
|
sleep = <&pmc 0x00010000>;
|
||||||
clock-frequency = <66666666>;
|
clock-frequency = <66666666>;
|
||||||
#interrupt-cells = <1>;
|
#interrupt-cells = <1>;
|
||||||
#size-cells = <2>;
|
#size-cells = <2>;
|
||||||
|
|
@ -334,4 +405,68 @@
|
||||||
compatible = "fsl,mpc8349-pci";
|
compatible = "fsl,mpc8349-pci";
|
||||||
device_type = "pci";
|
device_type = "pci";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
pci1: pcie@e0009000 {
|
||||||
|
#address-cells = <3>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
#interrupt-cells = <1>;
|
||||||
|
device_type = "pci";
|
||||||
|
compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie";
|
||||||
|
reg = <0xe0009000 0x00001000>;
|
||||||
|
ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
|
||||||
|
0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
|
||||||
|
bus-range = <0 255>;
|
||||||
|
interrupt-map-mask = <0xf800 0 0 7>;
|
||||||
|
interrupt-map = <0 0 0 1 &ipic 1 8
|
||||||
|
0 0 0 2 &ipic 1 8
|
||||||
|
0 0 0 3 &ipic 1 8
|
||||||
|
0 0 0 4 &ipic 1 8>;
|
||||||
|
sleep = <&pmc 0x00300000>;
|
||||||
|
clock-frequency = <0>;
|
||||||
|
|
||||||
|
pcie@0 {
|
||||||
|
#address-cells = <3>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
device_type = "pci";
|
||||||
|
reg = <0 0 0 0 0>;
|
||||||
|
ranges = <0x02000000 0 0xa8000000
|
||||||
|
0x02000000 0 0xa8000000
|
||||||
|
0 0x10000000
|
||||||
|
0x01000000 0 0x00000000
|
||||||
|
0x01000000 0 0x00000000
|
||||||
|
0 0x00800000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
pci2: pcie@e000a000 {
|
||||||
|
#address-cells = <3>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
#interrupt-cells = <1>;
|
||||||
|
device_type = "pci";
|
||||||
|
compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie";
|
||||||
|
reg = <0xe000a000 0x00001000>;
|
||||||
|
ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
|
||||||
|
0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
|
||||||
|
bus-range = <0 255>;
|
||||||
|
interrupt-map-mask = <0xf800 0 0 7>;
|
||||||
|
interrupt-map = <0 0 0 1 &ipic 2 8
|
||||||
|
0 0 0 2 &ipic 2 8
|
||||||
|
0 0 0 3 &ipic 2 8
|
||||||
|
0 0 0 4 &ipic 2 8>;
|
||||||
|
sleep = <&pmc 0x000c0000>;
|
||||||
|
clock-frequency = <0>;
|
||||||
|
|
||||||
|
pcie@0 {
|
||||||
|
#address-cells = <3>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
device_type = "pci";
|
||||||
|
reg = <0 0 0 0 0>;
|
||||||
|
ranges = <0x02000000 0 0xc8000000
|
||||||
|
0x02000000 0 0xc8000000
|
||||||
|
0 0x10000000
|
||||||
|
0x01000000 0 0x00000000
|
||||||
|
0x01000000 0 0x00000000
|
||||||
|
0 0x00800000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
|
||||||
|
|
@ -127,21 +127,38 @@
|
||||||
reg = <0x200 0x100>;
|
reg = <0x200 0x100>;
|
||||||
};
|
};
|
||||||
|
|
||||||
i2c@3000 {
|
sleep-nexus {
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <0>;
|
#size-cells = <1>;
|
||||||
cell-index = <0>;
|
compatible = "simple-bus";
|
||||||
compatible = "fsl-i2c";
|
sleep = <&pmc 0x0c000000>;
|
||||||
reg = <0x3000 0x100>;
|
ranges;
|
||||||
interrupts = <14 0x8>;
|
|
||||||
interrupt-parent = <&ipic>;
|
|
||||||
dfsrr;
|
|
||||||
|
|
||||||
rtc@68 {
|
i2c@3000 {
|
||||||
compatible = "dallas,ds1374";
|
#address-cells = <1>;
|
||||||
reg = <0x68>;
|
#size-cells = <0>;
|
||||||
interrupts = <19 0x8>;
|
cell-index = <0>;
|
||||||
|
compatible = "fsl-i2c";
|
||||||
|
reg = <0x3000 0x100>;
|
||||||
|
interrupts = <14 0x8>;
|
||||||
interrupt-parent = <&ipic>;
|
interrupt-parent = <&ipic>;
|
||||||
|
dfsrr;
|
||||||
|
|
||||||
|
rtc@68 {
|
||||||
|
compatible = "dallas,ds1374";
|
||||||
|
reg = <0x68>;
|
||||||
|
interrupts = <19 0x8>;
|
||||||
|
interrupt-parent = <&ipic>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
sdhci@2e000 {
|
||||||
|
compatible = "fsl,mpc8379-esdhc";
|
||||||
|
reg = <0x2e000 0x1000>;
|
||||||
|
interrupts = <42 0x8>;
|
||||||
|
interrupt-parent = <&ipic>;
|
||||||
|
/* Filled in by U-Boot */
|
||||||
|
clock-frequency = <0>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -213,69 +230,83 @@
|
||||||
interrupts = <38 0x8>;
|
interrupts = <38 0x8>;
|
||||||
dr_mode = "host";
|
dr_mode = "host";
|
||||||
phy_type = "ulpi";
|
phy_type = "ulpi";
|
||||||
};
|
sleep = <&pmc 0x00c00000>;
|
||||||
|
|
||||||
mdio@24520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-mdio";
|
|
||||||
reg = <0x24520 0x20>;
|
|
||||||
phy2: ethernet-phy@2 {
|
|
||||||
interrupt-parent = <&ipic>;
|
|
||||||
interrupts = <17 0x8>;
|
|
||||||
reg = <0x2>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
phy3: ethernet-phy@3 {
|
|
||||||
interrupt-parent = <&ipic>;
|
|
||||||
interrupts = <18 0x8>;
|
|
||||||
reg = <0x3>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
tbi0: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
mdio@25520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-tbi";
|
|
||||||
reg = <0x25520 0x20>;
|
|
||||||
|
|
||||||
tbi1: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
};
|
||||||
|
|
||||||
enet0: ethernet@24000 {
|
enet0: ethernet@24000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <0>;
|
cell-index = <0>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "eTSEC";
|
model = "eTSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x24000 0x1000>;
|
reg = <0x24000 0x1000>;
|
||||||
|
ranges = <0x0 0x24000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <32 0x8 33 0x8 34 0x8>;
|
interrupts = <32 0x8 33 0x8 34 0x8>;
|
||||||
phy-connection-type = "mii";
|
phy-connection-type = "mii";
|
||||||
interrupt-parent = <&ipic>;
|
interrupt-parent = <&ipic>;
|
||||||
tbi-handle = <&tbi0>;
|
tbi-handle = <&tbi0>;
|
||||||
phy-handle = <&phy2>;
|
phy-handle = <&phy2>;
|
||||||
|
sleep = <&pmc 0xc0000000>;
|
||||||
|
fsl,magic-packet;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-mdio";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
phy2: ethernet-phy@2 {
|
||||||
|
interrupt-parent = <&ipic>;
|
||||||
|
interrupts = <17 0x8>;
|
||||||
|
reg = <0x2>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
|
||||||
|
phy3: ethernet-phy@3 {
|
||||||
|
interrupt-parent = <&ipic>;
|
||||||
|
interrupts = <18 0x8>;
|
||||||
|
reg = <0x3>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
|
||||||
|
tbi0: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
enet1: ethernet@25000 {
|
enet1: ethernet@25000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <1>;
|
cell-index = <1>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "eTSEC";
|
model = "eTSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x25000 0x1000>;
|
reg = <0x25000 0x1000>;
|
||||||
|
ranges = <0x0 0x25000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <35 0x8 36 0x8 37 0x8>;
|
interrupts = <35 0x8 36 0x8 37 0x8>;
|
||||||
phy-connection-type = "mii";
|
phy-connection-type = "mii";
|
||||||
interrupt-parent = <&ipic>;
|
interrupt-parent = <&ipic>;
|
||||||
tbi-handle = <&tbi1>;
|
tbi-handle = <&tbi1>;
|
||||||
phy-handle = <&phy3>;
|
phy-handle = <&phy3>;
|
||||||
|
sleep = <&pmc 0x30000000>;
|
||||||
|
fsl,magic-packet;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-tbi";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
tbi1: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
serial0: serial@4500 {
|
serial0: serial@4500 {
|
||||||
|
|
@ -308,14 +339,7 @@
|
||||||
fsl,channel-fifo-len = <24>;
|
fsl,channel-fifo-len = <24>;
|
||||||
fsl,exec-units-mask = <0x9fe>;
|
fsl,exec-units-mask = <0x9fe>;
|
||||||
fsl,descriptor-types-mask = <0x3ab0ebf>;
|
fsl,descriptor-types-mask = <0x3ab0ebf>;
|
||||||
};
|
sleep = <&pmc 0x03000000>;
|
||||||
|
|
||||||
sdhc@2e000 {
|
|
||||||
model = "eSDHC";
|
|
||||||
compatible = "fsl,esdhc";
|
|
||||||
reg = <0x2e000 0x1000>;
|
|
||||||
interrupts = <42 0x8>;
|
|
||||||
interrupt-parent = <&ipic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
sata@18000 {
|
sata@18000 {
|
||||||
|
|
@ -323,6 +347,7 @@
|
||||||
reg = <0x18000 0x1000>;
|
reg = <0x18000 0x1000>;
|
||||||
interrupts = <44 0x8>;
|
interrupts = <44 0x8>;
|
||||||
interrupt-parent = <&ipic>;
|
interrupt-parent = <&ipic>;
|
||||||
|
sleep = <&pmc 0x000000c0>;
|
||||||
};
|
};
|
||||||
|
|
||||||
sata@19000 {
|
sata@19000 {
|
||||||
|
|
@ -330,6 +355,7 @@
|
||||||
reg = <0x19000 0x1000>;
|
reg = <0x19000 0x1000>;
|
||||||
interrupts = <45 0x8>;
|
interrupts = <45 0x8>;
|
||||||
interrupt-parent = <&ipic>;
|
interrupt-parent = <&ipic>;
|
||||||
|
sleep = <&pmc 0x00000030>;
|
||||||
};
|
};
|
||||||
|
|
||||||
sata@1a000 {
|
sata@1a000 {
|
||||||
|
|
@ -337,6 +363,7 @@
|
||||||
reg = <0x1a000 0x1000>;
|
reg = <0x1a000 0x1000>;
|
||||||
interrupts = <46 0x8>;
|
interrupts = <46 0x8>;
|
||||||
interrupt-parent = <&ipic>;
|
interrupt-parent = <&ipic>;
|
||||||
|
sleep = <&pmc 0x0000000c>;
|
||||||
};
|
};
|
||||||
|
|
||||||
sata@1b000 {
|
sata@1b000 {
|
||||||
|
|
@ -344,6 +371,7 @@
|
||||||
reg = <0x1b000 0x1000>;
|
reg = <0x1b000 0x1000>;
|
||||||
interrupts = <47 0x8>;
|
interrupts = <47 0x8>;
|
||||||
interrupt-parent = <&ipic>;
|
interrupt-parent = <&ipic>;
|
||||||
|
sleep = <&pmc 0x00000003>;
|
||||||
};
|
};
|
||||||
|
|
||||||
/* IPIC
|
/* IPIC
|
||||||
|
|
@ -359,6 +387,13 @@
|
||||||
#interrupt-cells = <2>;
|
#interrupt-cells = <2>;
|
||||||
reg = <0x700 0x100>;
|
reg = <0x700 0x100>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
pmc: power@b00 {
|
||||||
|
compatible = "fsl,mpc8379-pmc", "fsl,mpc8349-pmc";
|
||||||
|
reg = <0xb00 0x100 0xa00 0x100>;
|
||||||
|
interrupts = <80 0x8>;
|
||||||
|
interrupt-parent = <&ipic>;
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
pci0: pci@e0008500 {
|
pci0: pci@e0008500 {
|
||||||
|
|
@ -413,6 +448,7 @@
|
||||||
ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
|
ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
|
||||||
0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
|
0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
|
||||||
0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
|
0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
|
||||||
|
sleep = <&pmc 0x00010000>;
|
||||||
clock-frequency = <0>;
|
clock-frequency = <0>;
|
||||||
#interrupt-cells = <1>;
|
#interrupt-cells = <1>;
|
||||||
#size-cells = <2>;
|
#size-cells = <2>;
|
||||||
|
|
|
||||||
|
|
@ -107,26 +107,72 @@
|
||||||
reg = <0x200 0x100>;
|
reg = <0x200 0x100>;
|
||||||
};
|
};
|
||||||
|
|
||||||
i2c@3000 {
|
gpio1: gpio-controller@c00 {
|
||||||
#address-cells = <1>;
|
#gpio-cells = <2>;
|
||||||
#size-cells = <0>;
|
compatible = "fsl,mpc8379-gpio", "fsl,mpc8349-gpio";
|
||||||
cell-index = <0>;
|
reg = <0xc00 0x100>;
|
||||||
compatible = "fsl-i2c";
|
interrupts = <74 0x8>;
|
||||||
reg = <0x3000 0x100>;
|
|
||||||
interrupts = <14 0x8>;
|
|
||||||
interrupt-parent = <&ipic>;
|
interrupt-parent = <&ipic>;
|
||||||
dfsrr;
|
gpio-controller;
|
||||||
rtc@68 {
|
};
|
||||||
compatible = "dallas,ds1339";
|
|
||||||
reg = <0x68>;
|
gpio2: gpio-controller@d00 {
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
compatible = "fsl,mpc8379-gpio", "fsl,mpc8349-gpio";
|
||||||
|
reg = <0xd00 0x100>;
|
||||||
|
interrupts = <75 0x8>;
|
||||||
|
interrupt-parent = <&ipic>;
|
||||||
|
gpio-controller;
|
||||||
|
};
|
||||||
|
|
||||||
|
sleep-nexus {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
compatible = "simple-bus";
|
||||||
|
sleep = <&pmc 0x0c000000>;
|
||||||
|
ranges;
|
||||||
|
|
||||||
|
i2c@3000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
cell-index = <0>;
|
||||||
|
compatible = "fsl-i2c";
|
||||||
|
reg = <0x3000 0x100>;
|
||||||
|
interrupts = <14 0x8>;
|
||||||
|
interrupt-parent = <&ipic>;
|
||||||
|
dfsrr;
|
||||||
|
|
||||||
|
dtt@48 {
|
||||||
|
compatible = "national,lm75";
|
||||||
|
reg = <0x48>;
|
||||||
|
};
|
||||||
|
|
||||||
|
at24@50 {
|
||||||
|
compatible = "at24,24c256";
|
||||||
|
reg = <0x50>;
|
||||||
|
};
|
||||||
|
|
||||||
|
rtc@68 {
|
||||||
|
compatible = "dallas,ds1339";
|
||||||
|
reg = <0x68>;
|
||||||
|
};
|
||||||
|
|
||||||
|
mcu_pio: mcu@a {
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
compatible = "fsl,mc9s08qg8-mpc8379erdb",
|
||||||
|
"fsl,mcu-mpc8349emitx";
|
||||||
|
reg = <0x0a>;
|
||||||
|
gpio-controller;
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
mcu_pio: mcu@a {
|
sdhci@2e000 {
|
||||||
#gpio-cells = <2>;
|
compatible = "fsl,mpc8379-esdhc";
|
||||||
compatible = "fsl,mc9s08qg8-mpc8379erdb",
|
reg = <0x2e000 0x1000>;
|
||||||
"fsl,mcu-mpc8349emitx";
|
interrupts = <42 0x8>;
|
||||||
reg = <0x0a>;
|
interrupt-parent = <&ipic>;
|
||||||
gpio-controller;
|
/* Filled in by U-Boot */
|
||||||
|
clock-frequency = <0>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -197,63 +243,76 @@
|
||||||
interrupt-parent = <&ipic>;
|
interrupt-parent = <&ipic>;
|
||||||
interrupts = <38 0x8>;
|
interrupts = <38 0x8>;
|
||||||
phy_type = "ulpi";
|
phy_type = "ulpi";
|
||||||
};
|
sleep = <&pmc 0x00c00000>;
|
||||||
|
|
||||||
mdio@24520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-mdio";
|
|
||||||
reg = <0x24520 0x20>;
|
|
||||||
phy2: ethernet-phy@2 {
|
|
||||||
interrupt-parent = <&ipic>;
|
|
||||||
interrupts = <17 0x8>;
|
|
||||||
reg = <0x2>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
tbi0: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
mdio@25520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-tbi";
|
|
||||||
reg = <0x25520 0x20>;
|
|
||||||
|
|
||||||
tbi1: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
};
|
||||||
|
|
||||||
enet0: ethernet@24000 {
|
enet0: ethernet@24000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <0>;
|
cell-index = <0>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "eTSEC";
|
model = "eTSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x24000 0x1000>;
|
reg = <0x24000 0x1000>;
|
||||||
|
ranges = <0x0 0x24000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <32 0x8 33 0x8 34 0x8>;
|
interrupts = <32 0x8 33 0x8 34 0x8>;
|
||||||
phy-connection-type = "mii";
|
phy-connection-type = "mii";
|
||||||
interrupt-parent = <&ipic>;
|
interrupt-parent = <&ipic>;
|
||||||
tbi-handle = <&tbi0>;
|
tbi-handle = <&tbi0>;
|
||||||
phy-handle = <&phy2>;
|
phy-handle = <&phy2>;
|
||||||
|
sleep = <&pmc 0xc0000000>;
|
||||||
|
fsl,magic-packet;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-mdio";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
phy2: ethernet-phy@2 {
|
||||||
|
interrupt-parent = <&ipic>;
|
||||||
|
interrupts = <17 0x8>;
|
||||||
|
reg = <0x2>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
|
||||||
|
tbi0: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
enet1: ethernet@25000 {
|
enet1: ethernet@25000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <1>;
|
cell-index = <1>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "eTSEC";
|
model = "eTSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x25000 0x1000>;
|
reg = <0x25000 0x1000>;
|
||||||
|
ranges = <0x0 0x25000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <35 0x8 36 0x8 37 0x8>;
|
interrupts = <35 0x8 36 0x8 37 0x8>;
|
||||||
phy-connection-type = "mii";
|
phy-connection-type = "mii";
|
||||||
interrupt-parent = <&ipic>;
|
interrupt-parent = <&ipic>;
|
||||||
fixed-link = <1 1 1000 0 0>;
|
fixed-link = <1 1 1000 0 0>;
|
||||||
tbi-handle = <&tbi1>;
|
tbi-handle = <&tbi1>;
|
||||||
|
sleep = <&pmc 0x30000000>;
|
||||||
|
fsl,magic-packet;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-tbi";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
tbi1: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
serial0: serial@4500 {
|
serial0: serial@4500 {
|
||||||
|
|
@ -286,6 +345,7 @@
|
||||||
fsl,channel-fifo-len = <24>;
|
fsl,channel-fifo-len = <24>;
|
||||||
fsl,exec-units-mask = <0x9fe>;
|
fsl,exec-units-mask = <0x9fe>;
|
||||||
fsl,descriptor-types-mask = <0x3ab0ebf>;
|
fsl,descriptor-types-mask = <0x3ab0ebf>;
|
||||||
|
sleep = <&pmc 0x03000000>;
|
||||||
};
|
};
|
||||||
|
|
||||||
sata@18000 {
|
sata@18000 {
|
||||||
|
|
@ -293,6 +353,7 @@
|
||||||
reg = <0x18000 0x1000>;
|
reg = <0x18000 0x1000>;
|
||||||
interrupts = <44 0x8>;
|
interrupts = <44 0x8>;
|
||||||
interrupt-parent = <&ipic>;
|
interrupt-parent = <&ipic>;
|
||||||
|
sleep = <&pmc 0x000000c0>;
|
||||||
};
|
};
|
||||||
|
|
||||||
sata@19000 {
|
sata@19000 {
|
||||||
|
|
@ -300,6 +361,7 @@
|
||||||
reg = <0x19000 0x1000>;
|
reg = <0x19000 0x1000>;
|
||||||
interrupts = <45 0x8>;
|
interrupts = <45 0x8>;
|
||||||
interrupt-parent = <&ipic>;
|
interrupt-parent = <&ipic>;
|
||||||
|
sleep = <&pmc 0x00000030>;
|
||||||
};
|
};
|
||||||
|
|
||||||
sata@1a000 {
|
sata@1a000 {
|
||||||
|
|
@ -307,6 +369,7 @@
|
||||||
reg = <0x1a000 0x1000>;
|
reg = <0x1a000 0x1000>;
|
||||||
interrupts = <46 0x8>;
|
interrupts = <46 0x8>;
|
||||||
interrupt-parent = <&ipic>;
|
interrupt-parent = <&ipic>;
|
||||||
|
sleep = <&pmc 0x0000000c>;
|
||||||
};
|
};
|
||||||
|
|
||||||
sata@1b000 {
|
sata@1b000 {
|
||||||
|
|
@ -314,6 +377,7 @@
|
||||||
reg = <0x1b000 0x1000>;
|
reg = <0x1b000 0x1000>;
|
||||||
interrupts = <47 0x8>;
|
interrupts = <47 0x8>;
|
||||||
interrupt-parent = <&ipic>;
|
interrupt-parent = <&ipic>;
|
||||||
|
sleep = <&pmc 0x00000003>;
|
||||||
};
|
};
|
||||||
|
|
||||||
/* IPIC
|
/* IPIC
|
||||||
|
|
@ -329,6 +393,13 @@
|
||||||
#interrupt-cells = <2>;
|
#interrupt-cells = <2>;
|
||||||
reg = <0x700 0x100>;
|
reg = <0x700 0x100>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
pmc: power@b00 {
|
||||||
|
compatible = "fsl,mpc8379-pmc", "fsl,mpc8349-pmc";
|
||||||
|
reg = <0xb00 0x100 0xa00 0x100>;
|
||||||
|
interrupts = <80 0x8>;
|
||||||
|
interrupt-parent = <&ipic>;
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
pci0: pci@e0008500 {
|
pci0: pci@e0008500 {
|
||||||
|
|
@ -354,6 +425,7 @@
|
||||||
ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
|
ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
|
||||||
0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
|
0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
|
||||||
0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
|
0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
|
||||||
|
sleep = <&pmc 0x00010000>;
|
||||||
clock-frequency = <66666666>;
|
clock-frequency = <66666666>;
|
||||||
#interrupt-cells = <1>;
|
#interrupt-cells = <1>;
|
||||||
#size-cells = <2>;
|
#size-cells = <2>;
|
||||||
|
|
|
||||||
|
|
@ -137,42 +137,6 @@
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
mdio@24520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-mdio";
|
|
||||||
reg = <0x24520 0x20>;
|
|
||||||
|
|
||||||
phy0: ethernet-phy@0 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <10 0x1>;
|
|
||||||
reg = <0>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
phy1: ethernet-phy@1 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <10 0x1>;
|
|
||||||
reg = <1>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
tbi0: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
mdio@26520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-tbi";
|
|
||||||
reg = <0x26520 0x20>;
|
|
||||||
|
|
||||||
tbi1: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
usb@22000 {
|
usb@22000 {
|
||||||
compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
|
compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
|
||||||
reg = <0x22000 0x1000>;
|
reg = <0x22000 0x1000>;
|
||||||
|
|
@ -194,31 +158,73 @@
|
||||||
};
|
};
|
||||||
|
|
||||||
enet0: ethernet@24000 {
|
enet0: ethernet@24000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <0>;
|
cell-index = <0>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "eTSEC";
|
model = "eTSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x24000 0x1000>;
|
reg = <0x24000 0x1000>;
|
||||||
|
ranges = <0x0 0x24000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <29 2 30 2 34 2>;
|
interrupts = <29 2 30 2 34 2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
tbi-handle = <&tbi0>;
|
tbi-handle = <&tbi0>;
|
||||||
phy-handle = <&phy1>;
|
phy-handle = <&phy1>;
|
||||||
phy-connection-type = "rgmii-id";
|
phy-connection-type = "rgmii-id";
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-mdio";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
phy0: ethernet-phy@0 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <10 0x1>;
|
||||||
|
reg = <0>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
phy1: ethernet-phy@1 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <10 0x1>;
|
||||||
|
reg = <1>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
tbi0: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
enet1: ethernet@26000 {
|
enet1: ethernet@26000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <1>;
|
cell-index = <1>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "eTSEC";
|
model = "eTSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x26000 0x1000>;
|
reg = <0x26000 0x1000>;
|
||||||
|
ranges = <0x0 0x26000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <31 2 32 2 33 2>;
|
interrupts = <31 2 32 2 33 2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
tbi-handle = <&tbi1>;
|
tbi-handle = <&tbi1>;
|
||||||
phy-handle = <&phy0>;
|
phy-handle = <&phy0>;
|
||||||
phy-connection-type = "rgmii-id";
|
phy-connection-type = "rgmii-id";
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-tbi";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
tbi1: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
usb@2b000 {
|
usb@2b000 {
|
||||||
|
|
|
||||||
|
|
@ -126,97 +126,106 @@
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
mdio@24520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-mdio";
|
|
||||||
reg = <0x24520 0x20>;
|
|
||||||
|
|
||||||
phy0: ethernet-phy@0 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <5 1>;
|
|
||||||
reg = <0x0>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
phy1: ethernet-phy@1 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <5 1>;
|
|
||||||
reg = <0x1>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
phy3: ethernet-phy@3 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <7 1>;
|
|
||||||
reg = <0x3>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
tbi0: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
mdio@25520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-tbi";
|
|
||||||
reg = <0x25520 0x20>;
|
|
||||||
|
|
||||||
tbi1: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
mdio@26520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-tbi";
|
|
||||||
reg = <0x26520 0x20>;
|
|
||||||
|
|
||||||
tbi2: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
enet0: ethernet@24000 {
|
enet0: ethernet@24000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <0>;
|
cell-index = <0>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "TSEC";
|
model = "TSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x24000 0x1000>;
|
reg = <0x24000 0x1000>;
|
||||||
|
ranges = <0x0 0x24000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <29 2 30 2 34 2>;
|
interrupts = <29 2 30 2 34 2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
tbi-handle = <&tbi0>;
|
tbi-handle = <&tbi0>;
|
||||||
phy-handle = <&phy0>;
|
phy-handle = <&phy0>;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-mdio";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
phy0: ethernet-phy@0 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <5 1>;
|
||||||
|
reg = <0x0>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
phy1: ethernet-phy@1 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <5 1>;
|
||||||
|
reg = <0x1>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
phy3: ethernet-phy@3 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <7 1>;
|
||||||
|
reg = <0x3>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
tbi0: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
enet1: ethernet@25000 {
|
enet1: ethernet@25000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <1>;
|
cell-index = <1>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "TSEC";
|
model = "TSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x25000 0x1000>;
|
reg = <0x25000 0x1000>;
|
||||||
|
ranges = <0x0 0x25000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <35 2 36 2 40 2>;
|
interrupts = <35 2 36 2 40 2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
tbi-handle = <&tbi1>;
|
tbi-handle = <&tbi1>;
|
||||||
phy-handle = <&phy1>;
|
phy-handle = <&phy1>;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-tbi";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
tbi1: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
enet2: ethernet@26000 {
|
enet2: ethernet@26000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <2>;
|
cell-index = <2>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "FEC";
|
model = "FEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x26000 0x1000>;
|
reg = <0x26000 0x1000>;
|
||||||
|
ranges = <0x0 0x26000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <41 2>;
|
interrupts = <41 2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
tbi-handle = <&tbi2>;
|
tbi-handle = <&tbi2>;
|
||||||
phy-handle = <&phy3>;
|
phy-handle = <&phy3>;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-tbi";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
tbi2: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
serial0: serial@4500 {
|
serial0: serial@4500 {
|
||||||
|
|
|
||||||
|
|
@ -126,66 +126,72 @@
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
mdio@24520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-mdio";
|
|
||||||
reg = <0x24520 0x20>;
|
|
||||||
|
|
||||||
phy0: ethernet-phy@0 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <5 1>;
|
|
||||||
reg = <0x0>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
phy1: ethernet-phy@1 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <5 1>;
|
|
||||||
reg = <0x1>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
tbi0: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
mdio@25520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-tbi";
|
|
||||||
reg = <0x25520 0x20>;
|
|
||||||
|
|
||||||
tbi1: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
enet0: ethernet@24000 {
|
enet0: ethernet@24000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <0>;
|
cell-index = <0>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "TSEC";
|
model = "TSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x24000 0x1000>;
|
reg = <0x24000 0x1000>;
|
||||||
|
ranges = <0x0 0x24000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <29 2 30 2 34 2>;
|
interrupts = <29 2 30 2 34 2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
tbi-handle = <&tbi0>;
|
tbi-handle = <&tbi0>;
|
||||||
phy-handle = <&phy0>;
|
phy-handle = <&phy0>;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-mdio";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
phy0: ethernet-phy@0 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <5 1>;
|
||||||
|
reg = <0x0>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
phy1: ethernet-phy@1 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <5 1>;
|
||||||
|
reg = <0x1>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
tbi0: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
enet1: ethernet@25000 {
|
enet1: ethernet@25000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <1>;
|
cell-index = <1>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "TSEC";
|
model = "TSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x25000 0x1000>;
|
reg = <0x25000 0x1000>;
|
||||||
|
ranges = <0x0 0x25000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <35 2 36 2 40 2>;
|
interrupts = <35 2 36 2 40 2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
tbi-handle = <&tbi1>;
|
tbi-handle = <&tbi1>;
|
||||||
phy-handle = <&phy1>;
|
phy-handle = <&phy1>;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-tbi";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
tbi1: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
serial0: serial@4500 {
|
serial0: serial@4500 {
|
||||||
|
|
|
||||||
|
|
@ -98,44 +98,6 @@
|
||||||
dfsrr;
|
dfsrr;
|
||||||
};
|
};
|
||||||
|
|
||||||
mdio@24520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-mdio";
|
|
||||||
reg = <0x24520 0x20>;
|
|
||||||
|
|
||||||
phy0: ethernet-phy@0 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <10 1>;
|
|
||||||
reg = <0x0>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
phy1: ethernet-phy@1 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <10 1>;
|
|
||||||
reg = <0x1>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
|
|
||||||
tbi0: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
mdio@26520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-tbi";
|
|
||||||
reg = <0x26520 0x20>;
|
|
||||||
|
|
||||||
tbi1: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
|
|
||||||
dma@21300 {
|
dma@21300 {
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <1>;
|
#size-cells = <1>;
|
||||||
|
|
@ -178,31 +140,74 @@
|
||||||
};
|
};
|
||||||
|
|
||||||
enet0: ethernet@24000 {
|
enet0: ethernet@24000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <0>;
|
cell-index = <0>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "TSEC";
|
model = "TSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x24000 0x1000>;
|
reg = <0x24000 0x1000>;
|
||||||
|
ranges = <0x0 0x24000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <29 2 30 2 34 2>;
|
interrupts = <29 2 30 2 34 2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
phy-handle = <&phy0>;
|
phy-handle = <&phy0>;
|
||||||
tbi-handle = <&tbi0>;
|
tbi-handle = <&tbi0>;
|
||||||
phy-connection-type = "rgmii-id";
|
phy-connection-type = "rgmii-id";
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-mdio";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
phy0: ethernet-phy@0 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <10 1>;
|
||||||
|
reg = <0x0>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
phy1: ethernet-phy@1 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <10 1>;
|
||||||
|
reg = <0x1>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
|
||||||
|
tbi0: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
enet1: ethernet@26000 {
|
enet1: ethernet@26000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <1>;
|
cell-index = <1>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "TSEC";
|
model = "TSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x26000 0x1000>;
|
reg = <0x26000 0x1000>;
|
||||||
|
ranges = <0x0 0x26000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <31 2 32 2 33 2>;
|
interrupts = <31 2 32 2 33 2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
phy-handle = <&phy1>;
|
phy-handle = <&phy1>;
|
||||||
tbi-handle = <&tbi1>;
|
tbi-handle = <&tbi1>;
|
||||||
phy-connection-type = "rgmii-id";
|
phy-connection-type = "rgmii-id";
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-tbi";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
tbi1: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
serial0: serial@4500 {
|
serial0: serial@4500 {
|
||||||
|
|
|
||||||
|
|
@ -142,129 +142,141 @@
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
mdio@24520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-mdio";
|
|
||||||
reg = <0x24520 0x20>;
|
|
||||||
|
|
||||||
phy0: ethernet-phy@0 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <5 1>;
|
|
||||||
reg = <0x0>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
phy1: ethernet-phy@1 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <5 1>;
|
|
||||||
reg = <0x1>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
phy2: ethernet-phy@2 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <5 1>;
|
|
||||||
reg = <0x2>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
phy3: ethernet-phy@3 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <5 1>;
|
|
||||||
reg = <0x3>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
tbi0: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
mdio@25520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-tbi";
|
|
||||||
reg = <0x25520 0x20>;
|
|
||||||
|
|
||||||
tbi1: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
mdio@26520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-tbi";
|
|
||||||
reg = <0x26520 0x20>;
|
|
||||||
|
|
||||||
tbi2: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
mdio@27520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-tbi";
|
|
||||||
reg = <0x27520 0x20>;
|
|
||||||
|
|
||||||
tbi3: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
enet0: ethernet@24000 {
|
enet0: ethernet@24000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <0>;
|
cell-index = <0>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "eTSEC";
|
model = "eTSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x24000 0x1000>;
|
reg = <0x24000 0x1000>;
|
||||||
|
ranges = <0x0 0x24000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <29 2 30 2 34 2>;
|
interrupts = <29 2 30 2 34 2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
tbi-handle = <&tbi0>;
|
tbi-handle = <&tbi0>;
|
||||||
phy-handle = <&phy0>;
|
phy-handle = <&phy0>;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-mdio";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
phy0: ethernet-phy@0 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <5 1>;
|
||||||
|
reg = <0x0>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
phy1: ethernet-phy@1 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <5 1>;
|
||||||
|
reg = <0x1>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
phy2: ethernet-phy@2 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <5 1>;
|
||||||
|
reg = <0x2>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
phy3: ethernet-phy@3 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <5 1>;
|
||||||
|
reg = <0x3>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
tbi0: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
enet1: ethernet@25000 {
|
enet1: ethernet@25000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <1>;
|
cell-index = <1>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "eTSEC";
|
model = "eTSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x25000 0x1000>;
|
reg = <0x25000 0x1000>;
|
||||||
|
ranges = <0x0 0x25000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <35 2 36 2 40 2>;
|
interrupts = <35 2 36 2 40 2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
tbi-handle = <&tbi1>;
|
tbi-handle = <&tbi1>;
|
||||||
phy-handle = <&phy1>;
|
phy-handle = <&phy1>;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-tbi";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
tbi1: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
/* eTSEC 3/4 are currently broken
|
/* eTSEC 3/4 are currently broken
|
||||||
enet2: ethernet@26000 {
|
enet2: ethernet@26000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <2>;
|
cell-index = <2>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "eTSEC";
|
model = "eTSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x26000 0x1000>;
|
reg = <0x26000 0x1000>;
|
||||||
|
ranges = <0x0 0x26000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <31 2 32 2 33 2>;
|
interrupts = <31 2 32 2 33 2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
tbi-handle = <&tbi2>;
|
tbi-handle = <&tbi2>;
|
||||||
phy-handle = <&phy2>;
|
phy-handle = <&phy2>;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-tbi";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
tbi2: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
enet3: ethernet@27000 {
|
enet3: ethernet@27000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <3>;
|
cell-index = <3>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "eTSEC";
|
model = "eTSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x27000 0x1000>;
|
reg = <0x27000 0x1000>;
|
||||||
|
ranges = <0x0 0x27000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <37 2 38 2 39 2>;
|
interrupts = <37 2 38 2 39 2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
tbi-handle = <&tbi3>;
|
tbi-handle = <&tbi3>;
|
||||||
phy-handle = <&phy3>;
|
phy-handle = <&phy3>;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-tbi";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
tbi3: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -126,66 +126,72 @@
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
mdio@24520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-mdio";
|
|
||||||
reg = <0x24520 0x20>;
|
|
||||||
|
|
||||||
phy0: ethernet-phy@0 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <5 1>;
|
|
||||||
reg = <0x0>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
phy1: ethernet-phy@1 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <5 1>;
|
|
||||||
reg = <0x1>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
tbi0: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
mdio@25520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-tbi";
|
|
||||||
reg = <0x25520 0x20>;
|
|
||||||
|
|
||||||
tbi1: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
enet0: ethernet@24000 {
|
enet0: ethernet@24000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <0>;
|
cell-index = <0>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "TSEC";
|
model = "TSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x24000 0x1000>;
|
reg = <0x24000 0x1000>;
|
||||||
|
ranges = <0x0 0x24000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <29 2 30 2 34 2>;
|
interrupts = <29 2 30 2 34 2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
tbi-handle = <&tbi0>;
|
tbi-handle = <&tbi0>;
|
||||||
phy-handle = <&phy0>;
|
phy-handle = <&phy0>;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-mdio";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
phy0: ethernet-phy@0 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <5 1>;
|
||||||
|
reg = <0x0>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
phy1: ethernet-phy@1 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <5 1>;
|
||||||
|
reg = <0x1>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
tbi0: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
enet1: ethernet@25000 {
|
enet1: ethernet@25000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <1>;
|
cell-index = <1>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "TSEC";
|
model = "TSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x25000 0x1000>;
|
reg = <0x25000 0x1000>;
|
||||||
|
ranges = <0x0 0x25000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <35 2 36 2 40 2>;
|
interrupts = <35 2 36 2 40 2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
tbi-handle = <&tbi1>;
|
tbi-handle = <&tbi1>;
|
||||||
phy-handle = <&phy1>;
|
phy-handle = <&phy1>;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-tbi";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
tbi1: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
serial0: serial@4500 {
|
serial0: serial@4500 {
|
||||||
|
|
|
||||||
|
|
@ -115,78 +115,84 @@
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
mdio@24520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-mdio";
|
|
||||||
reg = <0x24520 0x20>;
|
|
||||||
|
|
||||||
phy0: ethernet-phy@0 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <5 1>;
|
|
||||||
reg = <0x0>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
phy1: ethernet-phy@1 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <5 1>;
|
|
||||||
reg = <0x1>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
phy2: ethernet-phy@2 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <7 1>;
|
|
||||||
reg = <0x2>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
phy3: ethernet-phy@3 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <7 1>;
|
|
||||||
reg = <0x3>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
tbi0: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
mdio@25520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-tbi";
|
|
||||||
reg = <0x25520 0x20>;
|
|
||||||
|
|
||||||
tbi1: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
enet0: ethernet@24000 {
|
enet0: ethernet@24000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <0>;
|
cell-index = <0>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "TSEC";
|
model = "TSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x24000 0x1000>;
|
reg = <0x24000 0x1000>;
|
||||||
|
ranges = <0x0 0x24000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <29 2 30 2 34 2>;
|
interrupts = <29 2 30 2 34 2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
tbi-handle = <&tbi0>;
|
tbi-handle = <&tbi0>;
|
||||||
phy-handle = <&phy0>;
|
phy-handle = <&phy0>;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-mdio";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
phy0: ethernet-phy@0 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <5 1>;
|
||||||
|
reg = <0x0>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
phy1: ethernet-phy@1 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <5 1>;
|
||||||
|
reg = <0x1>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
phy2: ethernet-phy@2 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <7 1>;
|
||||||
|
reg = <0x2>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
phy3: ethernet-phy@3 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <7 1>;
|
||||||
|
reg = <0x3>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
tbi0: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
enet1: ethernet@25000 {
|
enet1: ethernet@25000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <1>;
|
cell-index = <1>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "TSEC";
|
model = "TSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x25000 0x1000>;
|
reg = <0x25000 0x1000>;
|
||||||
|
ranges = <0x0 0x25000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <35 2 36 2 40 2>;
|
interrupts = <35 2 36 2 40 2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
tbi-handle = <&tbi1>;
|
tbi-handle = <&tbi1>;
|
||||||
phy-handle = <&phy1>;
|
phy-handle = <&phy1>;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-tbi";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
tbi1: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
mpic: pic@40000 {
|
mpic: pic@40000 {
|
||||||
|
|
|
||||||
|
|
@ -149,78 +149,84 @@
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
mdio@24520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-mdio";
|
|
||||||
reg = <0x24520 0x20>;
|
|
||||||
|
|
||||||
phy0: ethernet-phy@7 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <1 1>;
|
|
||||||
reg = <0x7>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
phy1: ethernet-phy@1 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <2 1>;
|
|
||||||
reg = <0x1>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
phy2: ethernet-phy@2 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <1 1>;
|
|
||||||
reg = <0x2>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
phy3: ethernet-phy@3 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <2 1>;
|
|
||||||
reg = <0x3>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
tbi0: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
mdio@25520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-tbi";
|
|
||||||
reg = <0x25520 0x20>;
|
|
||||||
|
|
||||||
tbi1: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
enet0: ethernet@24000 {
|
enet0: ethernet@24000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <0>;
|
cell-index = <0>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "eTSEC";
|
model = "eTSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x24000 0x1000>;
|
reg = <0x24000 0x1000>;
|
||||||
|
ranges = <0x0 0x24000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <29 2 30 2 34 2>;
|
interrupts = <29 2 30 2 34 2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
tbi-handle = <&tbi0>;
|
tbi-handle = <&tbi0>;
|
||||||
phy-handle = <&phy2>;
|
phy-handle = <&phy2>;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-mdio";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
phy0: ethernet-phy@7 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <1 1>;
|
||||||
|
reg = <0x7>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
phy1: ethernet-phy@1 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <2 1>;
|
||||||
|
reg = <0x1>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
phy2: ethernet-phy@2 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <1 1>;
|
||||||
|
reg = <0x2>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
phy3: ethernet-phy@3 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <2 1>;
|
||||||
|
reg = <0x3>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
tbi0: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
enet1: ethernet@25000 {
|
enet1: ethernet@25000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <1>;
|
cell-index = <1>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "eTSEC";
|
model = "eTSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x25000 0x1000>;
|
reg = <0x25000 0x1000>;
|
||||||
|
ranges = <0x0 0x25000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <35 2 36 2 40 2>;
|
interrupts = <35 2 36 2 40 2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
tbi-handle = <&tbi1>;
|
tbi-handle = <&tbi1>;
|
||||||
phy-handle = <&phy3>;
|
phy-handle = <&phy3>;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-tbi";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
tbi1: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
serial0: serial@4500 {
|
serial0: serial@4500 {
|
||||||
|
|
|
||||||
|
|
@ -1,7 +1,7 @@
|
||||||
/*
|
/*
|
||||||
* MPC8572 DS Device Tree Source
|
* MPC8572 DS Device Tree Source
|
||||||
*
|
*
|
||||||
* Copyright 2007, 2008 Freescale Semiconductor Inc.
|
* Copyright 2007-2009 Freescale Semiconductor Inc.
|
||||||
*
|
*
|
||||||
* This program is free software; you can redistribute it and/or modify it
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
* under the terms of the GNU General Public License as published by the
|
* under the terms of the GNU General Public License as published by the
|
||||||
|
|
@ -312,129 +312,141 @@
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
mdio@24520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-mdio";
|
|
||||||
reg = <0x24520 0x20>;
|
|
||||||
|
|
||||||
phy0: ethernet-phy@0 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <10 1>;
|
|
||||||
reg = <0x0>;
|
|
||||||
};
|
|
||||||
phy1: ethernet-phy@1 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <10 1>;
|
|
||||||
reg = <0x1>;
|
|
||||||
};
|
|
||||||
phy2: ethernet-phy@2 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <10 1>;
|
|
||||||
reg = <0x2>;
|
|
||||||
};
|
|
||||||
phy3: ethernet-phy@3 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <10 1>;
|
|
||||||
reg = <0x3>;
|
|
||||||
};
|
|
||||||
|
|
||||||
tbi0: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
mdio@25520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-tbi";
|
|
||||||
reg = <0x25520 0x20>;
|
|
||||||
|
|
||||||
tbi1: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
mdio@26520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-tbi";
|
|
||||||
reg = <0x26520 0x20>;
|
|
||||||
|
|
||||||
tbi2: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
mdio@27520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-tbi";
|
|
||||||
reg = <0x27520 0x20>;
|
|
||||||
|
|
||||||
tbi3: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
enet0: ethernet@24000 {
|
enet0: ethernet@24000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <0>;
|
cell-index = <0>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "eTSEC";
|
model = "eTSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x24000 0x1000>;
|
reg = <0x24000 0x1000>;
|
||||||
|
ranges = <0x0 0x24000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <29 2 30 2 34 2>;
|
interrupts = <29 2 30 2 34 2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
tbi-handle = <&tbi0>;
|
tbi-handle = <&tbi0>;
|
||||||
phy-handle = <&phy0>;
|
phy-handle = <&phy0>;
|
||||||
phy-connection-type = "rgmii-id";
|
phy-connection-type = "rgmii-id";
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-mdio";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
phy0: ethernet-phy@0 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <10 1>;
|
||||||
|
reg = <0x0>;
|
||||||
|
};
|
||||||
|
phy1: ethernet-phy@1 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <10 1>;
|
||||||
|
reg = <0x1>;
|
||||||
|
};
|
||||||
|
phy2: ethernet-phy@2 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <10 1>;
|
||||||
|
reg = <0x2>;
|
||||||
|
};
|
||||||
|
phy3: ethernet-phy@3 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <10 1>;
|
||||||
|
reg = <0x3>;
|
||||||
|
};
|
||||||
|
|
||||||
|
tbi0: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
enet1: ethernet@25000 {
|
enet1: ethernet@25000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <1>;
|
cell-index = <1>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "eTSEC";
|
model = "eTSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x25000 0x1000>;
|
reg = <0x25000 0x1000>;
|
||||||
|
ranges = <0x0 0x25000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <35 2 36 2 40 2>;
|
interrupts = <35 2 36 2 40 2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
tbi-handle = <&tbi1>;
|
tbi-handle = <&tbi1>;
|
||||||
phy-handle = <&phy1>;
|
phy-handle = <&phy1>;
|
||||||
phy-connection-type = "rgmii-id";
|
phy-connection-type = "rgmii-id";
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-tbi";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
tbi1: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
enet2: ethernet@26000 {
|
enet2: ethernet@26000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <2>;
|
cell-index = <2>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "eTSEC";
|
model = "eTSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x26000 0x1000>;
|
reg = <0x26000 0x1000>;
|
||||||
|
ranges = <0x0 0x26000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <31 2 32 2 33 2>;
|
interrupts = <31 2 32 2 33 2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
tbi-handle = <&tbi2>;
|
tbi-handle = <&tbi2>;
|
||||||
phy-handle = <&phy2>;
|
phy-handle = <&phy2>;
|
||||||
phy-connection-type = "rgmii-id";
|
phy-connection-type = "rgmii-id";
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-tbi";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
tbi2: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
enet3: ethernet@27000 {
|
enet3: ethernet@27000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <3>;
|
cell-index = <3>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "eTSEC";
|
model = "eTSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x27000 0x1000>;
|
reg = <0x27000 0x1000>;
|
||||||
|
ranges = <0x0 0x27000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <37 2 38 2 39 2>;
|
interrupts = <37 2 38 2 39 2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
tbi-handle = <&tbi3>;
|
tbi-handle = <&tbi3>;
|
||||||
phy-handle = <&phy3>;
|
phy-handle = <&phy3>;
|
||||||
phy-connection-type = "rgmii-id";
|
phy-connection-type = "rgmii-id";
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-tbi";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
tbi3: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
serial0: serial@4500 {
|
serial0: serial@4500 {
|
||||||
|
|
@ -643,7 +655,7 @@
|
||||||
|
|
||||||
0x1000000 0x0 0x0
|
0x1000000 0x0 0x0
|
||||||
0x1000000 0x0 0x0
|
0x1000000 0x0 0x0
|
||||||
0x0 0x100000>;
|
0x0 0x10000>;
|
||||||
uli1575@0 {
|
uli1575@0 {
|
||||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||||
#size-cells = <2>;
|
#size-cells = <2>;
|
||||||
|
|
@ -654,7 +666,7 @@
|
||||||
|
|
||||||
0x1000000 0x0 0x0
|
0x1000000 0x0 0x0
|
||||||
0x1000000 0x0 0x0
|
0x1000000 0x0 0x0
|
||||||
0x0 0x100000>;
|
0x0 0x10000>;
|
||||||
isa@1e {
|
isa@1e {
|
||||||
device_type = "isa";
|
device_type = "isa";
|
||||||
#interrupt-cells = <2>;
|
#interrupt-cells = <2>;
|
||||||
|
|
@ -744,7 +756,7 @@
|
||||||
|
|
||||||
0x1000000 0x0 0x0
|
0x1000000 0x0 0x0
|
||||||
0x1000000 0x0 0x0
|
0x1000000 0x0 0x0
|
||||||
0x0 0x100000>;
|
0x0 0x10000>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -781,7 +793,7 @@
|
||||||
|
|
||||||
0x1000000 0x0 0x0
|
0x1000000 0x0 0x0
|
||||||
0x1000000 0x0 0x0
|
0x1000000 0x0 0x0
|
||||||
0x0 0x100000>;
|
0x0 0x10000>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,799 @@
|
||||||
|
/*
|
||||||
|
* MPC8572 DS Device Tree Source
|
||||||
|
*
|
||||||
|
* Copyright 2007-2009 Freescale Semiconductor Inc.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms of the GNU General Public License as published by the
|
||||||
|
* Free Software Foundation; either version 2 of the License, or (at your
|
||||||
|
* option) any later version.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
/ {
|
||||||
|
model = "fsl,MPC8572DS";
|
||||||
|
compatible = "fsl,MPC8572DS";
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
|
||||||
|
aliases {
|
||||||
|
ethernet0 = &enet0;
|
||||||
|
ethernet1 = &enet1;
|
||||||
|
ethernet2 = &enet2;
|
||||||
|
ethernet3 = &enet3;
|
||||||
|
serial0 = &serial0;
|
||||||
|
serial1 = &serial1;
|
||||||
|
pci0 = &pci0;
|
||||||
|
pci1 = &pci1;
|
||||||
|
pci2 = &pci2;
|
||||||
|
};
|
||||||
|
|
||||||
|
cpus {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
PowerPC,8572@0 {
|
||||||
|
device_type = "cpu";
|
||||||
|
reg = <0x0>;
|
||||||
|
d-cache-line-size = <32>; // 32 bytes
|
||||||
|
i-cache-line-size = <32>; // 32 bytes
|
||||||
|
d-cache-size = <0x8000>; // L1, 32K
|
||||||
|
i-cache-size = <0x8000>; // L1, 32K
|
||||||
|
timebase-frequency = <0>;
|
||||||
|
bus-frequency = <0>;
|
||||||
|
clock-frequency = <0>;
|
||||||
|
next-level-cache = <&L2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
PowerPC,8572@1 {
|
||||||
|
device_type = "cpu";
|
||||||
|
reg = <0x1>;
|
||||||
|
d-cache-line-size = <32>; // 32 bytes
|
||||||
|
i-cache-line-size = <32>; // 32 bytes
|
||||||
|
d-cache-size = <0x8000>; // L1, 32K
|
||||||
|
i-cache-size = <0x8000>; // L1, 32K
|
||||||
|
timebase-frequency = <0>;
|
||||||
|
bus-frequency = <0>;
|
||||||
|
clock-frequency = <0>;
|
||||||
|
next-level-cache = <&L2>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
memory {
|
||||||
|
device_type = "memory";
|
||||||
|
};
|
||||||
|
|
||||||
|
localbus@fffe05000 {
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
|
||||||
|
reg = <0xf 0xffe05000 0 0x1000>;
|
||||||
|
interrupts = <19 2>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
|
||||||
|
ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
|
||||||
|
0x1 0x0 0xf 0xe0000000 0x08000000
|
||||||
|
0x2 0x0 0xf 0xffa00000 0x00040000
|
||||||
|
0x3 0x0 0xf 0xffdf0000 0x00008000
|
||||||
|
0x4 0x0 0xf 0xffa40000 0x00040000
|
||||||
|
0x5 0x0 0xf 0xffa80000 0x00040000
|
||||||
|
0x6 0x0 0xf 0xffac0000 0x00040000>;
|
||||||
|
|
||||||
|
nor@0,0 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
compatible = "cfi-flash";
|
||||||
|
reg = <0x0 0x0 0x8000000>;
|
||||||
|
bank-width = <2>;
|
||||||
|
device-width = <1>;
|
||||||
|
|
||||||
|
ramdisk@0 {
|
||||||
|
reg = <0x0 0x03000000>;
|
||||||
|
read-only;
|
||||||
|
};
|
||||||
|
|
||||||
|
diagnostic@3000000 {
|
||||||
|
reg = <0x03000000 0x00e00000>;
|
||||||
|
read-only;
|
||||||
|
};
|
||||||
|
|
||||||
|
dink@3e00000 {
|
||||||
|
reg = <0x03e00000 0x00200000>;
|
||||||
|
read-only;
|
||||||
|
};
|
||||||
|
|
||||||
|
kernel@4000000 {
|
||||||
|
reg = <0x04000000 0x00400000>;
|
||||||
|
read-only;
|
||||||
|
};
|
||||||
|
|
||||||
|
jffs2@4400000 {
|
||||||
|
reg = <0x04400000 0x03b00000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
dtb@7f00000 {
|
||||||
|
reg = <0x07f00000 0x00080000>;
|
||||||
|
read-only;
|
||||||
|
};
|
||||||
|
|
||||||
|
u-boot@7f80000 {
|
||||||
|
reg = <0x07f80000 0x00080000>;
|
||||||
|
read-only;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
nand@2,0 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
compatible = "fsl,mpc8572-fcm-nand",
|
||||||
|
"fsl,elbc-fcm-nand";
|
||||||
|
reg = <0x2 0x0 0x40000>;
|
||||||
|
|
||||||
|
u-boot@0 {
|
||||||
|
reg = <0x0 0x02000000>;
|
||||||
|
read-only;
|
||||||
|
};
|
||||||
|
|
||||||
|
jffs2@2000000 {
|
||||||
|
reg = <0x02000000 0x10000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
ramdisk@12000000 {
|
||||||
|
reg = <0x12000000 0x08000000>;
|
||||||
|
read-only;
|
||||||
|
};
|
||||||
|
|
||||||
|
kernel@1a000000 {
|
||||||
|
reg = <0x1a000000 0x04000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
dtb@1e000000 {
|
||||||
|
reg = <0x1e000000 0x01000000>;
|
||||||
|
read-only;
|
||||||
|
};
|
||||||
|
|
||||||
|
empty@1f000000 {
|
||||||
|
reg = <0x1f000000 0x21000000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
nand@4,0 {
|
||||||
|
compatible = "fsl,mpc8572-fcm-nand",
|
||||||
|
"fsl,elbc-fcm-nand";
|
||||||
|
reg = <0x4 0x0 0x40000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
nand@5,0 {
|
||||||
|
compatible = "fsl,mpc8572-fcm-nand",
|
||||||
|
"fsl,elbc-fcm-nand";
|
||||||
|
reg = <0x5 0x0 0x40000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
nand@6,0 {
|
||||||
|
compatible = "fsl,mpc8572-fcm-nand",
|
||||||
|
"fsl,elbc-fcm-nand";
|
||||||
|
reg = <0x6 0x0 0x40000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
soc8572@fffe00000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
device_type = "soc";
|
||||||
|
compatible = "simple-bus";
|
||||||
|
ranges = <0x0 0xf 0xffe00000 0x100000>;
|
||||||
|
reg = <0xf 0xffe00000 0 0x1000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed
|
||||||
|
bus-frequency = <0>; // Filled out by uboot.
|
||||||
|
|
||||||
|
memory-controller@2000 {
|
||||||
|
compatible = "fsl,mpc8572-memory-controller";
|
||||||
|
reg = <0x2000 0x1000>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <18 2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
memory-controller@6000 {
|
||||||
|
compatible = "fsl,mpc8572-memory-controller";
|
||||||
|
reg = <0x6000 0x1000>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <18 2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
L2: l2-cache-controller@20000 {
|
||||||
|
compatible = "fsl,mpc8572-l2-cache-controller";
|
||||||
|
reg = <0x20000 0x1000>;
|
||||||
|
cache-line-size = <32>; // 32 bytes
|
||||||
|
cache-size = <0x100000>; // L2, 1M
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <16 2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
i2c@3000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
cell-index = <0>;
|
||||||
|
compatible = "fsl-i2c";
|
||||||
|
reg = <0x3000 0x100>;
|
||||||
|
interrupts = <43 2>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
dfsrr;
|
||||||
|
};
|
||||||
|
|
||||||
|
i2c@3100 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
cell-index = <1>;
|
||||||
|
compatible = "fsl-i2c";
|
||||||
|
reg = <0x3100 0x100>;
|
||||||
|
interrupts = <43 2>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
dfsrr;
|
||||||
|
};
|
||||||
|
|
||||||
|
dma@c300 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
|
||||||
|
reg = <0xc300 0x4>;
|
||||||
|
ranges = <0x0 0xc100 0x200>;
|
||||||
|
cell-index = <1>;
|
||||||
|
dma-channel@0 {
|
||||||
|
compatible = "fsl,mpc8572-dma-channel",
|
||||||
|
"fsl,eloplus-dma-channel";
|
||||||
|
reg = <0x0 0x80>;
|
||||||
|
cell-index = <0>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <76 2>;
|
||||||
|
};
|
||||||
|
dma-channel@80 {
|
||||||
|
compatible = "fsl,mpc8572-dma-channel",
|
||||||
|
"fsl,eloplus-dma-channel";
|
||||||
|
reg = <0x80 0x80>;
|
||||||
|
cell-index = <1>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <77 2>;
|
||||||
|
};
|
||||||
|
dma-channel@100 {
|
||||||
|
compatible = "fsl,mpc8572-dma-channel",
|
||||||
|
"fsl,eloplus-dma-channel";
|
||||||
|
reg = <0x100 0x80>;
|
||||||
|
cell-index = <2>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <78 2>;
|
||||||
|
};
|
||||||
|
dma-channel@180 {
|
||||||
|
compatible = "fsl,mpc8572-dma-channel",
|
||||||
|
"fsl,eloplus-dma-channel";
|
||||||
|
reg = <0x180 0x80>;
|
||||||
|
cell-index = <3>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <79 2>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
dma@21300 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
|
||||||
|
reg = <0x21300 0x4>;
|
||||||
|
ranges = <0x0 0x21100 0x200>;
|
||||||
|
cell-index = <0>;
|
||||||
|
dma-channel@0 {
|
||||||
|
compatible = "fsl,mpc8572-dma-channel",
|
||||||
|
"fsl,eloplus-dma-channel";
|
||||||
|
reg = <0x0 0x80>;
|
||||||
|
cell-index = <0>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <20 2>;
|
||||||
|
};
|
||||||
|
dma-channel@80 {
|
||||||
|
compatible = "fsl,mpc8572-dma-channel",
|
||||||
|
"fsl,eloplus-dma-channel";
|
||||||
|
reg = <0x80 0x80>;
|
||||||
|
cell-index = <1>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <21 2>;
|
||||||
|
};
|
||||||
|
dma-channel@100 {
|
||||||
|
compatible = "fsl,mpc8572-dma-channel",
|
||||||
|
"fsl,eloplus-dma-channel";
|
||||||
|
reg = <0x100 0x80>;
|
||||||
|
cell-index = <2>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <22 2>;
|
||||||
|
};
|
||||||
|
dma-channel@180 {
|
||||||
|
compatible = "fsl,mpc8572-dma-channel",
|
||||||
|
"fsl,eloplus-dma-channel";
|
||||||
|
reg = <0x180 0x80>;
|
||||||
|
cell-index = <3>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <23 2>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
enet0: ethernet@24000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
cell-index = <0>;
|
||||||
|
device_type = "network";
|
||||||
|
model = "eTSEC";
|
||||||
|
compatible = "gianfar";
|
||||||
|
reg = <0x24000 0x1000>;
|
||||||
|
ranges = <0x0 0x24000 0x1000>;
|
||||||
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
|
interrupts = <29 2 30 2 34 2>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
tbi-handle = <&tbi0>;
|
||||||
|
phy-handle = <&phy0>;
|
||||||
|
phy-connection-type = "rgmii-id";
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-mdio";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
phy0: ethernet-phy@0 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <10 1>;
|
||||||
|
reg = <0x0>;
|
||||||
|
};
|
||||||
|
phy1: ethernet-phy@1 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <10 1>;
|
||||||
|
reg = <0x1>;
|
||||||
|
};
|
||||||
|
phy2: ethernet-phy@2 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <10 1>;
|
||||||
|
reg = <0x2>;
|
||||||
|
};
|
||||||
|
phy3: ethernet-phy@3 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <10 1>;
|
||||||
|
reg = <0x3>;
|
||||||
|
};
|
||||||
|
|
||||||
|
tbi0: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
enet1: ethernet@25000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
cell-index = <1>;
|
||||||
|
device_type = "network";
|
||||||
|
model = "eTSEC";
|
||||||
|
compatible = "gianfar";
|
||||||
|
reg = <0x25000 0x1000>;
|
||||||
|
ranges = <0x0 0x25000 0x1000>;
|
||||||
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
|
interrupts = <35 2 36 2 40 2>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
tbi-handle = <&tbi1>;
|
||||||
|
phy-handle = <&phy1>;
|
||||||
|
phy-connection-type = "rgmii-id";
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-tbi";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
tbi1: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
enet2: ethernet@26000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
cell-index = <2>;
|
||||||
|
device_type = "network";
|
||||||
|
model = "eTSEC";
|
||||||
|
compatible = "gianfar";
|
||||||
|
reg = <0x26000 0x1000>;
|
||||||
|
ranges = <0x0 0x26000 0x1000>;
|
||||||
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
|
interrupts = <31 2 32 2 33 2>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
tbi-handle = <&tbi2>;
|
||||||
|
phy-handle = <&phy2>;
|
||||||
|
phy-connection-type = "rgmii-id";
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-tbi";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
tbi2: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
enet3: ethernet@27000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
cell-index = <3>;
|
||||||
|
device_type = "network";
|
||||||
|
model = "eTSEC";
|
||||||
|
compatible = "gianfar";
|
||||||
|
reg = <0x27000 0x1000>;
|
||||||
|
ranges = <0x0 0x27000 0x1000>;
|
||||||
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
|
interrupts = <37 2 38 2 39 2>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
tbi-handle = <&tbi3>;
|
||||||
|
phy-handle = <&phy3>;
|
||||||
|
phy-connection-type = "rgmii-id";
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-tbi";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
tbi3: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
serial0: serial@4500 {
|
||||||
|
cell-index = <0>;
|
||||||
|
device_type = "serial";
|
||||||
|
compatible = "ns16550";
|
||||||
|
reg = <0x4500 0x100>;
|
||||||
|
clock-frequency = <0>;
|
||||||
|
interrupts = <42 2>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
};
|
||||||
|
|
||||||
|
serial1: serial@4600 {
|
||||||
|
cell-index = <1>;
|
||||||
|
device_type = "serial";
|
||||||
|
compatible = "ns16550";
|
||||||
|
reg = <0x4600 0x100>;
|
||||||
|
clock-frequency = <0>;
|
||||||
|
interrupts = <42 2>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
};
|
||||||
|
|
||||||
|
global-utilities@e0000 { //global utilities block
|
||||||
|
compatible = "fsl,mpc8572-guts";
|
||||||
|
reg = <0xe0000 0x1000>;
|
||||||
|
fsl,has-rstcr;
|
||||||
|
};
|
||||||
|
|
||||||
|
msi@41600 {
|
||||||
|
compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
|
||||||
|
reg = <0x41600 0x80>;
|
||||||
|
msi-available-ranges = <0 0x100>;
|
||||||
|
interrupts = <
|
||||||
|
0xe0 0
|
||||||
|
0xe1 0
|
||||||
|
0xe2 0
|
||||||
|
0xe3 0
|
||||||
|
0xe4 0
|
||||||
|
0xe5 0
|
||||||
|
0xe6 0
|
||||||
|
0xe7 0>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
};
|
||||||
|
|
||||||
|
crypto@30000 {
|
||||||
|
compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
|
||||||
|
"fsl,sec2.1", "fsl,sec2.0";
|
||||||
|
reg = <0x30000 0x10000>;
|
||||||
|
interrupts = <45 2 58 2>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
fsl,num-channels = <4>;
|
||||||
|
fsl,channel-fifo-len = <24>;
|
||||||
|
fsl,exec-units-mask = <0x9fe>;
|
||||||
|
fsl,descriptor-types-mask = <0x3ab0ebf>;
|
||||||
|
};
|
||||||
|
|
||||||
|
mpic: pic@40000 {
|
||||||
|
interrupt-controller;
|
||||||
|
#address-cells = <0>;
|
||||||
|
#interrupt-cells = <2>;
|
||||||
|
reg = <0x40000 0x40000>;
|
||||||
|
compatible = "chrp,open-pic";
|
||||||
|
device_type = "open-pic";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
pci0: pcie@fffe08000 {
|
||||||
|
cell-index = <0>;
|
||||||
|
compatible = "fsl,mpc8548-pcie";
|
||||||
|
device_type = "pci";
|
||||||
|
#interrupt-cells = <1>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
#address-cells = <3>;
|
||||||
|
reg = <0xf 0xffe08000 0 0x1000>;
|
||||||
|
bus-range = <0 255>;
|
||||||
|
ranges = <0x2000000 0x0 0xc0000000 0xc 0x00000000 0x0 0x20000000
|
||||||
|
0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000>;
|
||||||
|
clock-frequency = <33333333>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <24 2>;
|
||||||
|
interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
|
||||||
|
interrupt-map = <
|
||||||
|
/* IDSEL 0x11 func 0 - PCI slot 1 */
|
||||||
|
0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
|
||||||
|
0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
|
||||||
|
0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
|
||||||
|
0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
|
||||||
|
|
||||||
|
/* IDSEL 0x11 func 1 - PCI slot 1 */
|
||||||
|
0x8900 0x0 0x0 0x1 &mpic 0x2 0x1
|
||||||
|
0x8900 0x0 0x0 0x2 &mpic 0x3 0x1
|
||||||
|
0x8900 0x0 0x0 0x3 &mpic 0x4 0x1
|
||||||
|
0x8900 0x0 0x0 0x4 &mpic 0x1 0x1
|
||||||
|
|
||||||
|
/* IDSEL 0x11 func 2 - PCI slot 1 */
|
||||||
|
0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1
|
||||||
|
0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1
|
||||||
|
0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1
|
||||||
|
0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1
|
||||||
|
|
||||||
|
/* IDSEL 0x11 func 3 - PCI slot 1 */
|
||||||
|
0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1
|
||||||
|
0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1
|
||||||
|
0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1
|
||||||
|
0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1
|
||||||
|
|
||||||
|
/* IDSEL 0x11 func 4 - PCI slot 1 */
|
||||||
|
0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1
|
||||||
|
0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1
|
||||||
|
0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1
|
||||||
|
0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1
|
||||||
|
|
||||||
|
/* IDSEL 0x11 func 5 - PCI slot 1 */
|
||||||
|
0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1
|
||||||
|
0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1
|
||||||
|
0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1
|
||||||
|
0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1
|
||||||
|
|
||||||
|
/* IDSEL 0x11 func 6 - PCI slot 1 */
|
||||||
|
0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1
|
||||||
|
0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1
|
||||||
|
0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1
|
||||||
|
0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1
|
||||||
|
|
||||||
|
/* IDSEL 0x11 func 7 - PCI slot 1 */
|
||||||
|
0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1
|
||||||
|
0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1
|
||||||
|
0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1
|
||||||
|
0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1
|
||||||
|
|
||||||
|
/* IDSEL 0x12 func 0 - PCI slot 2 */
|
||||||
|
0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
|
||||||
|
0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
|
||||||
|
0x9000 0x0 0x0 0x3 &mpic 0x1 0x1
|
||||||
|
0x9000 0x0 0x0 0x4 &mpic 0x2 0x1
|
||||||
|
|
||||||
|
/* IDSEL 0x12 func 1 - PCI slot 2 */
|
||||||
|
0x9100 0x0 0x0 0x1 &mpic 0x3 0x1
|
||||||
|
0x9100 0x0 0x0 0x2 &mpic 0x4 0x1
|
||||||
|
0x9100 0x0 0x0 0x3 &mpic 0x1 0x1
|
||||||
|
0x9100 0x0 0x0 0x4 &mpic 0x2 0x1
|
||||||
|
|
||||||
|
/* IDSEL 0x12 func 2 - PCI slot 2 */
|
||||||
|
0x9200 0x0 0x0 0x1 &mpic 0x3 0x1
|
||||||
|
0x9200 0x0 0x0 0x2 &mpic 0x4 0x1
|
||||||
|
0x9200 0x0 0x0 0x3 &mpic 0x1 0x1
|
||||||
|
0x9200 0x0 0x0 0x4 &mpic 0x2 0x1
|
||||||
|
|
||||||
|
/* IDSEL 0x12 func 3 - PCI slot 2 */
|
||||||
|
0x9300 0x0 0x0 0x1 &mpic 0x3 0x1
|
||||||
|
0x9300 0x0 0x0 0x2 &mpic 0x4 0x1
|
||||||
|
0x9300 0x0 0x0 0x3 &mpic 0x1 0x1
|
||||||
|
0x9300 0x0 0x0 0x4 &mpic 0x2 0x1
|
||||||
|
|
||||||
|
/* IDSEL 0x12 func 4 - PCI slot 2 */
|
||||||
|
0x9400 0x0 0x0 0x1 &mpic 0x3 0x1
|
||||||
|
0x9400 0x0 0x0 0x2 &mpic 0x4 0x1
|
||||||
|
0x9400 0x0 0x0 0x3 &mpic 0x1 0x1
|
||||||
|
0x9400 0x0 0x0 0x4 &mpic 0x2 0x1
|
||||||
|
|
||||||
|
/* IDSEL 0x12 func 5 - PCI slot 2 */
|
||||||
|
0x9500 0x0 0x0 0x1 &mpic 0x3 0x1
|
||||||
|
0x9500 0x0 0x0 0x2 &mpic 0x4 0x1
|
||||||
|
0x9500 0x0 0x0 0x3 &mpic 0x1 0x1
|
||||||
|
0x9500 0x0 0x0 0x4 &mpic 0x2 0x1
|
||||||
|
|
||||||
|
/* IDSEL 0x12 func 6 - PCI slot 2 */
|
||||||
|
0x9600 0x0 0x0 0x1 &mpic 0x3 0x1
|
||||||
|
0x9600 0x0 0x0 0x2 &mpic 0x4 0x1
|
||||||
|
0x9600 0x0 0x0 0x3 &mpic 0x1 0x1
|
||||||
|
0x9600 0x0 0x0 0x4 &mpic 0x2 0x1
|
||||||
|
|
||||||
|
/* IDSEL 0x12 func 7 - PCI slot 2 */
|
||||||
|
0x9700 0x0 0x0 0x1 &mpic 0x3 0x1
|
||||||
|
0x9700 0x0 0x0 0x2 &mpic 0x4 0x1
|
||||||
|
0x9700 0x0 0x0 0x3 &mpic 0x1 0x1
|
||||||
|
0x9700 0x0 0x0 0x4 &mpic 0x2 0x1
|
||||||
|
|
||||||
|
// IDSEL 0x1c USB
|
||||||
|
0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
|
||||||
|
0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
|
||||||
|
0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
|
||||||
|
0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
|
||||||
|
|
||||||
|
// IDSEL 0x1d Audio
|
||||||
|
0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
|
||||||
|
|
||||||
|
// IDSEL 0x1e Legacy
|
||||||
|
0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
|
||||||
|
0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
|
||||||
|
|
||||||
|
// IDSEL 0x1f IDE/SATA
|
||||||
|
0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
|
||||||
|
0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
|
||||||
|
|
||||||
|
>;
|
||||||
|
|
||||||
|
pcie@0 {
|
||||||
|
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
#address-cells = <3>;
|
||||||
|
device_type = "pci";
|
||||||
|
ranges = <0x2000000 0x0 0xc0000000
|
||||||
|
0x2000000 0x0 0xc0000000
|
||||||
|
0x0 0x20000000
|
||||||
|
|
||||||
|
0x1000000 0x0 0x0
|
||||||
|
0x1000000 0x0 0x0
|
||||||
|
0x0 0x10000>;
|
||||||
|
uli1575@0 {
|
||||||
|
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
#address-cells = <3>;
|
||||||
|
ranges = <0x2000000 0x0 0xc0000000
|
||||||
|
0x2000000 0x0 0xc0000000
|
||||||
|
0x0 0x20000000
|
||||||
|
|
||||||
|
0x1000000 0x0 0x0
|
||||||
|
0x1000000 0x0 0x0
|
||||||
|
0x0 0x10000>;
|
||||||
|
isa@1e {
|
||||||
|
device_type = "isa";
|
||||||
|
#interrupt-cells = <2>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
#address-cells = <2>;
|
||||||
|
reg = <0xf000 0x0 0x0 0x0 0x0>;
|
||||||
|
ranges = <0x1 0x0 0x1000000 0x0 0x0
|
||||||
|
0x1000>;
|
||||||
|
interrupt-parent = <&i8259>;
|
||||||
|
|
||||||
|
i8259: interrupt-controller@20 {
|
||||||
|
reg = <0x1 0x20 0x2
|
||||||
|
0x1 0xa0 0x2
|
||||||
|
0x1 0x4d0 0x2>;
|
||||||
|
interrupt-controller;
|
||||||
|
device_type = "interrupt-controller";
|
||||||
|
#address-cells = <0>;
|
||||||
|
#interrupt-cells = <2>;
|
||||||
|
compatible = "chrp,iic";
|
||||||
|
interrupts = <9 2>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
};
|
||||||
|
|
||||||
|
i8042@60 {
|
||||||
|
#size-cells = <0>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
|
||||||
|
interrupts = <1 3 12 3>;
|
||||||
|
interrupt-parent =
|
||||||
|
<&i8259>;
|
||||||
|
|
||||||
|
keyboard@0 {
|
||||||
|
reg = <0x0>;
|
||||||
|
compatible = "pnpPNP,303";
|
||||||
|
};
|
||||||
|
|
||||||
|
mouse@1 {
|
||||||
|
reg = <0x1>;
|
||||||
|
compatible = "pnpPNP,f03";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
rtc@70 {
|
||||||
|
compatible = "pnpPNP,b00";
|
||||||
|
reg = <0x1 0x70 0x2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
gpio@400 {
|
||||||
|
reg = <0x1 0x400 0x80>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
};
|
||||||
|
|
||||||
|
pci1: pcie@fffe09000 {
|
||||||
|
cell-index = <1>;
|
||||||
|
compatible = "fsl,mpc8548-pcie";
|
||||||
|
device_type = "pci";
|
||||||
|
#interrupt-cells = <1>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
#address-cells = <3>;
|
||||||
|
reg = <0xf 0xffe09000 0 0x1000>;
|
||||||
|
bus-range = <0 255>;
|
||||||
|
ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
|
||||||
|
0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x00010000>;
|
||||||
|
clock-frequency = <33333333>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <25 2>;
|
||||||
|
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||||
|
interrupt-map = <
|
||||||
|
/* IDSEL 0x0 */
|
||||||
|
0000 0x0 0x0 0x1 &mpic 0x4 0x1
|
||||||
|
0000 0x0 0x0 0x2 &mpic 0x5 0x1
|
||||||
|
0000 0x0 0x0 0x3 &mpic 0x6 0x1
|
||||||
|
0000 0x0 0x0 0x4 &mpic 0x7 0x1
|
||||||
|
>;
|
||||||
|
pcie@0 {
|
||||||
|
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
#address-cells = <3>;
|
||||||
|
device_type = "pci";
|
||||||
|
ranges = <0x2000000 0x0 0xc0000000
|
||||||
|
0x2000000 0x0 0xc0000000
|
||||||
|
0x0 0x20000000
|
||||||
|
|
||||||
|
0x1000000 0x0 0x0
|
||||||
|
0x1000000 0x0 0x0
|
||||||
|
0x0 0x10000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
pci2: pcie@fffe0a000 {
|
||||||
|
cell-index = <2>;
|
||||||
|
compatible = "fsl,mpc8548-pcie";
|
||||||
|
device_type = "pci";
|
||||||
|
#interrupt-cells = <1>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
#address-cells = <3>;
|
||||||
|
reg = <0xf 0xffe0a000 0 0x1000>;
|
||||||
|
bus-range = <0 255>;
|
||||||
|
ranges = <0x2000000 0x0 0xc0000000 0xc 0x40000000 0x0 0x20000000
|
||||||
|
0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x00010000>;
|
||||||
|
clock-frequency = <33333333>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <26 2>;
|
||||||
|
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||||
|
interrupt-map = <
|
||||||
|
/* IDSEL 0x0 */
|
||||||
|
0000 0x0 0x0 0x1 &mpic 0x0 0x1
|
||||||
|
0000 0x0 0x0 0x2 &mpic 0x1 0x1
|
||||||
|
0000 0x0 0x0 0x3 &mpic 0x2 0x1
|
||||||
|
0000 0x0 0x0 0x4 &mpic 0x3 0x1
|
||||||
|
>;
|
||||||
|
pcie@0 {
|
||||||
|
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
#address-cells = <3>;
|
||||||
|
device_type = "pci";
|
||||||
|
ranges = <0x2000000 0x0 0xc0000000
|
||||||
|
0x2000000 0x0 0xc0000000
|
||||||
|
0x0 0x20000000
|
||||||
|
|
||||||
|
0x1000000 0x0 0x0
|
||||||
|
0x1000000 0x0 0x0
|
||||||
|
0x0 0x10000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
@ -6,7 +6,7 @@
|
||||||
* This dts file allows core0 to have memory, l2, i2c, dma1, global-util, eth0,
|
* This dts file allows core0 to have memory, l2, i2c, dma1, global-util, eth0,
|
||||||
* eth1, crypto, pci0, pci1.
|
* eth1, crypto, pci0, pci1.
|
||||||
*
|
*
|
||||||
* Copyright 2007, 2008 Freescale Semiconductor Inc.
|
* Copyright 2007-2009 Freescale Semiconductor Inc.
|
||||||
*
|
*
|
||||||
* This program is free software; you can redistribute it and/or modify it
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
* under the terms of the GNU General Public License as published by the
|
* under the terms of the GNU General Public License as published by the
|
||||||
|
|
@ -148,35 +148,38 @@
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
mdio@24520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-mdio";
|
|
||||||
reg = <0x24520 0x20>;
|
|
||||||
|
|
||||||
phy0: ethernet-phy@0 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <10 1>;
|
|
||||||
reg = <0x0>;
|
|
||||||
};
|
|
||||||
phy1: ethernet-phy@1 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <10 1>;
|
|
||||||
reg = <0x1>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
enet0: ethernet@24000 {
|
enet0: ethernet@24000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <0>;
|
cell-index = <0>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "eTSEC";
|
model = "eTSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x24000 0x1000>;
|
reg = <0x24000 0x1000>;
|
||||||
|
ranges = <0x0 0x24000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <29 2 30 2 34 2>;
|
interrupts = <29 2 30 2 34 2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
phy-handle = <&phy0>;
|
phy-handle = <&phy0>;
|
||||||
phy-connection-type = "rgmii-id";
|
phy-connection-type = "rgmii-id";
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-mdio";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
phy0: ethernet-phy@0 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <10 1>;
|
||||||
|
reg = <0x0>;
|
||||||
|
};
|
||||||
|
phy1: ethernet-phy@1 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <10 1>;
|
||||||
|
reg = <0x1>;
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
enet1: ethernet@25000 {
|
enet1: ethernet@25000 {
|
||||||
|
|
@ -227,7 +230,7 @@
|
||||||
device_type = "open-pic";
|
device_type = "open-pic";
|
||||||
protected-sources = <
|
protected-sources = <
|
||||||
31 32 33 37 38 39 /* enet2 enet3 */
|
31 32 33 37 38 39 /* enet2 enet3 */
|
||||||
76 77 78 79 27 42 /* dma2 pci2 serial*/
|
76 77 78 79 26 42 /* dma2 pci2 serial*/
|
||||||
0xe0 0xe1 0xe2 0xe3 /* msi */
|
0xe0 0xe1 0xe2 0xe3 /* msi */
|
||||||
0xe4 0xe5 0xe6 0xe7
|
0xe4 0xe5 0xe6 0xe7
|
||||||
>;
|
>;
|
||||||
|
|
@ -376,7 +379,7 @@
|
||||||
|
|
||||||
0x1000000 0x0 0x0
|
0x1000000 0x0 0x0
|
||||||
0x1000000 0x0 0x0
|
0x1000000 0x0 0x0
|
||||||
0x0 0x100000>;
|
0x0 0x10000>;
|
||||||
uli1575@0 {
|
uli1575@0 {
|
||||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||||
#size-cells = <2>;
|
#size-cells = <2>;
|
||||||
|
|
@ -387,7 +390,7 @@
|
||||||
|
|
||||||
0x1000000 0x0 0x0
|
0x1000000 0x0 0x0
|
||||||
0x1000000 0x0 0x0
|
0x1000000 0x0 0x0
|
||||||
0x0 0x100000>;
|
0x0 0x10000>;
|
||||||
isa@1e {
|
isa@1e {
|
||||||
device_type = "isa";
|
device_type = "isa";
|
||||||
#interrupt-cells = <2>;
|
#interrupt-cells = <2>;
|
||||||
|
|
@ -477,7 +480,7 @@
|
||||||
|
|
||||||
0x1000000 0x0 0x0
|
0x1000000 0x0 0x0
|
||||||
0x1000000 0x0 0x0
|
0x1000000 0x0 0x0
|
||||||
0x0 0x100000>;
|
0x0 0x10000>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
|
||||||
|
|
@ -7,7 +7,7 @@
|
||||||
*
|
*
|
||||||
* Please note to add "-b 1" for core1's dts compiling.
|
* Please note to add "-b 1" for core1's dts compiling.
|
||||||
*
|
*
|
||||||
* Copyright 2007, 2008 Freescale Semiconductor Inc.
|
* Copyright 2007-2009 Freescale Semiconductor Inc.
|
||||||
*
|
*
|
||||||
* This program is free software; you can redistribute it and/or modify it
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
* under the terms of the GNU General Public License as published by the
|
* under the terms of the GNU General Public License as published by the
|
||||||
|
|
@ -186,7 +186,7 @@
|
||||||
protected-sources = <
|
protected-sources = <
|
||||||
18 16 10 42 45 58 /* MEM L2 mdio serial crypto */
|
18 16 10 42 45 58 /* MEM L2 mdio serial crypto */
|
||||||
29 30 34 35 36 40 /* enet0 enet1 */
|
29 30 34 35 36 40 /* enet0 enet1 */
|
||||||
24 26 20 21 22 23 /* pcie0 pcie1 dma1 */
|
24 25 20 21 22 23 /* pci0 pci1 dma1 */
|
||||||
43 /* i2c */
|
43 /* i2c */
|
||||||
0x1 0x2 0x3 0x4 /* pci slot */
|
0x1 0x2 0x3 0x4 /* pci slot */
|
||||||
0x9 0xa 0xb 0xc /* usb */
|
0x9 0xa 0xb 0xc /* usb */
|
||||||
|
|
@ -228,7 +228,7 @@
|
||||||
|
|
||||||
0x1000000 0x0 0x0
|
0x1000000 0x0 0x0
|
||||||
0x1000000 0x0 0x0
|
0x1000000 0x0 0x0
|
||||||
0x0 0x100000>;
|
0x0 0x10000>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
|
||||||
|
|
@ -217,6 +217,7 @@
|
||||||
codec-handle = <&cs4270>;
|
codec-handle = <&cs4270>;
|
||||||
fsl,playback-dma = <&dma00>;
|
fsl,playback-dma = <&dma00>;
|
||||||
fsl,capture-dma = <&dma01>;
|
fsl,capture-dma = <&dma01>;
|
||||||
|
fsl,fifo-depth = <8>;
|
||||||
};
|
};
|
||||||
|
|
||||||
ssi@16100 {
|
ssi@16100 {
|
||||||
|
|
@ -225,6 +226,7 @@
|
||||||
reg = <0x16100 0x100>;
|
reg = <0x16100 0x100>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
interrupts = <63 2>;
|
interrupts = <63 2>;
|
||||||
|
fsl,fifo-depth = <8>;
|
||||||
};
|
};
|
||||||
|
|
||||||
dma@21300 {
|
dma@21300 {
|
||||||
|
|
|
||||||
|
|
@ -180,133 +180,144 @@
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
mdio@24520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-mdio";
|
|
||||||
reg = <0x24520 0x20>;
|
|
||||||
|
|
||||||
phy0: ethernet-phy@0 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <10 1>;
|
|
||||||
reg = <0>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
phy1: ethernet-phy@1 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <10 1>;
|
|
||||||
reg = <1>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
phy2: ethernet-phy@2 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <10 1>;
|
|
||||||
reg = <2>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
phy3: ethernet-phy@3 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <10 1>;
|
|
||||||
reg = <3>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
tbi0: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
mdio@25520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-tbi";
|
|
||||||
reg = <0x25520 0x20>;
|
|
||||||
|
|
||||||
tbi1: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
mdio@26520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-tbi";
|
|
||||||
reg = <0x26520 0x20>;
|
|
||||||
|
|
||||||
tbi2: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
mdio@27520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-tbi";
|
|
||||||
reg = <0x27520 0x20>;
|
|
||||||
|
|
||||||
tbi3: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
|
|
||||||
enet0: ethernet@24000 {
|
enet0: ethernet@24000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <0>;
|
cell-index = <0>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "TSEC";
|
model = "TSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x24000 0x1000>;
|
reg = <0x24000 0x1000>;
|
||||||
|
ranges = <0x0 0x24000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <29 2 30 2 34 2>;
|
interrupts = <29 2 30 2 34 2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
tbi-handle = <&tbi0>;
|
tbi-handle = <&tbi0>;
|
||||||
phy-handle = <&phy0>;
|
phy-handle = <&phy0>;
|
||||||
phy-connection-type = "rgmii-id";
|
phy-connection-type = "rgmii-id";
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-mdio";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
phy0: ethernet-phy@0 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <10 1>;
|
||||||
|
reg = <0>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
phy1: ethernet-phy@1 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <10 1>;
|
||||||
|
reg = <1>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
phy2: ethernet-phy@2 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <10 1>;
|
||||||
|
reg = <2>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
phy3: ethernet-phy@3 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <10 1>;
|
||||||
|
reg = <3>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
tbi0: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
enet1: ethernet@25000 {
|
enet1: ethernet@25000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <1>;
|
cell-index = <1>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "TSEC";
|
model = "TSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x25000 0x1000>;
|
reg = <0x25000 0x1000>;
|
||||||
|
ranges = <0x0 0x25000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <35 2 36 2 40 2>;
|
interrupts = <35 2 36 2 40 2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
tbi-handle = <&tbi1>;
|
tbi-handle = <&tbi1>;
|
||||||
phy-handle = <&phy1>;
|
phy-handle = <&phy1>;
|
||||||
phy-connection-type = "rgmii-id";
|
phy-connection-type = "rgmii-id";
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-tbi";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
tbi1: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
enet2: ethernet@26000 {
|
enet2: ethernet@26000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <2>;
|
cell-index = <2>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "TSEC";
|
model = "TSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x26000 0x1000>;
|
reg = <0x26000 0x1000>;
|
||||||
|
ranges = <0x0 0x26000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <31 2 32 2 33 2>;
|
interrupts = <31 2 32 2 33 2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
tbi-handle = <&tbi2>;
|
tbi-handle = <&tbi2>;
|
||||||
phy-handle = <&phy2>;
|
phy-handle = <&phy2>;
|
||||||
phy-connection-type = "rgmii-id";
|
phy-connection-type = "rgmii-id";
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-tbi";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
tbi2: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
enet3: ethernet@27000 {
|
enet3: ethernet@27000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <3>;
|
cell-index = <3>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "TSEC";
|
model = "TSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x27000 0x1000>;
|
reg = <0x27000 0x1000>;
|
||||||
|
ranges = <0x0 0x27000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <37 2 38 2 39 2>;
|
interrupts = <37 2 38 2 39 2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
tbi-handle = <&tbi3>;
|
tbi-handle = <&tbi3>;
|
||||||
phy-handle = <&phy3>;
|
phy-handle = <&phy3>;
|
||||||
phy-connection-type = "rgmii-id";
|
phy-connection-type = "rgmii-id";
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-tbi";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
tbi3: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
serial0: serial@4500 {
|
serial0: serial@4500 {
|
||||||
|
|
|
||||||
|
|
@ -19,6 +19,7 @@
|
||||||
compatible = "phytec,pcm030";
|
compatible = "phytec,pcm030";
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <1>;
|
#size-cells = <1>;
|
||||||
|
interrupt-parent = <&mpc5200_pic>;
|
||||||
|
|
||||||
cpus {
|
cpus {
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
|
|
@ -29,26 +30,26 @@
|
||||||
reg = <0>;
|
reg = <0>;
|
||||||
d-cache-line-size = <32>;
|
d-cache-line-size = <32>;
|
||||||
i-cache-line-size = <32>;
|
i-cache-line-size = <32>;
|
||||||
d-cache-size = <0x4000>; /* L1, 16K */
|
d-cache-size = <0x4000>; // L1, 16K
|
||||||
i-cache-size = <0x4000>; /* L1, 16K */
|
i-cache-size = <0x4000>; // L1, 16K
|
||||||
timebase-frequency = <0>; /* From Bootloader */
|
timebase-frequency = <0>; // from bootloader
|
||||||
bus-frequency = <0>; /* From Bootloader */
|
bus-frequency = <0>; // from bootloader
|
||||||
clock-frequency = <0>; /* From Bootloader */
|
clock-frequency = <0>; // from bootloader
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
memory {
|
memory {
|
||||||
device_type = "memory";
|
device_type = "memory";
|
||||||
reg = <0x00000000 0x04000000>; /* 64MB */
|
reg = <0x00000000 0x04000000>; // 64MB
|
||||||
};
|
};
|
||||||
|
|
||||||
soc5200@f0000000 {
|
soc5200@f0000000 {
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <1>;
|
#size-cells = <1>;
|
||||||
compatible = "fsl,mpc5200b-immr";
|
compatible = "fsl,mpc5200b-immr";
|
||||||
ranges = <0x0 0xf0000000 0x0000c000>;
|
ranges = <0 0xf0000000 0x0000c000>;
|
||||||
bus-frequency = <0>; /* From bootloader */
|
bus-frequency = <0>; // from bootloader
|
||||||
system-frequency = <0>; /* From bootloader */
|
system-frequency = <0>; // from bootloader
|
||||||
|
|
||||||
cdm@200 {
|
cdm@200 {
|
||||||
compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
|
compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
|
||||||
|
|
@ -56,87 +57,70 @@
|
||||||
};
|
};
|
||||||
|
|
||||||
mpc5200_pic: interrupt-controller@500 {
|
mpc5200_pic: interrupt-controller@500 {
|
||||||
/* 5200 interrupts are encoded into two levels; */
|
// 5200 interrupts are encoded into two levels;
|
||||||
interrupt-controller;
|
interrupt-controller;
|
||||||
#interrupt-cells = <3>;
|
#interrupt-cells = <3>;
|
||||||
device_type = "interrupt-controller";
|
|
||||||
compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
|
compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
|
||||||
reg = <0x500 0x80>;
|
reg = <0x500 0x80>;
|
||||||
};
|
};
|
||||||
|
|
||||||
timer@600 { /* General Purpose Timer */
|
timer@600 { // General Purpose Timer
|
||||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||||
cell-index = <0>;
|
|
||||||
reg = <0x600 0x10>;
|
reg = <0x600 0x10>;
|
||||||
interrupts = <0x1 0x9 0x0>;
|
interrupts = <1 9 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
fsl,has-wdt;
|
fsl,has-wdt;
|
||||||
};
|
};
|
||||||
|
|
||||||
timer@610 { /* General Purpose Timer */
|
timer@610 { // General Purpose Timer
|
||||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||||
cell-index = <1>;
|
|
||||||
reg = <0x610 0x10>;
|
reg = <0x610 0x10>;
|
||||||
interrupts = <0x1 0xa 0x0>;
|
interrupts = <1 10 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
gpt2: timer@620 { /* General Purpose Timer in GPIO mode */
|
gpt2: timer@620 { // General Purpose Timer in GPIO mode
|
||||||
compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
|
compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
|
||||||
cell-index = <2>;
|
|
||||||
reg = <0x620 0x10>;
|
reg = <0x620 0x10>;
|
||||||
interrupts = <0x1 0xb 0x0>;
|
interrupts = <1 11 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
gpio-controller;
|
gpio-controller;
|
||||||
#gpio-cells = <2>;
|
#gpio-cells = <2>;
|
||||||
};
|
};
|
||||||
|
|
||||||
gpt3: timer@630 { /* General Purpose Timer in GPIO mode */
|
gpt3: timer@630 { // General Purpose Timer in GPIO mode
|
||||||
compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
|
compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
|
||||||
cell-index = <3>;
|
|
||||||
reg = <0x630 0x10>;
|
reg = <0x630 0x10>;
|
||||||
interrupts = <0x1 0xc 0x0>;
|
interrupts = <1 12 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
gpio-controller;
|
gpio-controller;
|
||||||
#gpio-cells = <2>;
|
#gpio-cells = <2>;
|
||||||
};
|
};
|
||||||
|
|
||||||
gpt4: timer@640 { /* General Purpose Timer in GPIO mode */
|
gpt4: timer@640 { // General Purpose Timer in GPIO mode
|
||||||
compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
|
compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
|
||||||
cell-index = <4>;
|
|
||||||
reg = <0x640 0x10>;
|
reg = <0x640 0x10>;
|
||||||
interrupts = <0x1 0xd 0x0>;
|
interrupts = <1 13 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
gpio-controller;
|
gpio-controller;
|
||||||
#gpio-cells = <2>;
|
#gpio-cells = <2>;
|
||||||
};
|
};
|
||||||
|
|
||||||
gpt5: timer@650 { /* General Purpose Timer in GPIO mode */
|
gpt5: timer@650 { // General Purpose Timer in GPIO mode
|
||||||
compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
|
compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
|
||||||
cell-index = <5>;
|
|
||||||
reg = <0x650 0x10>;
|
reg = <0x650 0x10>;
|
||||||
interrupts = <0x1 0xe 0x0>;
|
interrupts = <1 14 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
gpio-controller;
|
gpio-controller;
|
||||||
#gpio-cells = <2>;
|
#gpio-cells = <2>;
|
||||||
};
|
};
|
||||||
|
|
||||||
gpt6: timer@660 { /* General Purpose Timer in GPIO mode */
|
gpt6: timer@660 { // General Purpose Timer in GPIO mode
|
||||||
compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
|
compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
|
||||||
cell-index = <6>;
|
|
||||||
reg = <0x660 0x10>;
|
reg = <0x660 0x10>;
|
||||||
interrupts = <0x1 0xf 0x0>;
|
interrupts = <1 15 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
gpio-controller;
|
gpio-controller;
|
||||||
#gpio-cells = <2>;
|
#gpio-cells = <2>;
|
||||||
};
|
};
|
||||||
|
|
||||||
gpt7: timer@670 { /* General Purpose Timer in GPIO mode */
|
gpt7: timer@670 { // General Purpose Timer in GPIO mode
|
||||||
compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
|
compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
|
||||||
cell-index = <7>;
|
|
||||||
reg = <0x670 0x10>;
|
reg = <0x670 0x10>;
|
||||||
interrupts = <0x1 0x10 0x0>;
|
interrupts = <1 16 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
gpio-controller;
|
gpio-controller;
|
||||||
#gpio-cells = <2>;
|
#gpio-cells = <2>;
|
||||||
};
|
};
|
||||||
|
|
@ -144,40 +128,33 @@
|
||||||
rtc@800 { // Real time clock
|
rtc@800 { // Real time clock
|
||||||
compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
|
compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
|
||||||
reg = <0x800 0x100>;
|
reg = <0x800 0x100>;
|
||||||
interrupts = <0x1 0x5 0x0 0x1 0x6 0x0>;
|
interrupts = <1 5 0 1 6 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
can@900 {
|
can@900 {
|
||||||
compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
|
compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
|
||||||
cell-index = <0>;
|
interrupts = <2 17 0>;
|
||||||
interrupts = <0x2 0x11 0x0>;
|
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
reg = <0x900 0x80>;
|
reg = <0x900 0x80>;
|
||||||
};
|
};
|
||||||
|
|
||||||
can@980 {
|
can@980 {
|
||||||
compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
|
compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
|
||||||
cell-index = <1>;
|
interrupts = <2 18 0>;
|
||||||
interrupts = <0x2 0x12 0x0>;
|
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
reg = <0x980 0x80>;
|
reg = <0x980 0x80>;
|
||||||
};
|
};
|
||||||
|
|
||||||
gpio_simple: gpio@b00 {
|
gpio_simple: gpio@b00 {
|
||||||
compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
|
compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
|
||||||
reg = <0xb00 0x40>;
|
reg = <0xb00 0x40>;
|
||||||
interrupts = <0x1 0x7 0x0>;
|
interrupts = <1 7 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
gpio-controller;
|
gpio-controller;
|
||||||
#gpio-cells = <2>;
|
#gpio-cells = <2>;
|
||||||
};
|
};
|
||||||
|
|
||||||
gpio_wkup: gpio-wkup@c00 {
|
gpio_wkup: gpio@c00 {
|
||||||
compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
|
compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
|
||||||
reg = <0xc00 0x40>;
|
reg = <0xc00 0x40>;
|
||||||
interrupts = <0x1 0x8 0x0 0x0 0x3 0x0>;
|
interrupts = <1 8 0 0 3 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
gpio-controller;
|
gpio-controller;
|
||||||
#gpio-cells = <2>;
|
#gpio-cells = <2>;
|
||||||
};
|
};
|
||||||
|
|
@ -185,26 +162,22 @@
|
||||||
spi@f00 {
|
spi@f00 {
|
||||||
compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
|
compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
|
||||||
reg = <0xf00 0x20>;
|
reg = <0xf00 0x20>;
|
||||||
interrupts = <0x2 0xd 0x0 0x2 0xe 0x0>;
|
interrupts = <2 13 0 2 14 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
usb@1000 {
|
usb@1000 {
|
||||||
compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
|
compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
|
||||||
reg = <0x1000 0xff>;
|
reg = <0x1000 0xff>;
|
||||||
interrupts = <0x2 0x6 0x0>;
|
interrupts = <2 6 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
dma-controller@1200 {
|
dma-controller@1200 {
|
||||||
device_type = "dma-controller";
|
|
||||||
compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
|
compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
|
||||||
reg = <0x1200 0x80>;
|
reg = <0x1200 0x80>;
|
||||||
interrupts = <0x3 0x0 0x0 0x3 0x1 0x0 0x3 0x2 0x0 0x3 0x3 0x0
|
interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
|
||||||
0x3 0x4 0x0 0x3 0x5 0x0 0x3 0x6 0x0 0x3 0x7 0x0
|
3 4 0 3 5 0 3 6 0 3 7 0
|
||||||
0x3 0x8 0x0 0x3 0x9 0x0 0x3 0xa 0x0 0x3 0xb 0x0
|
3 8 0 3 9 0 3 10 0 3 11 0
|
||||||
0x3 0xc 0x0 0x3 0xd 0x0 0x3 0xe 0x0 0x3 0xf 0x0>;
|
3 12 0 3 13 0 3 14 0 3 15 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
xlb@1f00 {
|
xlb@1f00 {
|
||||||
|
|
@ -213,24 +186,19 @@
|
||||||
};
|
};
|
||||||
|
|
||||||
ac97@2000 { /* PSC1 in ac97 mode */
|
ac97@2000 { /* PSC1 in ac97 mode */
|
||||||
device_type = "sound";
|
|
||||||
compatible = "mpc5200b-psc-ac97","fsl,mpc5200b-psc-ac97";
|
compatible = "mpc5200b-psc-ac97","fsl,mpc5200b-psc-ac97";
|
||||||
cell-index = <0>;
|
cell-index = <0>;
|
||||||
reg = <0x2000 0x100>;
|
reg = <0x2000 0x100>;
|
||||||
interrupts = <0x2 0x2 0x0>;
|
interrupts = <2 1 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
/* PSC2 port is used by CAN1/2 */
|
/* PSC2 port is used by CAN1/2 */
|
||||||
|
|
||||||
serial@2400 { /* PSC3 in UART mode */
|
serial@2400 { /* PSC3 in UART mode */
|
||||||
device_type = "serial";
|
|
||||||
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||||
port-number = <0>;
|
|
||||||
cell-index = <2>;
|
cell-index = <2>;
|
||||||
reg = <0x2400 0x100>;
|
reg = <0x2400 0x100>;
|
||||||
interrupts = <0x2 0x3 0x0>;
|
interrupts = <2 3 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
/* PSC4 is ??? */
|
/* PSC4 is ??? */
|
||||||
|
|
@ -238,55 +206,44 @@
|
||||||
/* PSC5 is ??? */
|
/* PSC5 is ??? */
|
||||||
|
|
||||||
serial@2c00 { /* PSC6 in UART mode */
|
serial@2c00 { /* PSC6 in UART mode */
|
||||||
device_type = "serial";
|
|
||||||
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||||
port-number = <1>;
|
|
||||||
cell-index = <5>;
|
cell-index = <5>;
|
||||||
reg = <0x2c00 0x100>;
|
reg = <0x2c00 0x100>;
|
||||||
interrupts = <0x2 0x4 0x0>;
|
interrupts = <2 4 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
ethernet@3000 {
|
ethernet@3000 {
|
||||||
device_type = "network";
|
|
||||||
compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
|
compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
|
||||||
reg = <0x3000 0x400>;
|
reg = <0x3000 0x400>;
|
||||||
local-mac-address = [00 00 00 00 00 00];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <0x2 0x5 0x0>;
|
interrupts = <2 5 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
phy-handle = <&phy0>;
|
phy-handle = <&phy0>;
|
||||||
};
|
};
|
||||||
|
|
||||||
mdio@3000 {
|
mdio@3000 {
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <0>;
|
#size-cells = <0>;
|
||||||
compatible = "fsl,mpc5200b-mdio", "fsl,mpc5200-mdio";
|
compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
|
||||||
reg = <0x3000 0x400>; /* fec range, since we need to setup fec interrupts */
|
reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
|
||||||
interrupts = <0x2 0x5 0x0>; /* these are for "mii command finished", not link changes & co. */
|
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
|
|
||||||
phy0:ethernet-phy@0 {
|
phy0: ethernet-phy@0 {
|
||||||
device_type = "ethernet-phy";
|
reg = <0>;
|
||||||
reg = <0x0>;
|
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
ata@3a00 {
|
ata@3a00 {
|
||||||
device_type = "ata";
|
|
||||||
compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
|
compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
|
||||||
reg = <0x3a00 0x100>;
|
reg = <0x3a00 0x100>;
|
||||||
interrupts = <0x2 0x7 0x0>;
|
interrupts = <2 7 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
i2c@3d00 {
|
i2c@3d00 {
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <0>;
|
#size-cells = <0>;
|
||||||
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
|
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
|
||||||
cell-index = <0>;
|
|
||||||
reg = <0x3d00 0x40>;
|
reg = <0x3d00 0x40>;
|
||||||
interrupts = <0x2 0xf 0x0>;
|
interrupts = <2 15 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
fsl5200-clocking;
|
fsl5200-clocking;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -294,10 +251,8 @@
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <0>;
|
#size-cells = <0>;
|
||||||
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
|
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
|
||||||
cell-index = <1>;
|
|
||||||
reg = <0x3d40 0x40>;
|
reg = <0x3d40 0x40>;
|
||||||
interrupts = <0x2 0x10 0x0>;
|
interrupts = <2 16 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
fsl5200-clocking;
|
fsl5200-clocking;
|
||||||
rtc@51 {
|
rtc@51 {
|
||||||
compatible = "nxp,pcf8563";
|
compatible = "nxp,pcf8563";
|
||||||
|
|
@ -307,7 +262,7 @@
|
||||||
};
|
};
|
||||||
|
|
||||||
sram@8000 {
|
sram@8000 {
|
||||||
compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram","sram";
|
compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
|
||||||
reg = <0x8000 0x4000>;
|
reg = <0x8000 0x4000>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -340,22 +295,21 @@
|
||||||
device_type = "pci";
|
device_type = "pci";
|
||||||
compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
|
compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
|
||||||
reg = <0xf0000d00 0x100>;
|
reg = <0xf0000d00 0x100>;
|
||||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
interrupt-map-mask = <0xf800 0 0 7>;
|
||||||
interrupt-map = <0xc000 0x0 0x0 0x1 &mpc5200_pic 0x0 0x0 0x3 /* 1st slot */
|
interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
|
||||||
0xc000 0x0 0x0 0x2 &mpc5200_pic 0x1 0x1 0x3
|
0xc000 0 0 2 &mpc5200_pic 1 1 3
|
||||||
0xc000 0x0 0x0 0x3 &mpc5200_pic 0x1 0x2 0x3
|
0xc000 0 0 3 &mpc5200_pic 1 2 3
|
||||||
0xc000 0x0 0x0 0x4 &mpc5200_pic 0x1 0x3 0x3
|
0xc000 0 0 4 &mpc5200_pic 1 3 3
|
||||||
|
|
||||||
0xc800 0x0 0x0 0x1 &mpc5200_pic 0x1 0x1 0x3 /* 2nd slot */
|
0xc800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot
|
||||||
0xc800 0x0 0x0 0x2 &mpc5200_pic 0x1 0x2 0x3
|
0xc800 0 0 2 &mpc5200_pic 1 2 3
|
||||||
0xc800 0x0 0x0 0x3 &mpc5200_pic 0x1 0x3 0x3
|
0xc800 0 0 3 &mpc5200_pic 1 3 3
|
||||||
0xc800 0x0 0x0 0x4 &mpc5200_pic 0x0 0x0 0x3>;
|
0xc800 0 0 4 &mpc5200_pic 0 0 3>;
|
||||||
clock-frequency = <0>; // From boot loader
|
clock-frequency = <0>; // From boot loader
|
||||||
interrupts = <0x2 0x8 0x0 0x2 0x9 0x0 0x2 0xa 0x0>;
|
interrupts = <2 8 0 2 9 0 2 10 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
bus-range = <0 0>;
|
bus-range = <0 0>;
|
||||||
ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x20000000
|
ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
|
||||||
0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
|
0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
|
||||||
0x01000000 0x0 0x00000000 0xb0000000 0x0 0x01000000>;
|
0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,392 @@
|
||||||
|
/*
|
||||||
|
* phyCORE-MPC5200B-IO (pcm032) board Device Tree Source
|
||||||
|
*
|
||||||
|
* Copyright (C) 2006-2009 Pengutronix
|
||||||
|
* Sascha Hauer <s.hauer@pengutronix.de>
|
||||||
|
* Juergen Beisert <j.beisert@pengutronix.de>
|
||||||
|
* Wolfram Sang <w.sang@pengutronix.de>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms of the GNU General Public License as published by the
|
||||||
|
* Free Software Foundation; either version 2 of the License, or (at your
|
||||||
|
* option) any later version.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "phytec,pcm032";
|
||||||
|
compatible = "phytec,pcm032";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
interrupt-parent = <&mpc5200_pic>;
|
||||||
|
|
||||||
|
cpus {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
PowerPC,5200@0 {
|
||||||
|
device_type = "cpu";
|
||||||
|
reg = <0>;
|
||||||
|
d-cache-line-size = <32>;
|
||||||
|
i-cache-line-size = <32>;
|
||||||
|
d-cache-size = <0x4000>; // L1, 16K
|
||||||
|
i-cache-size = <0x4000>; // L1, 16K
|
||||||
|
timebase-frequency = <0>; // from bootloader
|
||||||
|
bus-frequency = <0>; // from bootloader
|
||||||
|
clock-frequency = <0>; // from bootloader
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
memory {
|
||||||
|
device_type = "memory";
|
||||||
|
reg = <0x00000000 0x08000000>; // 128MB
|
||||||
|
};
|
||||||
|
|
||||||
|
soc5200@f0000000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
compatible = "fsl,mpc5200b-immr";
|
||||||
|
ranges = <0 0xf0000000 0x0000c000>;
|
||||||
|
bus-frequency = <0>; // from bootloader
|
||||||
|
system-frequency = <0>; // from bootloader
|
||||||
|
|
||||||
|
cdm@200 {
|
||||||
|
compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
|
||||||
|
reg = <0x200 0x38>;
|
||||||
|
};
|
||||||
|
|
||||||
|
mpc5200_pic: interrupt-controller@500 {
|
||||||
|
// 5200 interrupts are encoded into two levels;
|
||||||
|
interrupt-controller;
|
||||||
|
#interrupt-cells = <3>;
|
||||||
|
compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
|
||||||
|
reg = <0x500 0x80>;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer@600 { // General Purpose Timer
|
||||||
|
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||||
|
reg = <0x600 0x10>;
|
||||||
|
interrupts = <1 9 0>;
|
||||||
|
fsl,has-wdt;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer@610 { // General Purpose Timer
|
||||||
|
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||||
|
reg = <0x610 0x10>;
|
||||||
|
interrupts = <1 10 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
gpt2: timer@620 { // General Purpose Timer in GPIO mode
|
||||||
|
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||||
|
reg = <0x620 0x10>;
|
||||||
|
interrupts = <1 11 0>;
|
||||||
|
gpio-controller;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
gpt3: timer@630 { // General Purpose Timer in GPIO mode
|
||||||
|
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||||
|
reg = <0x630 0x10>;
|
||||||
|
interrupts = <1 12 0>;
|
||||||
|
gpio-controller;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
gpt4: timer@640 { // General Purpose Timer in GPIO mode
|
||||||
|
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||||
|
reg = <0x640 0x10>;
|
||||||
|
interrupts = <1 13 0>;
|
||||||
|
gpio-controller;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
gpt5: timer@650 { // General Purpose Timer in GPIO mode
|
||||||
|
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||||
|
reg = <0x650 0x10>;
|
||||||
|
interrupts = <1 14 0>;
|
||||||
|
gpio-controller;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
gpt6: timer@660 { // General Purpose Timer in GPIO mode
|
||||||
|
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||||
|
reg = <0x660 0x10>;
|
||||||
|
interrupts = <1 15 0>;
|
||||||
|
gpio-controller;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
gpt7: timer@670 { // General Purpose Timer in GPIO mode
|
||||||
|
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||||
|
reg = <0x670 0x10>;
|
||||||
|
interrupts = <1 16 0>;
|
||||||
|
gpio-controller;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
rtc@800 { // Real time clock
|
||||||
|
compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
|
||||||
|
reg = <0x800 0x100>;
|
||||||
|
interrupts = <1 5 0 1 6 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
can@900 {
|
||||||
|
compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
|
||||||
|
interrupts = <2 17 0>;
|
||||||
|
reg = <0x900 0x80>;
|
||||||
|
};
|
||||||
|
|
||||||
|
can@980 {
|
||||||
|
compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
|
||||||
|
interrupts = <2 18 0>;
|
||||||
|
reg = <0x980 0x80>;
|
||||||
|
};
|
||||||
|
|
||||||
|
gpio_simple: gpio@b00 {
|
||||||
|
compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
|
||||||
|
reg = <0xb00 0x40>;
|
||||||
|
interrupts = <1 7 0>;
|
||||||
|
gpio-controller;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
gpio_wkup: gpio@c00 {
|
||||||
|
compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
|
||||||
|
reg = <0xc00 0x40>;
|
||||||
|
interrupts = <1 8 0 0 3 0>;
|
||||||
|
gpio-controller;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
spi@f00 {
|
||||||
|
compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
|
||||||
|
reg = <0xf00 0x20>;
|
||||||
|
interrupts = <2 13 0 2 14 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
usb@1000 {
|
||||||
|
compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
|
||||||
|
reg = <0x1000 0xff>;
|
||||||
|
interrupts = <2 6 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
dma-controller@1200 {
|
||||||
|
compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
|
||||||
|
reg = <0x1200 0x80>;
|
||||||
|
interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
|
||||||
|
3 4 0 3 5 0 3 6 0 3 7 0
|
||||||
|
3 8 0 3 9 0 3 10 0 3 11 0
|
||||||
|
3 12 0 3 13 0 3 14 0 3 15 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
xlb@1f00 {
|
||||||
|
compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
|
||||||
|
reg = <0x1f00 0x100>;
|
||||||
|
};
|
||||||
|
|
||||||
|
ac97@2000 { /* PSC1 is ac97 */
|
||||||
|
compatible = "fsl,mpc5200b-psc-ac97","fsl,mpc5200-psc-ac97";
|
||||||
|
cell-index = <0>;
|
||||||
|
reg = <0x2000 0x100>;
|
||||||
|
interrupts = <2 1 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
/* PSC2 port is used by CAN1/2 */
|
||||||
|
|
||||||
|
serial@2400 { /* PSC3 in UART mode */
|
||||||
|
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||||
|
cell-index = <2>;
|
||||||
|
reg = <0x2400 0x100>;
|
||||||
|
interrupts = <2 3 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
/* PSC4 is ??? */
|
||||||
|
|
||||||
|
/* PSC5 is ??? */
|
||||||
|
|
||||||
|
serial@2c00 { /* PSC6 in UART mode */
|
||||||
|
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||||
|
cell-index = <5>;
|
||||||
|
reg = <0x2c00 0x100>;
|
||||||
|
interrupts = <2 4 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
ethernet@3000 {
|
||||||
|
compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
|
||||||
|
reg = <0x3000 0x400>;
|
||||||
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
|
interrupts = <2 5 0>;
|
||||||
|
phy-handle = <&phy0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
mdio@3000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
|
||||||
|
reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
|
||||||
|
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
|
||||||
|
|
||||||
|
phy0: ethernet-phy@0 {
|
||||||
|
reg = <0>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
ata@3a00 {
|
||||||
|
compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
|
||||||
|
reg = <0x3a00 0x100>;
|
||||||
|
interrupts = <2 7 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
i2c@3d00 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
|
||||||
|
reg = <0x3d00 0x40>;
|
||||||
|
interrupts = <2 15 0>;
|
||||||
|
fsl5200-clocking;
|
||||||
|
};
|
||||||
|
|
||||||
|
i2c@3d40 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
|
||||||
|
reg = <0x3d40 0x40>;
|
||||||
|
interrupts = <2 16 0>;
|
||||||
|
fsl5200-clocking;
|
||||||
|
rtc@51 {
|
||||||
|
compatible = "nxp,pcf8563";
|
||||||
|
reg = <0x51>;
|
||||||
|
};
|
||||||
|
eeprom@52 {
|
||||||
|
compatible = "at24,24c32";
|
||||||
|
reg = <0x52>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
sram@8000 {
|
||||||
|
compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
|
||||||
|
reg = <0x8000 0x4000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
pci@f0000d00 {
|
||||||
|
#interrupt-cells = <1>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
#address-cells = <3>;
|
||||||
|
device_type = "pci";
|
||||||
|
compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
|
||||||
|
reg = <0xf0000d00 0x100>;
|
||||||
|
interrupt-map-mask = <0xf800 0 0 7>;
|
||||||
|
interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
|
||||||
|
0xc000 0 0 2 &mpc5200_pic 1 1 3
|
||||||
|
0xc000 0 0 3 &mpc5200_pic 1 2 3
|
||||||
|
0xc000 0 0 4 &mpc5200_pic 1 3 3
|
||||||
|
|
||||||
|
0xc800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot
|
||||||
|
0xc800 0 0 2 &mpc5200_pic 1 2 3
|
||||||
|
0xc800 0 0 3 &mpc5200_pic 1 3 3
|
||||||
|
0xc800 0 0 4 &mpc5200_pic 0 0 3>;
|
||||||
|
clock-frequency = <0>; // From boot loader
|
||||||
|
interrupts = <2 8 0 2 9 0 2 10 0>;
|
||||||
|
bus-range = <0 0>;
|
||||||
|
ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
|
||||||
|
0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
|
||||||
|
0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
localbus {
|
||||||
|
compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
|
||||||
|
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
|
||||||
|
ranges = <0 0 0xfe000000 0x02000000
|
||||||
|
1 0 0xfc000000 0x02000000
|
||||||
|
2 0 0xfbe00000 0x00200000
|
||||||
|
3 0 0xf9e00000 0x02000000
|
||||||
|
4 0 0xf7e00000 0x02000000
|
||||||
|
5 0 0xe6000000 0x02000000
|
||||||
|
6 0 0xe8000000 0x02000000
|
||||||
|
7 0 0xea000000 0x02000000>;
|
||||||
|
|
||||||
|
flash@0,0 {
|
||||||
|
compatible = "cfi-flash";
|
||||||
|
reg = <0 0 0x02000000>;
|
||||||
|
bank-width = <4>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
|
||||||
|
partition@0 {
|
||||||
|
label = "ubootl";
|
||||||
|
reg = <0x00000000 0x00040000>;
|
||||||
|
};
|
||||||
|
partition@40000 {
|
||||||
|
label = "kernel";
|
||||||
|
reg = <0x00040000 0x001c0000>;
|
||||||
|
};
|
||||||
|
partition@200000 {
|
||||||
|
label = "jffs2";
|
||||||
|
reg = <0x00200000 0x01d00000>;
|
||||||
|
};
|
||||||
|
partition@1f00000 {
|
||||||
|
label = "uboot";
|
||||||
|
reg = <0x01f00000 0x00040000>;
|
||||||
|
};
|
||||||
|
partition@1f40000 {
|
||||||
|
label = "env";
|
||||||
|
reg = <0x01f40000 0x00040000>;
|
||||||
|
};
|
||||||
|
partition@1f80000 {
|
||||||
|
label = "oftree";
|
||||||
|
reg = <0x01f80000 0x00040000>;
|
||||||
|
};
|
||||||
|
partition@1fc0000 {
|
||||||
|
label = "space";
|
||||||
|
reg = <0x01fc0000 0x00040000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
sram@2,0 {
|
||||||
|
compatible = "mtd-ram";
|
||||||
|
reg = <2 0 0x00200000>;
|
||||||
|
bank-width = <2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
/*
|
||||||
|
* example snippets for FPGA
|
||||||
|
*
|
||||||
|
* fpga@3,0 {
|
||||||
|
* compatible = "fpga_driver";
|
||||||
|
* reg = <3 0 0x02000000>;
|
||||||
|
* bank-width = <4>;
|
||||||
|
* };
|
||||||
|
*
|
||||||
|
* fpga@4,0 {
|
||||||
|
* compatible = "fpga_driver";
|
||||||
|
* reg = <4 0 0x02000000>;
|
||||||
|
* bank-width = <4>;
|
||||||
|
* };
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* example snippets for free chipselects
|
||||||
|
*
|
||||||
|
* device@5,0 {
|
||||||
|
* compatible = "custom_driver";
|
||||||
|
* reg = <5 0 0x02000000>;
|
||||||
|
* };
|
||||||
|
*
|
||||||
|
* device@6,0 {
|
||||||
|
* compatible = "custom_driver";
|
||||||
|
* reg = <6 0 0x02000000>;
|
||||||
|
* };
|
||||||
|
*
|
||||||
|
* device@7,0 {
|
||||||
|
* compatible = "custom_driver";
|
||||||
|
* reg = <7 0 0x02000000>;
|
||||||
|
* };
|
||||||
|
*/
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
|
@ -0,0 +1,244 @@
|
||||||
|
/*
|
||||||
|
* Device Tree Source for AMCC Redwood(460SX)
|
||||||
|
*
|
||||||
|
* Copyright 2008 AMCC <tmarri@amcc.com>
|
||||||
|
*
|
||||||
|
* This file is licensed under the terms of the GNU General Public
|
||||||
|
* License version 2. This program is licensed "as is" without
|
||||||
|
* any warranty of any kind, whether express or implied.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
|
||||||
|
/ {
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
model = "amcc,redwood";
|
||||||
|
compatible = "amcc,redwood";
|
||||||
|
dcr-parent = <&{/cpus/cpu@0}>;
|
||||||
|
|
||||||
|
aliases {
|
||||||
|
ethernet0 = &EMAC0;
|
||||||
|
serial0 = &UART0;
|
||||||
|
};
|
||||||
|
|
||||||
|
cpus {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
cpu@0 {
|
||||||
|
device_type = "cpu";
|
||||||
|
model = "PowerPC,460SX";
|
||||||
|
reg = <0x00000000>;
|
||||||
|
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||||
|
timebase-frequency = <0>; /* Filled in by U-Boot */
|
||||||
|
i-cache-line-size = <32>;
|
||||||
|
d-cache-line-size = <32>;
|
||||||
|
i-cache-size = <32768>;
|
||||||
|
d-cache-size = <32768>;
|
||||||
|
dcr-controller;
|
||||||
|
dcr-access-method = "native";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
memory {
|
||||||
|
device_type = "memory";
|
||||||
|
reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
|
||||||
|
};
|
||||||
|
|
||||||
|
UIC0: interrupt-controller0 {
|
||||||
|
compatible = "ibm,uic-460sx","ibm,uic";
|
||||||
|
interrupt-controller;
|
||||||
|
cell-index = <0>;
|
||||||
|
dcr-reg = <0x0c0 0x009>;
|
||||||
|
#address-cells = <0>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
#interrupt-cells = <2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
UIC1: interrupt-controller1 {
|
||||||
|
compatible = "ibm,uic-460sx","ibm,uic";
|
||||||
|
interrupt-controller;
|
||||||
|
cell-index = <1>;
|
||||||
|
dcr-reg = <0x0d0 0x009>;
|
||||||
|
#address-cells = <0>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
#interrupt-cells = <2>;
|
||||||
|
interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
|
||||||
|
interrupt-parent = <&UIC0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
UIC2: interrupt-controller2 {
|
||||||
|
compatible = "ibm,uic-460sx","ibm,uic";
|
||||||
|
interrupt-controller;
|
||||||
|
cell-index = <2>;
|
||||||
|
dcr-reg = <0x0e0 0x009>;
|
||||||
|
#address-cells = <0>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
#interrupt-cells = <2>;
|
||||||
|
interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
|
||||||
|
interrupt-parent = <&UIC0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
UIC3: interrupt-controller3 {
|
||||||
|
compatible = "ibm,uic-460sx","ibm,uic";
|
||||||
|
interrupt-controller;
|
||||||
|
cell-index = <3>;
|
||||||
|
dcr-reg = <0x0f0 0x009>;
|
||||||
|
#address-cells = <0>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
#interrupt-cells = <2>;
|
||||||
|
interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
|
||||||
|
interrupt-parent = <&UIC0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
SDR0: sdr {
|
||||||
|
compatible = "ibm,sdr-460sx";
|
||||||
|
dcr-reg = <0x00e 0x002>;
|
||||||
|
};
|
||||||
|
|
||||||
|
CPR0: cpr {
|
||||||
|
compatible = "ibm,cpr-460sx";
|
||||||
|
dcr-reg = <0x00c 0x002>;
|
||||||
|
};
|
||||||
|
|
||||||
|
plb {
|
||||||
|
compatible = "ibm,plb-460sx", "ibm,plb4";
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
ranges;
|
||||||
|
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||||
|
|
||||||
|
SDRAM0: sdram {
|
||||||
|
compatible = "ibm,sdram-460sx", "ibm,sdram-405gp";
|
||||||
|
dcr-reg = <0x010 0x002>;
|
||||||
|
};
|
||||||
|
|
||||||
|
MAL0: mcmal {
|
||||||
|
compatible = "ibm,mcmal-460sx", "ibm,mcmal2";
|
||||||
|
dcr-reg = <0x180 0x62>;
|
||||||
|
num-tx-chans = <4>;
|
||||||
|
num-rx-chans = <32>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
interrupt-parent = <&UIC1>;
|
||||||
|
interrupts = < /*TXEOB*/ 0x6 0x4
|
||||||
|
/*RXEOB*/ 0x7 0x4
|
||||||
|
/*SERR*/ 0x1 0x4
|
||||||
|
/*TXDE*/ 0x2 0x4
|
||||||
|
/*RXDE*/ 0x3 0x4
|
||||||
|
/*COAL TX0*/ 0x18 0x2
|
||||||
|
/*COAL TX1*/ 0x19 0x2
|
||||||
|
/*COAL TX2*/ 0x1a 0x2
|
||||||
|
/*COAL TX3*/ 0x1b 0x2
|
||||||
|
/*COAL RX0*/ 0x1c 0x2
|
||||||
|
/*COAL RX1*/ 0x1d 0x2
|
||||||
|
/*COAL RX2*/ 0x1e 0x2
|
||||||
|
/*COAL RX3*/ 0x1f 0x2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
POB0: opb {
|
||||||
|
compatible = "ibm,opb-460sx", "ibm,opb";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
|
||||||
|
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||||
|
|
||||||
|
EBC0: ebc {
|
||||||
|
compatible = "ibm,ebc-460sx", "ibm,ebc";
|
||||||
|
dcr-reg = <0x012 0x002>;
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||||
|
/* ranges property is supplied by U-Boot */
|
||||||
|
interrupts = <0x6 0x4>;
|
||||||
|
interrupt-parent = <&UIC1>;
|
||||||
|
|
||||||
|
nor_flash@0,0 {
|
||||||
|
compatible = "amd,s29gl512n", "cfi-flash";
|
||||||
|
bank-width = <2>;
|
||||||
|
reg = <0x0000000 0x00000000 0x04000000>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
partition@0 {
|
||||||
|
label = "kernel";
|
||||||
|
reg = <0x00000000 0x001e0000>;
|
||||||
|
};
|
||||||
|
partition@1e0000 {
|
||||||
|
label = "dtb";
|
||||||
|
reg = <0x001e0000 0x00020000>;
|
||||||
|
};
|
||||||
|
partition@200000 {
|
||||||
|
label = "ramdisk";
|
||||||
|
reg = <0x00200000 0x01400000>;
|
||||||
|
};
|
||||||
|
partition@1600000 {
|
||||||
|
label = "jffs2";
|
||||||
|
reg = <0x01600000 0x00400000>;
|
||||||
|
};
|
||||||
|
partition@1a00000 {
|
||||||
|
label = "user";
|
||||||
|
reg = <0x01a00000 0x02560000>;
|
||||||
|
};
|
||||||
|
partition@3f60000 {
|
||||||
|
label = "env";
|
||||||
|
reg = <0x03f60000 0x00040000>;
|
||||||
|
};
|
||||||
|
partition@3fa0000 {
|
||||||
|
label = "u-boot";
|
||||||
|
reg = <0x03fa0000 0x00060000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
UART0: serial@ef600200 {
|
||||||
|
device_type = "serial";
|
||||||
|
compatible = "ns16550";
|
||||||
|
reg = <0xef600200 0x00000008>;
|
||||||
|
virtual-reg = <0xef600200>;
|
||||||
|
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||||
|
current-speed = <0>; /* Filled in by U-Boot */
|
||||||
|
interrupt-parent = <&UIC0>;
|
||||||
|
interrupts = <0x0 0x4>;
|
||||||
|
};
|
||||||
|
|
||||||
|
RGMII0: emac-rgmii@ef600900 {
|
||||||
|
compatible = "ibm,rgmii-460sx", "ibm,rgmii";
|
||||||
|
reg = <0xef600900 0x00000008>;
|
||||||
|
};
|
||||||
|
|
||||||
|
EMAC0: ethernet@ef600a00 {
|
||||||
|
device_type = "network";
|
||||||
|
compatible = "ibm,emac-460sx", "ibm,emac4";
|
||||||
|
interrupt-parent = <&EMAC0>;
|
||||||
|
interrupts = <0x0 0x1>;
|
||||||
|
#interrupt-cells = <1>;
|
||||||
|
#address-cells = <0>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
interrupt-map = </*Status*/ 0x0 &UIC0 0x13 0x4
|
||||||
|
/*Wake*/ 0x1 &UIC2 0x1d 0x4>;
|
||||||
|
reg = <0xef600a00 0x00000070>;
|
||||||
|
local-mac-address = [000000000000]; /* Filled in by U-Boot */
|
||||||
|
mal-device = <&MAL0>;
|
||||||
|
mal-tx-channel = <0>;
|
||||||
|
mal-rx-channel = <0>;
|
||||||
|
cell-index = <0>;
|
||||||
|
max-frame-size = <9000>;
|
||||||
|
rx-fifo-size = <4096>;
|
||||||
|
tx-fifo-size = <2048>;
|
||||||
|
phy-mode = "rgmii";
|
||||||
|
phy-map = <0x00000000>;
|
||||||
|
rgmii-device = <&RGMII0>;
|
||||||
|
rgmii-channel = <0>;
|
||||||
|
has-inverted-stacr-oc;
|
||||||
|
has-new-stacr-staopc;
|
||||||
|
};
|
||||||
|
|
||||||
|
};
|
||||||
|
|
||||||
|
};
|
||||||
|
chosen {
|
||||||
|
linux,stdout-path = "/plb/opb/serial@ef600200";
|
||||||
|
};
|
||||||
|
|
||||||
|
};
|
||||||
|
|
@ -159,68 +159,76 @@
|
||||||
phy_type = "ulpi";
|
phy_type = "ulpi";
|
||||||
};
|
};
|
||||||
|
|
||||||
mdio@24520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-mdio";
|
|
||||||
reg = <0x24520 0x20>;
|
|
||||||
|
|
||||||
phy0: ethernet-phy@19 {
|
|
||||||
interrupt-parent = <&ipic>;
|
|
||||||
interrupts = <20 0x8>;
|
|
||||||
reg = <0x19>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
phy1: ethernet-phy@1a {
|
|
||||||
interrupt-parent = <&ipic>;
|
|
||||||
interrupts = <21 0x8>;
|
|
||||||
reg = <0x1a>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
tbi0: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
mdio@25520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-tbi";
|
|
||||||
reg = <0x25520 0x20>;
|
|
||||||
|
|
||||||
tbi1: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
enet0: ethernet@24000 {
|
enet0: ethernet@24000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <0>;
|
cell-index = <0>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "TSEC";
|
model = "TSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x24000 0x1000>;
|
reg = <0x24000 0x1000>;
|
||||||
|
ranges = <0x0 0x24000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <32 0x8 33 0x8 34 0x8>;
|
interrupts = <32 0x8 33 0x8 34 0x8>;
|
||||||
interrupt-parent = <&ipic>;
|
interrupt-parent = <&ipic>;
|
||||||
tbi-handle = <&tbi0>;
|
tbi-handle = <&tbi0>;
|
||||||
phy-handle = <&phy0>;
|
phy-handle = <&phy0>;
|
||||||
linux,network-index = <0>;
|
linux,network-index = <0>;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-mdio";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
phy0: ethernet-phy@19 {
|
||||||
|
interrupt-parent = <&ipic>;
|
||||||
|
interrupts = <20 0x8>;
|
||||||
|
reg = <0x19>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
|
||||||
|
phy1: ethernet-phy@1a {
|
||||||
|
interrupt-parent = <&ipic>;
|
||||||
|
interrupts = <21 0x8>;
|
||||||
|
reg = <0x1a>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
|
||||||
|
tbi0: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
enet1: ethernet@25000 {
|
enet1: ethernet@25000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <1>;
|
cell-index = <1>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "TSEC";
|
model = "TSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x25000 0x1000>;
|
reg = <0x25000 0x1000>;
|
||||||
|
ranges = <0x0 0x25000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <35 0x8 36 0x8 37 0x8>;
|
interrupts = <35 0x8 36 0x8 37 0x8>;
|
||||||
interrupt-parent = <&ipic>;
|
interrupt-parent = <&ipic>;
|
||||||
tbi-handle = <&tbi1>;
|
tbi-handle = <&tbi1>;
|
||||||
phy-handle = <&phy1>;
|
phy-handle = <&phy1>;
|
||||||
linux,network-index = <1>;
|
linux,network-index = <1>;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-tbi";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
tbi1: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
serial0: serial@4500 {
|
serial0: serial@4500 {
|
||||||
|
|
|
||||||
|
|
@ -234,66 +234,72 @@
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
mdio@24520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-mdio";
|
|
||||||
reg = <0x24520 0x20>;
|
|
||||||
|
|
||||||
phy0: ethernet-phy@19 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <0x6 0x1>;
|
|
||||||
reg = <0x19>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
phy1: ethernet-phy@1a {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <0x7 0x1>;
|
|
||||||
reg = <0x1a>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
tbi0: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
mdio@25520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-tbi";
|
|
||||||
reg = <0x25520 0x20>;
|
|
||||||
|
|
||||||
tbi1: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
enet0: ethernet@24000 {
|
enet0: ethernet@24000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <0>;
|
cell-index = <0>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "eTSEC";
|
model = "eTSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x24000 0x1000>;
|
reg = <0x24000 0x1000>;
|
||||||
|
ranges = <0x0 0x24000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
|
interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
tbi-handle = <&tbi0>;
|
tbi-handle = <&tbi0>;
|
||||||
phy-handle = <&phy0>;
|
phy-handle = <&phy0>;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-mdio";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
phy0: ethernet-phy@19 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <0x6 0x1>;
|
||||||
|
reg = <0x19>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
phy1: ethernet-phy@1a {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <0x7 0x1>;
|
||||||
|
reg = <0x1a>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
tbi0: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
enet1: ethernet@25000 {
|
enet1: ethernet@25000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <1>;
|
cell-index = <1>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "eTSEC";
|
model = "eTSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x25000 0x1000>;
|
reg = <0x25000 0x1000>;
|
||||||
|
ranges = <0x0 0x25000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>;
|
interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
tbi-handle = <&tbi1>;
|
tbi-handle = <&tbi1>;
|
||||||
phy-handle = <&phy1>;
|
phy-handle = <&phy1>;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-tbi";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
tbi1: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
serial0: serial@4500 {
|
serial0: serial@4500 {
|
||||||
|
|
|
||||||
|
|
@ -139,77 +139,83 @@
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
mdio@24520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-mdio";
|
|
||||||
reg = <0x24520 0x20>;
|
|
||||||
phy0: ethernet-phy@19 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <0x6 0x1>;
|
|
||||||
reg = <0x19>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
phy1: ethernet-phy@1a {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <0x7 0x1>;
|
|
||||||
reg = <0x1a>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
phy2: ethernet-phy@1b {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <0x8 0x1>;
|
|
||||||
reg = <0x1b>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
phy3: ethernet-phy@1c {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <0x8 0x1>;
|
|
||||||
reg = <0x1c>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
tbi0: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
mdio@25520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-tbi";
|
|
||||||
reg = <0x25520 0x20>;
|
|
||||||
|
|
||||||
tbi1: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
enet0: ethernet@24000 {
|
enet0: ethernet@24000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <0>;
|
cell-index = <0>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "TSEC";
|
model = "TSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x24000 0x1000>;
|
reg = <0x24000 0x1000>;
|
||||||
|
ranges = <0x0 0x24000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
|
interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
tbi-handle = <&tbi0>;
|
tbi-handle = <&tbi0>;
|
||||||
phy-handle = <&phy0>;
|
phy-handle = <&phy0>;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-mdio";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
phy0: ethernet-phy@19 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <0x6 0x1>;
|
||||||
|
reg = <0x19>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
phy1: ethernet-phy@1a {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <0x7 0x1>;
|
||||||
|
reg = <0x1a>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
phy2: ethernet-phy@1b {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <0x8 0x1>;
|
||||||
|
reg = <0x1b>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
phy3: ethernet-phy@1c {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <0x8 0x1>;
|
||||||
|
reg = <0x1c>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
tbi0: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
enet1: ethernet@25000 {
|
enet1: ethernet@25000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <1>;
|
cell-index = <1>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "TSEC";
|
model = "TSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x25000 0x1000>;
|
reg = <0x25000 0x1000>;
|
||||||
|
ranges = <0x0 0x25000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>;
|
interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
tbi-handle = <&tbi1>;
|
tbi-handle = <&tbi1>;
|
||||||
phy-handle = <&phy1>;
|
phy-handle = <&phy1>;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-tbi";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
tbi1: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
mpic: pic@40000 {
|
mpic: pic@40000 {
|
||||||
|
|
|
||||||
|
|
@ -192,132 +192,144 @@
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
mdio@24520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-mdio";
|
|
||||||
reg = <0x24520 0x20>;
|
|
||||||
|
|
||||||
phy0: ethernet-phy@1f {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <10 1>;
|
|
||||||
reg = <0x1f>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
phy1: ethernet-phy@0 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <10 1>;
|
|
||||||
reg = <0>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
phy2: ethernet-phy@1 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <10 1>;
|
|
||||||
reg = <1>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
phy3: ethernet-phy@2 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <10 1>;
|
|
||||||
reg = <2>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
tbi0: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
mdio@25520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-tbi";
|
|
||||||
reg = <0x25520 0x20>;
|
|
||||||
|
|
||||||
tbi1: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
mdio@26520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-tbi";
|
|
||||||
reg = <0x26520 0x20>;
|
|
||||||
|
|
||||||
tbi2: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
mdio@27520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-tbi";
|
|
||||||
reg = <0x27520 0x20>;
|
|
||||||
|
|
||||||
tbi3: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
enet0: ethernet@24000 {
|
enet0: ethernet@24000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <0>;
|
cell-index = <0>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "TSEC";
|
model = "TSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x24000 0x1000>;
|
reg = <0x24000 0x1000>;
|
||||||
|
ranges = <0x0 0x24000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <29 2 30 2 34 2>;
|
interrupts = <29 2 30 2 34 2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
tbi-handle = <&tbi0>;
|
tbi-handle = <&tbi0>;
|
||||||
phy-handle = <&phy0>;
|
phy-handle = <&phy0>;
|
||||||
phy-connection-type = "rgmii-id";
|
phy-connection-type = "rgmii-id";
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-mdio";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
phy0: ethernet-phy@1f {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <10 1>;
|
||||||
|
reg = <0x1f>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
phy1: ethernet-phy@0 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <10 1>;
|
||||||
|
reg = <0>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
phy2: ethernet-phy@1 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <10 1>;
|
||||||
|
reg = <1>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
phy3: ethernet-phy@2 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <10 1>;
|
||||||
|
reg = <2>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
tbi0: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
enet1: ethernet@25000 {
|
enet1: ethernet@25000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <1>;
|
cell-index = <1>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "TSEC";
|
model = "TSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x25000 0x1000>;
|
reg = <0x25000 0x1000>;
|
||||||
|
ranges = <0x0 0x25000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <35 2 36 2 40 2>;
|
interrupts = <35 2 36 2 40 2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
tbi-handle = <&tbi1>;
|
tbi-handle = <&tbi1>;
|
||||||
phy-handle = <&phy1>;
|
phy-handle = <&phy1>;
|
||||||
phy-connection-type = "rgmii-id";
|
phy-connection-type = "rgmii-id";
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-tbi";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
tbi1: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
enet2: ethernet@26000 {
|
enet2: ethernet@26000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <2>;
|
cell-index = <2>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "TSEC";
|
model = "TSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x26000 0x1000>;
|
reg = <0x26000 0x1000>;
|
||||||
|
ranges = <0x0 0x26000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <31 2 32 2 33 2>;
|
interrupts = <31 2 32 2 33 2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
tbi-handle = <&tbi2>;
|
tbi-handle = <&tbi2>;
|
||||||
phy-handle = <&phy2>;
|
phy-handle = <&phy2>;
|
||||||
phy-connection-type = "rgmii-id";
|
phy-connection-type = "rgmii-id";
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-tbi";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
tbi2: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
enet3: ethernet@27000 {
|
enet3: ethernet@27000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <3>;
|
cell-index = <3>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "TSEC";
|
model = "TSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x27000 0x1000>;
|
reg = <0x27000 0x1000>;
|
||||||
|
ranges = <0x0 0x27000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <37 2 38 2 39 2>;
|
interrupts = <37 2 38 2 39 2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
tbi-handle = <&tbi3>;
|
tbi-handle = <&tbi3>;
|
||||||
phy-handle = <&phy3>;
|
phy-handle = <&phy3>;
|
||||||
phy-connection-type = "rgmii-id";
|
phy-connection-type = "rgmii-id";
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-tbi";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
tbi3: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
serial0: serial@4500 {
|
serial0: serial@4500 {
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,338 @@
|
||||||
|
/*
|
||||||
|
* Device Tree Source for the Socrates board (MPC8544).
|
||||||
|
*
|
||||||
|
* Copyright (c) 2008 Emcraft Systems.
|
||||||
|
* Sergei Poselenov, <sposelenov@emcraft.com>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms of the GNU General Public License as published by the
|
||||||
|
* Free Software Foundation; either version 2 of the License, or (at your
|
||||||
|
* option) any later version.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "abb,socrates";
|
||||||
|
compatible = "abb,socrates";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
|
||||||
|
aliases {
|
||||||
|
ethernet0 = &enet0;
|
||||||
|
ethernet1 = &enet1;
|
||||||
|
serial0 = &serial0;
|
||||||
|
serial1 = &serial1;
|
||||||
|
pci0 = &pci0;
|
||||||
|
};
|
||||||
|
|
||||||
|
cpus {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
PowerPC,8544@0 {
|
||||||
|
device_type = "cpu";
|
||||||
|
reg = <0>;
|
||||||
|
d-cache-line-size = <32>;
|
||||||
|
i-cache-line-size = <32>;
|
||||||
|
d-cache-size = <0x8000>; // L1, 32K
|
||||||
|
i-cache-size = <0x8000>; // L1, 32K
|
||||||
|
timebase-frequency = <0>;
|
||||||
|
bus-frequency = <0>;
|
||||||
|
clock-frequency = <0>;
|
||||||
|
next-level-cache = <&L2>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
memory {
|
||||||
|
device_type = "memory";
|
||||||
|
reg = <0x00000000 0x00000000>; // Filled in by U-Boot
|
||||||
|
};
|
||||||
|
|
||||||
|
soc8544@e0000000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
|
||||||
|
ranges = <0x00000000 0xe0000000 0x00100000>;
|
||||||
|
reg = <0xe0000000 0x00001000>; // CCSRBAR 1M
|
||||||
|
bus-frequency = <0>; // Filled in by U-Boot
|
||||||
|
compatible = "fsl,mpc8544-immr", "simple-bus";
|
||||||
|
|
||||||
|
memory-controller@2000 {
|
||||||
|
compatible = "fsl,mpc8544-memory-controller";
|
||||||
|
reg = <0x2000 0x1000>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <18 2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
L2: l2-cache-controller@20000 {
|
||||||
|
compatible = "fsl,mpc8544-l2-cache-controller";
|
||||||
|
reg = <0x20000 0x1000>;
|
||||||
|
cache-line-size = <32>;
|
||||||
|
cache-size = <0x40000>; // L2, 256K
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <16 2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
i2c@3000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
cell-index = <0>;
|
||||||
|
compatible = "fsl-i2c";
|
||||||
|
reg = <0x3000 0x100>;
|
||||||
|
interrupts = <43 2>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
dfsrr;
|
||||||
|
|
||||||
|
dtt@28 {
|
||||||
|
compatible = "winbond,w83782d";
|
||||||
|
reg = <0x28>;
|
||||||
|
};
|
||||||
|
rtc@32 {
|
||||||
|
compatible = "epson,rx8025";
|
||||||
|
reg = <0x32>;
|
||||||
|
interrupts = <7 1>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
};
|
||||||
|
dtt@4c {
|
||||||
|
compatible = "dallas,ds75";
|
||||||
|
reg = <0x4c>;
|
||||||
|
};
|
||||||
|
ts@4a {
|
||||||
|
compatible = "ti,tsc2003";
|
||||||
|
reg = <0x4a>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <8 1>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
i2c@3100 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
cell-index = <1>;
|
||||||
|
compatible = "fsl-i2c";
|
||||||
|
reg = <0x3100 0x100>;
|
||||||
|
interrupts = <43 2>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
dfsrr;
|
||||||
|
};
|
||||||
|
|
||||||
|
enet0: ethernet@24000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
cell-index = <0>;
|
||||||
|
device_type = "network";
|
||||||
|
model = "eTSEC";
|
||||||
|
compatible = "gianfar";
|
||||||
|
reg = <0x24000 0x1000>;
|
||||||
|
ranges = <0x0 0x24000 0x1000>;
|
||||||
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
|
interrupts = <29 2 30 2 34 2>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
phy-handle = <&phy0>;
|
||||||
|
tbi-handle = <&tbi0>;
|
||||||
|
phy-connection-type = "rgmii-id";
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-mdio";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
phy0: ethernet-phy@0 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <0 1>;
|
||||||
|
reg = <0>;
|
||||||
|
};
|
||||||
|
phy1: ethernet-phy@1 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <0 1>;
|
||||||
|
reg = <1>;
|
||||||
|
};
|
||||||
|
tbi0: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
enet1: ethernet@26000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
cell-index = <1>;
|
||||||
|
device_type = "network";
|
||||||
|
model = "eTSEC";
|
||||||
|
compatible = "gianfar";
|
||||||
|
reg = <0x26000 0x1000>;
|
||||||
|
ranges = <0x0 0x26000 0x1000>;
|
||||||
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
|
interrupts = <31 2 32 2 33 2>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
phy-handle = <&phy1>;
|
||||||
|
tbi-handle = <&tbi1>;
|
||||||
|
phy-connection-type = "rgmii-id";
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-tbi";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
tbi1: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
serial0: serial@4500 {
|
||||||
|
cell-index = <0>;
|
||||||
|
device_type = "serial";
|
||||||
|
compatible = "ns16550";
|
||||||
|
reg = <0x4500 0x100>;
|
||||||
|
clock-frequency = <0>;
|
||||||
|
interrupts = <42 2>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
};
|
||||||
|
|
||||||
|
serial1: serial@4600 {
|
||||||
|
cell-index = <1>;
|
||||||
|
device_type = "serial";
|
||||||
|
compatible = "ns16550";
|
||||||
|
reg = <0x4600 0x100>;
|
||||||
|
clock-frequency = <0>;
|
||||||
|
interrupts = <42 2>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
};
|
||||||
|
|
||||||
|
global-utilities@e0000 { //global utilities block
|
||||||
|
compatible = "fsl,mpc8548-guts";
|
||||||
|
reg = <0xe0000 0x1000>;
|
||||||
|
fsl,has-rstcr;
|
||||||
|
};
|
||||||
|
|
||||||
|
mpic: pic@40000 {
|
||||||
|
interrupt-controller;
|
||||||
|
#address-cells = <0>;
|
||||||
|
#interrupt-cells = <2>;
|
||||||
|
reg = <0x40000 0x40000>;
|
||||||
|
compatible = "chrp,open-pic";
|
||||||
|
device_type = "open-pic";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
|
||||||
|
localbus {
|
||||||
|
compatible = "fsl,mpc8544-localbus",
|
||||||
|
"fsl,pq3-localbus",
|
||||||
|
"simple-bus";
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
reg = <0xe0005000 0x40>;
|
||||||
|
|
||||||
|
ranges = <0 0 0xfc000000 0x04000000
|
||||||
|
2 0 0xc8000000 0x04000000
|
||||||
|
3 0 0xc0000000 0x00100000
|
||||||
|
>; /* Overwritten by U-Boot */
|
||||||
|
|
||||||
|
nor_flash@0,0 {
|
||||||
|
compatible = "amd,s29gl256n", "cfi-flash";
|
||||||
|
bank-width = <2>;
|
||||||
|
reg = <0x0 0x000000 0x4000000>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
partition@0 {
|
||||||
|
label = "kernel";
|
||||||
|
reg = <0x0 0x1e0000>;
|
||||||
|
read-only;
|
||||||
|
};
|
||||||
|
partition@1e0000 {
|
||||||
|
label = "dtb";
|
||||||
|
reg = <0x1e0000 0x20000>;
|
||||||
|
};
|
||||||
|
partition@200000 {
|
||||||
|
label = "root";
|
||||||
|
reg = <0x200000 0x200000>;
|
||||||
|
};
|
||||||
|
partition@400000 {
|
||||||
|
label = "user";
|
||||||
|
reg = <0x400000 0x3b80000>;
|
||||||
|
};
|
||||||
|
partition@3f80000 {
|
||||||
|
label = "env";
|
||||||
|
reg = <0x3f80000 0x40000>;
|
||||||
|
read-only;
|
||||||
|
};
|
||||||
|
partition@3fc0000 {
|
||||||
|
label = "u-boot";
|
||||||
|
reg = <0x3fc0000 0x40000>;
|
||||||
|
read-only;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
display@2,0 {
|
||||||
|
compatible = "fujitsu,lime";
|
||||||
|
reg = <2 0x0 0x4000000>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <6 1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
fpga_pic: fpga-pic@3,10 {
|
||||||
|
compatible = "abb,socrates-fpga-pic";
|
||||||
|
reg = <3 0x10 0x10>;
|
||||||
|
interrupt-controller;
|
||||||
|
/* IRQs 2, 10, 11, active low, level-sensitive */
|
||||||
|
interrupts = <2 1 10 1 11 1>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
#interrupt-cells = <3>;
|
||||||
|
};
|
||||||
|
|
||||||
|
spi@3,60 {
|
||||||
|
compatible = "abb,socrates-spi";
|
||||||
|
reg = <3 0x60 0x10>;
|
||||||
|
interrupts = <8 4 0>; // number, type, routing
|
||||||
|
interrupt-parent = <&fpga_pic>;
|
||||||
|
};
|
||||||
|
|
||||||
|
nand@3,70 {
|
||||||
|
compatible = "abb,socrates-nand";
|
||||||
|
reg = <3 0x70 0x04>;
|
||||||
|
bank-width = <1>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
data@0 {
|
||||||
|
label = "data";
|
||||||
|
reg = <0x0 0x40000000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
can@3,100 {
|
||||||
|
compatible = "philips,sja1000";
|
||||||
|
reg = <3 0x100 0x80>;
|
||||||
|
interrupts = <2 8 1>; // number, type, routing
|
||||||
|
interrupt-parent = <&fpga_pic>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
pci0: pci@e0008000 {
|
||||||
|
cell-index = <0>;
|
||||||
|
#interrupt-cells = <1>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
#address-cells = <3>;
|
||||||
|
compatible = "fsl,mpc8540-pci";
|
||||||
|
device_type = "pci";
|
||||||
|
reg = <0xe0008000 0x1000>;
|
||||||
|
clock-frequency = <66666666>;
|
||||||
|
|
||||||
|
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||||
|
interrupt-map = <
|
||||||
|
/* IDSEL 0x11 */
|
||||||
|
0x8800 0x0 0x0 1 &mpic 5 1
|
||||||
|
/* IDSEL 0x12 */
|
||||||
|
0x9000 0x0 0x0 1 &mpic 4 1>;
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <24 2>;
|
||||||
|
bus-range = <0x0 0x0>;
|
||||||
|
ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
|
||||||
|
0x01000000 0x0 0x00000000 0xe2000000 0x0 0x01000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
};
|
||||||
|
|
@ -124,66 +124,72 @@
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
mdio@24520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-mdio";
|
|
||||||
reg = <0x24520 0x20>;
|
|
||||||
|
|
||||||
phy2: ethernet-phy@2 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <5 4>;
|
|
||||||
reg = <2>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
phy4: ethernet-phy@4 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <5 4>;
|
|
||||||
reg = <4>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
tbi0: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
mdio@25520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-tbi";
|
|
||||||
reg = <0x25520 0x20>;
|
|
||||||
|
|
||||||
tbi1: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
enet0: ethernet@24000 {
|
enet0: ethernet@24000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <0>;
|
cell-index = <0>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "TSEC";
|
model = "TSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x24000 0x1000>;
|
reg = <0x24000 0x1000>;
|
||||||
|
ranges = <0x0 0x24000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <29 2 30 2 34 2>;
|
interrupts = <29 2 30 2 34 2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
tbi-handle = <&tbi0>;
|
tbi-handle = <&tbi0>;
|
||||||
phy-handle = <&phy2>;
|
phy-handle = <&phy2>;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-mdio";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
phy2: ethernet-phy@2 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <5 4>;
|
||||||
|
reg = <2>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
phy4: ethernet-phy@4 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <5 4>;
|
||||||
|
reg = <4>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
tbi0: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
enet1: ethernet@25000 {
|
enet1: ethernet@25000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <1>;
|
cell-index = <1>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "TSEC";
|
model = "TSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x25000 0x1000>;
|
reg = <0x25000 0x1000>;
|
||||||
|
ranges = <0x0 0x25000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <35 2 36 2 40 2>;
|
interrupts = <35 2 36 2 40 2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
tbi-handle = <&tbi1>;
|
tbi-handle = <&tbi1>;
|
||||||
phy-handle = <&phy4>;
|
phy-handle = <&phy4>;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-tbi";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
tbi1: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
mpic: pic@40000 {
|
mpic: pic@40000 {
|
||||||
|
|
|
||||||
|
|
@ -17,6 +17,7 @@
|
||||||
compatible = "tqc,tqm5200";
|
compatible = "tqc,tqm5200";
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <1>;
|
#size-cells = <1>;
|
||||||
|
interrupt-parent = <&mpc5200_pic>;
|
||||||
|
|
||||||
cpus {
|
cpus {
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
|
|
@ -66,36 +67,33 @@
|
||||||
compatible = "fsl,mpc5200-gpt";
|
compatible = "fsl,mpc5200-gpt";
|
||||||
reg = <0x600 0x10>;
|
reg = <0x600 0x10>;
|
||||||
interrupts = <1 9 0>;
|
interrupts = <1 9 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
fsl,has-wdt;
|
fsl,has-wdt;
|
||||||
};
|
};
|
||||||
|
|
||||||
can@900 {
|
can@900 {
|
||||||
compatible = "fsl,mpc5200-mscan";
|
compatible = "fsl,mpc5200-mscan";
|
||||||
interrupts = <2 17 0>;
|
interrupts = <2 17 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
reg = <0x900 0x80>;
|
reg = <0x900 0x80>;
|
||||||
};
|
};
|
||||||
|
|
||||||
can@980 {
|
can@980 {
|
||||||
compatible = "fsl,mpc5200-mscan";
|
compatible = "fsl,mpc5200-mscan";
|
||||||
interrupts = <2 18 0>;
|
interrupts = <2 18 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
reg = <0x980 0x80>;
|
reg = <0x980 0x80>;
|
||||||
};
|
};
|
||||||
|
|
||||||
gpio@b00 {
|
gpio_simple: gpio@b00 {
|
||||||
compatible = "fsl,mpc5200-gpio";
|
compatible = "fsl,mpc5200-gpio";
|
||||||
reg = <0xb00 0x40>;
|
reg = <0xb00 0x40>;
|
||||||
interrupts = <1 7 0>;
|
interrupts = <1 7 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
gpio-controller;
|
||||||
|
#gpio-cells = <2>;
|
||||||
};
|
};
|
||||||
|
|
||||||
usb@1000 {
|
usb@1000 {
|
||||||
compatible = "fsl,mpc5200-ohci","ohci-be";
|
compatible = "fsl,mpc5200-ohci","ohci-be";
|
||||||
reg = <0x1000 0xff>;
|
reg = <0x1000 0xff>;
|
||||||
interrupts = <2 6 0>;
|
interrupts = <2 6 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
dma-controller@1200 {
|
dma-controller@1200 {
|
||||||
|
|
@ -105,7 +103,6 @@
|
||||||
3 4 0 3 5 0 3 6 0 3 7 0
|
3 4 0 3 5 0 3 6 0 3 7 0
|
||||||
3 8 0 3 9 0 3 10 0 3 11 0
|
3 8 0 3 9 0 3 10 0 3 11 0
|
||||||
3 12 0 3 13 0 3 14 0 3 15 0>;
|
3 12 0 3 13 0 3 14 0 3 15 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
xlb@1f00 {
|
xlb@1f00 {
|
||||||
|
|
@ -114,39 +111,28 @@
|
||||||
};
|
};
|
||||||
|
|
||||||
serial@2000 { // PSC1
|
serial@2000 { // PSC1
|
||||||
device_type = "serial";
|
|
||||||
compatible = "fsl,mpc5200-psc-uart";
|
compatible = "fsl,mpc5200-psc-uart";
|
||||||
port-number = <0>; // Logical port assignment
|
|
||||||
reg = <0x2000 0x100>;
|
reg = <0x2000 0x100>;
|
||||||
interrupts = <2 1 0>;
|
interrupts = <2 1 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
serial@2200 { // PSC2
|
serial@2200 { // PSC2
|
||||||
device_type = "serial";
|
|
||||||
compatible = "fsl,mpc5200-psc-uart";
|
compatible = "fsl,mpc5200-psc-uart";
|
||||||
port-number = <1>; // Logical port assignment
|
|
||||||
reg = <0x2200 0x100>;
|
reg = <0x2200 0x100>;
|
||||||
interrupts = <2 2 0>;
|
interrupts = <2 2 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
serial@2400 { // PSC3
|
serial@2400 { // PSC3
|
||||||
device_type = "serial";
|
|
||||||
compatible = "fsl,mpc5200-psc-uart";
|
compatible = "fsl,mpc5200-psc-uart";
|
||||||
port-number = <2>; // Logical port assignment
|
|
||||||
reg = <0x2400 0x100>;
|
reg = <0x2400 0x100>;
|
||||||
interrupts = <2 3 0>;
|
interrupts = <2 3 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
ethernet@3000 {
|
ethernet@3000 {
|
||||||
device_type = "network";
|
|
||||||
compatible = "fsl,mpc5200-fec";
|
compatible = "fsl,mpc5200-fec";
|
||||||
reg = <0x3000 0x400>;
|
reg = <0x3000 0x400>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <2 5 0>;
|
interrupts = <2 5 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
phy-handle = <&phy0>;
|
phy-handle = <&phy0>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -156,10 +142,8 @@
|
||||||
compatible = "fsl,mpc5200-mdio";
|
compatible = "fsl,mpc5200-mdio";
|
||||||
reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
|
reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
|
||||||
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
|
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
|
|
||||||
phy0: ethernet-phy@0 {
|
phy0: ethernet-phy@0 {
|
||||||
device_type = "ethernet-phy";
|
|
||||||
reg = <0>;
|
reg = <0>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
@ -168,7 +152,6 @@
|
||||||
compatible = "fsl,mpc5200-ata";
|
compatible = "fsl,mpc5200-ata";
|
||||||
reg = <0x3a00 0x100>;
|
reg = <0x3a00 0x100>;
|
||||||
interrupts = <2 7 0>;
|
interrupts = <2 7 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
i2c@3d40 {
|
i2c@3d40 {
|
||||||
|
|
@ -177,7 +160,6 @@
|
||||||
compatible = "fsl,mpc5200-i2c","fsl-i2c";
|
compatible = "fsl,mpc5200-i2c","fsl-i2c";
|
||||||
reg = <0x3d40 0x40>;
|
reg = <0x3d40 0x40>;
|
||||||
interrupts = <2 16 0>;
|
interrupts = <2 16 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
fsl5200-clocking;
|
fsl5200-clocking;
|
||||||
|
|
||||||
rtc@68 {
|
rtc@68 {
|
||||||
|
|
@ -192,9 +174,8 @@
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
lpb {
|
localbus {
|
||||||
model = "fsl,lpb";
|
compatible = "fsl,mpc5200-lpb","simple-bus";
|
||||||
compatible = "fsl,lpb";
|
|
||||||
#address-cells = <2>;
|
#address-cells = <2>;
|
||||||
#size-cells = <1>;
|
#size-cells = <1>;
|
||||||
ranges = <0 0 0xfc000000 0x02000000>;
|
ranges = <0 0 0xfc000000 0x02000000>;
|
||||||
|
|
@ -223,7 +204,6 @@
|
||||||
0xc000 0 0 4 &mpc5200_pic 0 0 3>;
|
0xc000 0 0 4 &mpc5200_pic 0 0 3>;
|
||||||
clock-frequency = <0>; // From boot loader
|
clock-frequency = <0>; // From boot loader
|
||||||
interrupts = <2 8 0 2 9 0 2 10 0>;
|
interrupts = <2 8 0 2 9 0 2 10 0>;
|
||||||
interrupt-parent = <&mpc5200_pic>;
|
|
||||||
bus-range = <0 0>;
|
bus-range = <0 0>;
|
||||||
ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000
|
ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000
|
||||||
0x02000000 0 0x90000000 0x90000000 0 0x10000000
|
0x02000000 0 0x90000000 0x90000000 0 0x10000000
|
||||||
|
|
|
||||||
|
|
@ -84,6 +84,11 @@
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
dfsrr;
|
dfsrr;
|
||||||
|
|
||||||
|
dtt@50 {
|
||||||
|
compatible = "national,lm75";
|
||||||
|
reg = <0x50>;
|
||||||
|
};
|
||||||
|
|
||||||
rtc@68 {
|
rtc@68 {
|
||||||
compatible = "dallas,ds1337";
|
compatible = "dallas,ds1337";
|
||||||
reg = <0x68>;
|
reg = <0x68>;
|
||||||
|
|
@ -131,94 +136,103 @@
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
mdio@24520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-mdio";
|
|
||||||
reg = <0x24520 0x20>;
|
|
||||||
|
|
||||||
phy1: ethernet-phy@1 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <8 1>;
|
|
||||||
reg = <1>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
phy2: ethernet-phy@2 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <8 1>;
|
|
||||||
reg = <2>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
phy3: ethernet-phy@3 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <8 1>;
|
|
||||||
reg = <3>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
tbi0: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
mdio@25520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-tbi";
|
|
||||||
reg = <0x25520 0x20>;
|
|
||||||
|
|
||||||
tbi1: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
mdio@26520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-tbi";
|
|
||||||
reg = <0x26520 0x20>;
|
|
||||||
|
|
||||||
tbi2: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
enet0: ethernet@24000 {
|
enet0: ethernet@24000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <0>;
|
cell-index = <0>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "TSEC";
|
model = "TSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x24000 0x1000>;
|
reg = <0x24000 0x1000>;
|
||||||
|
ranges = <0x0 0x24000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <29 2 30 2 34 2>;
|
interrupts = <29 2 30 2 34 2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
phy-handle = <&phy2>;
|
phy-handle = <&phy2>;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-mdio";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
phy1: ethernet-phy@1 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <8 1>;
|
||||||
|
reg = <1>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
phy2: ethernet-phy@2 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <8 1>;
|
||||||
|
reg = <2>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
phy3: ethernet-phy@3 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <8 1>;
|
||||||
|
reg = <3>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
tbi0: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
enet1: ethernet@25000 {
|
enet1: ethernet@25000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <1>;
|
cell-index = <1>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "TSEC";
|
model = "TSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x25000 0x1000>;
|
reg = <0x25000 0x1000>;
|
||||||
|
ranges = <0x0 0x25000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <35 2 36 2 40 2>;
|
interrupts = <35 2 36 2 40 2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
phy-handle = <&phy1>;
|
phy-handle = <&phy1>;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-tbi";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
tbi1: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
enet2: ethernet@26000 {
|
enet2: ethernet@26000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <2>;
|
cell-index = <2>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "FEC";
|
model = "FEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x26000 0x1000>;
|
reg = <0x26000 0x1000>;
|
||||||
|
ranges = <0x0 0x26000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <41 2>;
|
interrupts = <41 2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
phy-handle = <&phy3>;
|
phy-handle = <&phy3>;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-tbi";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
tbi2: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
serial0: serial@4500 {
|
serial0: serial@4500 {
|
||||||
|
|
|
||||||
|
|
@ -83,6 +83,11 @@
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
dfsrr;
|
dfsrr;
|
||||||
|
|
||||||
|
dtt@50 {
|
||||||
|
compatible = "national,lm75";
|
||||||
|
reg = <0x50>;
|
||||||
|
};
|
||||||
|
|
||||||
rtc@68 {
|
rtc@68 {
|
||||||
compatible = "dallas,ds1337";
|
compatible = "dallas,ds1337";
|
||||||
reg = <0x68>;
|
reg = <0x68>;
|
||||||
|
|
@ -130,72 +135,78 @@
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
mdio@24520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-mdio";
|
|
||||||
reg = <0x24520 0x20>;
|
|
||||||
|
|
||||||
phy1: ethernet-phy@1 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <8 1>;
|
|
||||||
reg = <1>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
phy2: ethernet-phy@2 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <8 1>;
|
|
||||||
reg = <2>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
phy3: ethernet-phy@3 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <8 1>;
|
|
||||||
reg = <3>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
tbi0: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
mdio@25520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-tbi";
|
|
||||||
reg = <0x25520 0x20>;
|
|
||||||
|
|
||||||
tbi1: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
enet0: ethernet@24000 {
|
enet0: ethernet@24000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <0>;
|
cell-index = <0>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "TSEC";
|
model = "TSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x24000 0x1000>;
|
reg = <0x24000 0x1000>;
|
||||||
|
ranges = <0x0 0x24000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <29 2 30 2 34 2>;
|
interrupts = <29 2 30 2 34 2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
tbi-handle = <&tbi0>;
|
tbi-handle = <&tbi0>;
|
||||||
phy-handle = <&phy2>;
|
phy-handle = <&phy2>;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-mdio";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
phy1: ethernet-phy@1 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <8 1>;
|
||||||
|
reg = <1>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
phy2: ethernet-phy@2 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <8 1>;
|
||||||
|
reg = <2>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
phy3: ethernet-phy@3 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <8 1>;
|
||||||
|
reg = <3>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
tbi0: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
enet1: ethernet@25000 {
|
enet1: ethernet@25000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <1>;
|
cell-index = <1>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "TSEC";
|
model = "TSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x25000 0x1000>;
|
reg = <0x25000 0x1000>;
|
||||||
|
ranges = <0x0 0x25000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <35 2 36 2 40 2>;
|
interrupts = <35 2 36 2 40 2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
tbi-handle = <&tbi1>;
|
tbi-handle = <&tbi1>;
|
||||||
phy-handle = <&phy1>;
|
phy-handle = <&phy1>;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-tbi";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
tbi1: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
serial0: serial@4500 {
|
serial0: serial@4500 {
|
||||||
|
|
|
||||||
|
|
@ -85,6 +85,11 @@
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
dfsrr;
|
dfsrr;
|
||||||
|
|
||||||
|
dtt@50 {
|
||||||
|
compatible = "national,lm75";
|
||||||
|
reg = <0x50>;
|
||||||
|
};
|
||||||
|
|
||||||
rtc@68 {
|
rtc@68 {
|
||||||
compatible = "dallas,ds1337";
|
compatible = "dallas,ds1337";
|
||||||
reg = <0x68>;
|
reg = <0x68>;
|
||||||
|
|
@ -143,134 +148,146 @@
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
mdio@24520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-mdio";
|
|
||||||
reg = <0x24520 0x20>;
|
|
||||||
|
|
||||||
phy1: ethernet-phy@0 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <8 1>;
|
|
||||||
reg = <1>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
phy2: ethernet-phy@1 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <8 1>;
|
|
||||||
reg = <2>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
phy3: ethernet-phy@3 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <8 1>;
|
|
||||||
reg = <3>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
phy4: ethernet-phy@4 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <8 1>;
|
|
||||||
reg = <4>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
phy5: ethernet-phy@5 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <8 1>;
|
|
||||||
reg = <5>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
tbi0: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
mdio@25520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-tbi";
|
|
||||||
reg = <0x25520 0x20>;
|
|
||||||
|
|
||||||
tbi1: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
mdio@26520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-tbi";
|
|
||||||
reg = <0x26520 0x20>;
|
|
||||||
|
|
||||||
tbi2: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
mdio@27520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-tbi";
|
|
||||||
reg = <0x27520 0x20>;
|
|
||||||
|
|
||||||
tbi3: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
enet0: ethernet@24000 {
|
enet0: ethernet@24000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <0>;
|
cell-index = <0>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "eTSEC";
|
model = "eTSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x24000 0x1000>;
|
reg = <0x24000 0x1000>;
|
||||||
|
ranges = <0x0 0x24000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <29 2 30 2 34 2>;
|
interrupts = <29 2 30 2 34 2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
tbi-handle = <&tbi0>;
|
tbi-handle = <&tbi0>;
|
||||||
phy-handle = <&phy2>;
|
phy-handle = <&phy2>;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-mdio";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
phy1: ethernet-phy@0 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <8 1>;
|
||||||
|
reg = <1>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
phy2: ethernet-phy@1 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <8 1>;
|
||||||
|
reg = <2>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
phy3: ethernet-phy@3 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <8 1>;
|
||||||
|
reg = <3>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
phy4: ethernet-phy@4 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <8 1>;
|
||||||
|
reg = <4>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
phy5: ethernet-phy@5 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <8 1>;
|
||||||
|
reg = <5>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
tbi0: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
enet1: ethernet@25000 {
|
enet1: ethernet@25000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <1>;
|
cell-index = <1>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "eTSEC";
|
model = "eTSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x25000 0x1000>;
|
reg = <0x25000 0x1000>;
|
||||||
|
ranges = <0x0 0x25000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <35 2 36 2 40 2>;
|
interrupts = <35 2 36 2 40 2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
tbi-handle = <&tbi1>;
|
tbi-handle = <&tbi1>;
|
||||||
phy-handle = <&phy1>;
|
phy-handle = <&phy1>;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-tbi";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
tbi1: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
enet2: ethernet@26000 {
|
enet2: ethernet@26000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <2>;
|
cell-index = <2>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "eTSEC";
|
model = "eTSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x26000 0x1000>;
|
reg = <0x26000 0x1000>;
|
||||||
|
ranges = <0x0 0x26000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <31 2 32 2 33 2>;
|
interrupts = <31 2 32 2 33 2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
tbi-handle = <&tbi2>;
|
tbi-handle = <&tbi2>;
|
||||||
phy-handle = <&phy3>;
|
phy-handle = <&phy3>;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-tbi";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
tbi2: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
enet3: ethernet@27000 {
|
enet3: ethernet@27000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <3>;
|
cell-index = <3>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "eTSEC";
|
model = "eTSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x27000 0x1000>;
|
reg = <0x27000 0x1000>;
|
||||||
|
ranges = <0x0 0x27000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <37 2 38 2 39 2>;
|
interrupts = <37 2 38 2 39 2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
tbi-handle = <&tbi3>;
|
tbi-handle = <&tbi3>;
|
||||||
phy-handle = <&phy4>;
|
phy-handle = <&phy4>;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-tbi";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
tbi3: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
serial0: serial@4500 {
|
serial0: serial@4500 {
|
||||||
|
|
@ -365,14 +382,14 @@
|
||||||
can0@2,0 {
|
can0@2,0 {
|
||||||
compatible = "intel,82527"; // Bosch CC770
|
compatible = "intel,82527"; // Bosch CC770
|
||||||
reg = <2 0x0 0x100>;
|
reg = <2 0x0 0x100>;
|
||||||
interrupts = <4 0>;
|
interrupts = <4 1>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
};
|
};
|
||||||
|
|
||||||
can1@2,100 {
|
can1@2,100 {
|
||||||
compatible = "intel,82527"; // Bosch CC770
|
compatible = "intel,82527"; // Bosch CC770
|
||||||
reg = <2 0x100 0x100>;
|
reg = <2 0x100 0x100>;
|
||||||
interrupts = <4 0>;
|
interrupts = <4 1>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -85,6 +85,11 @@
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
dfsrr;
|
dfsrr;
|
||||||
|
|
||||||
|
dtt@50 {
|
||||||
|
compatible = "national,lm75";
|
||||||
|
reg = <0x50>;
|
||||||
|
};
|
||||||
|
|
||||||
rtc@68 {
|
rtc@68 {
|
||||||
compatible = "dallas,ds1337";
|
compatible = "dallas,ds1337";
|
||||||
reg = <0x68>;
|
reg = <0x68>;
|
||||||
|
|
@ -143,134 +148,146 @@
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
mdio@24520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-mdio";
|
|
||||||
reg = <0x24520 0x20>;
|
|
||||||
|
|
||||||
phy1: ethernet-phy@0 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <8 1>;
|
|
||||||
reg = <1>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
phy2: ethernet-phy@1 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <8 1>;
|
|
||||||
reg = <2>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
phy3: ethernet-phy@3 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <8 1>;
|
|
||||||
reg = <3>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
phy4: ethernet-phy@4 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <8 1>;
|
|
||||||
reg = <4>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
phy5: ethernet-phy@5 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <8 1>;
|
|
||||||
reg = <5>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
tbi0: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
mdio@25520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-tbi";
|
|
||||||
reg = <0x25520 0x20>;
|
|
||||||
|
|
||||||
tbi1: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
mdio@26520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-tbi";
|
|
||||||
reg = <0x26520 0x20>;
|
|
||||||
|
|
||||||
tbi2: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
mdio@27520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-tbi";
|
|
||||||
reg = <0x27520 0x20>;
|
|
||||||
|
|
||||||
tbi3: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
enet0: ethernet@24000 {
|
enet0: ethernet@24000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <0>;
|
cell-index = <0>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "eTSEC";
|
model = "eTSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x24000 0x1000>;
|
reg = <0x24000 0x1000>;
|
||||||
|
ranges = <0x0 0x24000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <29 2 30 2 34 2>;
|
interrupts = <29 2 30 2 34 2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
tbi-handle = <&tbi0>;
|
tbi-handle = <&tbi0>;
|
||||||
phy-handle = <&phy2>;
|
phy-handle = <&phy2>;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-mdio";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
phy1: ethernet-phy@0 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <8 1>;
|
||||||
|
reg = <1>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
phy2: ethernet-phy@1 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <8 1>;
|
||||||
|
reg = <2>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
phy3: ethernet-phy@3 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <8 1>;
|
||||||
|
reg = <3>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
phy4: ethernet-phy@4 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <8 1>;
|
||||||
|
reg = <4>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
phy5: ethernet-phy@5 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <8 1>;
|
||||||
|
reg = <5>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
tbi0: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
enet1: ethernet@25000 {
|
enet1: ethernet@25000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <1>;
|
cell-index = <1>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "eTSEC";
|
model = "eTSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x25000 0x1000>;
|
reg = <0x25000 0x1000>;
|
||||||
|
ranges = <0x0 0x25000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <35 2 36 2 40 2>;
|
interrupts = <35 2 36 2 40 2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
tbi-handle = <&tbi1>;
|
tbi-handle = <&tbi1>;
|
||||||
phy-handle = <&phy1>;
|
phy-handle = <&phy1>;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-tbi";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
tbi1: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
enet2: ethernet@26000 {
|
enet2: ethernet@26000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <2>;
|
cell-index = <2>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "eTSEC";
|
model = "eTSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x26000 0x1000>;
|
reg = <0x26000 0x1000>;
|
||||||
|
ranges = <0x0 0x26000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <31 2 32 2 33 2>;
|
interrupts = <31 2 32 2 33 2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
tbi-handle = <&tbi2>;
|
tbi-handle = <&tbi2>;
|
||||||
phy-handle = <&phy3>;
|
phy-handle = <&phy3>;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-tbi";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
tbi2: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
enet3: ethernet@27000 {
|
enet3: ethernet@27000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <3>;
|
cell-index = <3>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "eTSEC";
|
model = "eTSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x27000 0x1000>;
|
reg = <0x27000 0x1000>;
|
||||||
|
ranges = <0x0 0x27000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <37 2 38 2 39 2>;
|
interrupts = <37 2 38 2 39 2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
tbi-handle = <&tbi3>;
|
tbi-handle = <&tbi3>;
|
||||||
phy-handle = <&phy4>;
|
phy-handle = <&phy4>;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-tbi";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
tbi3: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
serial0: serial@4500 {
|
serial0: serial@4500 {
|
||||||
|
|
@ -365,14 +382,14 @@
|
||||||
can0@2,0 {
|
can0@2,0 {
|
||||||
compatible = "intel,82527"; // Bosch CC770
|
compatible = "intel,82527"; // Bosch CC770
|
||||||
reg = <2 0x0 0x100>;
|
reg = <2 0x0 0x100>;
|
||||||
interrupts = <4 0>;
|
interrupts = <4 1>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
};
|
};
|
||||||
|
|
||||||
can1@2,100 {
|
can1@2,100 {
|
||||||
compatible = "intel,82527"; // Bosch CC770
|
compatible = "intel,82527"; // Bosch CC770
|
||||||
reg = <2 0x100 0x100>;
|
reg = <2 0x100 0x100>;
|
||||||
interrupts = <4 0>;
|
interrupts = <4 1>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -83,6 +83,11 @@
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
dfsrr;
|
dfsrr;
|
||||||
|
|
||||||
|
dtt@50 {
|
||||||
|
compatible = "national,lm75";
|
||||||
|
reg = <0x50>;
|
||||||
|
};
|
||||||
|
|
||||||
rtc@68 {
|
rtc@68 {
|
||||||
compatible = "dallas,ds1337";
|
compatible = "dallas,ds1337";
|
||||||
reg = <0x68>;
|
reg = <0x68>;
|
||||||
|
|
@ -130,72 +135,78 @@
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
mdio@24520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-mdio";
|
|
||||||
reg = <0x24520 0x20>;
|
|
||||||
|
|
||||||
phy1: ethernet-phy@1 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <8 1>;
|
|
||||||
reg = <1>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
phy2: ethernet-phy@2 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <8 1>;
|
|
||||||
reg = <2>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
phy3: ethernet-phy@3 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <8 1>;
|
|
||||||
reg = <3>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
tbi0: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
mdio@25520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-tbi";
|
|
||||||
reg = <0x25520 0x20>;
|
|
||||||
|
|
||||||
tbi1: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
enet0: ethernet@24000 {
|
enet0: ethernet@24000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <0>;
|
cell-index = <0>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "TSEC";
|
model = "TSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x24000 0x1000>;
|
reg = <0x24000 0x1000>;
|
||||||
|
ranges = <0x0 0x24000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <29 2 30 2 34 2>;
|
interrupts = <29 2 30 2 34 2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
tbi-handle = <&tbi0>;
|
tbi-handle = <&tbi0>;
|
||||||
phy-handle = <&phy2>;
|
phy-handle = <&phy2>;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-mdio";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
phy1: ethernet-phy@1 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <8 1>;
|
||||||
|
reg = <1>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
phy2: ethernet-phy@2 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <8 1>;
|
||||||
|
reg = <2>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
phy3: ethernet-phy@3 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <8 1>;
|
||||||
|
reg = <3>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
tbi0: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
enet1: ethernet@25000 {
|
enet1: ethernet@25000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <1>;
|
cell-index = <1>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "TSEC";
|
model = "TSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x25000 0x1000>;
|
reg = <0x25000 0x1000>;
|
||||||
|
ranges = <0x0 0x25000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <35 2 36 2 40 2>;
|
interrupts = <35 2 36 2 40 2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
tbi-handle = <&tbi1>;
|
tbi-handle = <&tbi1>;
|
||||||
phy-handle = <&phy1>;
|
phy-handle = <&phy1>;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-tbi";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
tbi1: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
serial0: serial@4500 {
|
serial0: serial@4500 {
|
||||||
|
|
|
||||||
|
|
@ -85,6 +85,11 @@
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
dfsrr;
|
dfsrr;
|
||||||
|
|
||||||
|
dtt@50 {
|
||||||
|
compatible = "national,lm75";
|
||||||
|
reg = <0x50>;
|
||||||
|
};
|
||||||
|
|
||||||
rtc@68 {
|
rtc@68 {
|
||||||
compatible = "dallas,ds1337";
|
compatible = "dallas,ds1337";
|
||||||
reg = <0x68>;
|
reg = <0x68>;
|
||||||
|
|
@ -132,72 +137,78 @@
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
mdio@24520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-mdio";
|
|
||||||
reg = <0x24520 0x20>;
|
|
||||||
|
|
||||||
phy1: ethernet-phy@1 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <8 1>;
|
|
||||||
reg = <1>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
phy2: ethernet-phy@2 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <8 1>;
|
|
||||||
reg = <2>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
phy3: ethernet-phy@3 {
|
|
||||||
interrupt-parent = <&mpic>;
|
|
||||||
interrupts = <8 1>;
|
|
||||||
reg = <3>;
|
|
||||||
device_type = "ethernet-phy";
|
|
||||||
};
|
|
||||||
tbi0: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
mdio@25520 {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "fsl,gianfar-tbi";
|
|
||||||
reg = <0x25520 0x20>;
|
|
||||||
|
|
||||||
tbi1: tbi-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
device_type = "tbi-phy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
enet0: ethernet@24000 {
|
enet0: ethernet@24000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <0>;
|
cell-index = <0>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "TSEC";
|
model = "TSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x24000 0x1000>;
|
reg = <0x24000 0x1000>;
|
||||||
|
ranges = <0x0 0x24000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <29 2 30 2 34 2>;
|
interrupts = <29 2 30 2 34 2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
tbi-handle = <&tbi0>;
|
tbi-handle = <&tbi0>;
|
||||||
phy-handle = <&phy2>;
|
phy-handle = <&phy2>;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-mdio";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
phy1: ethernet-phy@1 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <8 1>;
|
||||||
|
reg = <1>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
phy2: ethernet-phy@2 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <8 1>;
|
||||||
|
reg = <2>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
phy3: ethernet-phy@3 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <8 1>;
|
||||||
|
reg = <3>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
tbi0: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
enet1: ethernet@25000 {
|
enet1: ethernet@25000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
cell-index = <1>;
|
cell-index = <1>;
|
||||||
device_type = "network";
|
device_type = "network";
|
||||||
model = "TSEC";
|
model = "TSEC";
|
||||||
compatible = "gianfar";
|
compatible = "gianfar";
|
||||||
reg = <0x25000 0x1000>;
|
reg = <0x25000 0x1000>;
|
||||||
|
ranges = <0x0 0x25000 0x1000>;
|
||||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
interrupts = <35 2 36 2 40 2>;
|
interrupts = <35 2 36 2 40 2>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
tbi-handle = <&tbi1>;
|
tbi-handle = <&tbi1>;
|
||||||
phy-handle = <&phy1>;
|
phy-handle = <&phy1>;
|
||||||
|
|
||||||
|
mdio@520 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "fsl,gianfar-tbi";
|
||||||
|
reg = <0x520 0x20>;
|
||||||
|
|
||||||
|
tbi1: tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
mpic: pic@40000 {
|
mpic: pic@40000 {
|
||||||
|
|
@ -335,14 +346,14 @@
|
||||||
can0@2,0 {
|
can0@2,0 {
|
||||||
compatible = "intel,82527"; // Bosch CC770
|
compatible = "intel,82527"; // Bosch CC770
|
||||||
reg = <2 0x0 0x100>;
|
reg = <2 0x0 0x100>;
|
||||||
interrupts = <4 0>;
|
interrupts = <4 1>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
};
|
};
|
||||||
|
|
||||||
can1@2,100 {
|
can1@2,100 {
|
||||||
compatible = "intel,82527"; // Bosch CC770
|
compatible = "intel,82527"; // Bosch CC770
|
||||||
reg = <2 0x100 0x100>;
|
reg = <2 0x100 0x100>;
|
||||||
interrupts = <4 0>;
|
interrupts = <4 1>;
|
||||||
interrupt-parent = <&mpic>;
|
interrupt-parent = <&mpic>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
|
||||||
|
|
@ -7,6 +7,15 @@
|
||||||
* This file is licensed under the terms of the GNU General Public License
|
* This file is licensed under the terms of the GNU General Public License
|
||||||
* version 2. This program is licensed "as is" without any warranty of any
|
* version 2. This program is licensed "as is" without any warranty of any
|
||||||
* kind, whether express or implied.
|
* kind, whether express or implied.
|
||||||
|
*
|
||||||
|
* ---
|
||||||
|
*
|
||||||
|
* Device Tree Generator version: 1.1
|
||||||
|
*
|
||||||
|
* CAUTION: This file is automatically generated by libgen.
|
||||||
|
* Version: Xilinx EDK 10.1.03 EDK_K_SP3.6
|
||||||
|
*
|
||||||
|
* XPS project directory: ml507_ppc440_emb_ref
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/dts-v1/;
|
/dts-v1/;
|
||||||
|
|
@ -22,8 +31,8 @@
|
||||||
reg = < 0 0x10000000 >;
|
reg = < 0 0x10000000 >;
|
||||||
} ;
|
} ;
|
||||||
chosen {
|
chosen {
|
||||||
bootargs = "console=ttyS0 ip=on root=/dev/ram";
|
bootargs = "console=ttyS0 root=/dev/ram";
|
||||||
linux,stdout-path = "/plb@0/serial@83e00000";
|
linux,stdout-path = &RS232_Uart_1;
|
||||||
} ;
|
} ;
|
||||||
cpus {
|
cpus {
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
|
|
@ -136,19 +145,19 @@
|
||||||
compatible = "xlnx,ll-dma-1.00.a";
|
compatible = "xlnx,ll-dma-1.00.a";
|
||||||
dcr-reg = < 0x80 0x11 >;
|
dcr-reg = < 0x80 0x11 >;
|
||||||
interrupt-parent = <&xps_intc_0>;
|
interrupt-parent = <&xps_intc_0>;
|
||||||
interrupts = < 9 2 0xa 2 >;
|
interrupts = < 10 2 11 2 >;
|
||||||
} ;
|
} ;
|
||||||
} ;
|
} ;
|
||||||
} ;
|
} ;
|
||||||
plb_v46_0: plb@0 {
|
plb_v46_0: plb@0 {
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <1>;
|
#size-cells = <1>;
|
||||||
compatible = "xlnx,plb-v46-1.02.a", "simple-bus";
|
compatible = "xlnx,plb-v46-1.03.a", "simple-bus";
|
||||||
ranges ;
|
ranges ;
|
||||||
DIP_Switches_8Bit: gpio@81460000 {
|
DIP_Switches_8Bit: gpio@81460000 {
|
||||||
compatible = "xlnx,xps-gpio-1.00.a";
|
compatible = "xlnx,xps-gpio-1.00.a";
|
||||||
interrupt-parent = <&xps_intc_0>;
|
interrupt-parent = <&xps_intc_0>;
|
||||||
interrupts = < 6 2 >;
|
interrupts = < 7 2 >;
|
||||||
reg = < 0x81460000 0x10000 >;
|
reg = < 0x81460000 0x10000 >;
|
||||||
xlnx,all-inputs = <1>;
|
xlnx,all-inputs = <1>;
|
||||||
xlnx,all-inputs-2 = <0>;
|
xlnx,all-inputs-2 = <0>;
|
||||||
|
|
@ -163,6 +172,86 @@
|
||||||
xlnx,tri-default = <0xffffffff>;
|
xlnx,tri-default = <0xffffffff>;
|
||||||
xlnx,tri-default-2 = <0xffffffff>;
|
xlnx,tri-default-2 = <0xffffffff>;
|
||||||
} ;
|
} ;
|
||||||
|
FLASH: flash@fc000000 {
|
||||||
|
bank-width = <2>;
|
||||||
|
compatible = "xlnx,xps-mch-emc-2.00.a", "cfi-flash";
|
||||||
|
reg = < 0xfc000000 0x2000000 >;
|
||||||
|
xlnx,family = "virtex5";
|
||||||
|
xlnx,include-datawidth-matching-0 = <0x1>;
|
||||||
|
xlnx,include-datawidth-matching-1 = <0x0>;
|
||||||
|
xlnx,include-datawidth-matching-2 = <0x0>;
|
||||||
|
xlnx,include-datawidth-matching-3 = <0x0>;
|
||||||
|
xlnx,include-negedge-ioregs = <0x0>;
|
||||||
|
xlnx,include-plb-ipif = <0x1>;
|
||||||
|
xlnx,include-wrbuf = <0x1>;
|
||||||
|
xlnx,max-mem-width = <0x10>;
|
||||||
|
xlnx,mch-native-dwidth = <0x20>;
|
||||||
|
xlnx,mch-plb-clk-period-ps = <0x2710>;
|
||||||
|
xlnx,mch-splb-awidth = <0x20>;
|
||||||
|
xlnx,mch0-accessbuf-depth = <0x10>;
|
||||||
|
xlnx,mch0-protocol = <0x0>;
|
||||||
|
xlnx,mch0-rddatabuf-depth = <0x10>;
|
||||||
|
xlnx,mch1-accessbuf-depth = <0x10>;
|
||||||
|
xlnx,mch1-protocol = <0x0>;
|
||||||
|
xlnx,mch1-rddatabuf-depth = <0x10>;
|
||||||
|
xlnx,mch2-accessbuf-depth = <0x10>;
|
||||||
|
xlnx,mch2-protocol = <0x0>;
|
||||||
|
xlnx,mch2-rddatabuf-depth = <0x10>;
|
||||||
|
xlnx,mch3-accessbuf-depth = <0x10>;
|
||||||
|
xlnx,mch3-protocol = <0x0>;
|
||||||
|
xlnx,mch3-rddatabuf-depth = <0x10>;
|
||||||
|
xlnx,mem0-width = <0x10>;
|
||||||
|
xlnx,mem1-width = <0x20>;
|
||||||
|
xlnx,mem2-width = <0x20>;
|
||||||
|
xlnx,mem3-width = <0x20>;
|
||||||
|
xlnx,num-banks-mem = <0x1>;
|
||||||
|
xlnx,num-channels = <0x2>;
|
||||||
|
xlnx,priority-mode = <0x0>;
|
||||||
|
xlnx,synch-mem-0 = <0x0>;
|
||||||
|
xlnx,synch-mem-1 = <0x0>;
|
||||||
|
xlnx,synch-mem-2 = <0x0>;
|
||||||
|
xlnx,synch-mem-3 = <0x0>;
|
||||||
|
xlnx,synch-pipedelay-0 = <0x2>;
|
||||||
|
xlnx,synch-pipedelay-1 = <0x2>;
|
||||||
|
xlnx,synch-pipedelay-2 = <0x2>;
|
||||||
|
xlnx,synch-pipedelay-3 = <0x2>;
|
||||||
|
xlnx,tavdv-ps-mem-0 = <0x1adb0>;
|
||||||
|
xlnx,tavdv-ps-mem-1 = <0x3a98>;
|
||||||
|
xlnx,tavdv-ps-mem-2 = <0x3a98>;
|
||||||
|
xlnx,tavdv-ps-mem-3 = <0x3a98>;
|
||||||
|
xlnx,tcedv-ps-mem-0 = <0x1adb0>;
|
||||||
|
xlnx,tcedv-ps-mem-1 = <0x3a98>;
|
||||||
|
xlnx,tcedv-ps-mem-2 = <0x3a98>;
|
||||||
|
xlnx,tcedv-ps-mem-3 = <0x3a98>;
|
||||||
|
xlnx,thzce-ps-mem-0 = <0x88b8>;
|
||||||
|
xlnx,thzce-ps-mem-1 = <0x1b58>;
|
||||||
|
xlnx,thzce-ps-mem-2 = <0x1b58>;
|
||||||
|
xlnx,thzce-ps-mem-3 = <0x1b58>;
|
||||||
|
xlnx,thzoe-ps-mem-0 = <0x1b58>;
|
||||||
|
xlnx,thzoe-ps-mem-1 = <0x1b58>;
|
||||||
|
xlnx,thzoe-ps-mem-2 = <0x1b58>;
|
||||||
|
xlnx,thzoe-ps-mem-3 = <0x1b58>;
|
||||||
|
xlnx,tlzwe-ps-mem-0 = <0x88b8>;
|
||||||
|
xlnx,tlzwe-ps-mem-1 = <0x0>;
|
||||||
|
xlnx,tlzwe-ps-mem-2 = <0x0>;
|
||||||
|
xlnx,tlzwe-ps-mem-3 = <0x0>;
|
||||||
|
xlnx,twc-ps-mem-0 = <0x2af8>;
|
||||||
|
xlnx,twc-ps-mem-1 = <0x3a98>;
|
||||||
|
xlnx,twc-ps-mem-2 = <0x3a98>;
|
||||||
|
xlnx,twc-ps-mem-3 = <0x3a98>;
|
||||||
|
xlnx,twp-ps-mem-0 = <0x11170>;
|
||||||
|
xlnx,twp-ps-mem-1 = <0x2ee0>;
|
||||||
|
xlnx,twp-ps-mem-2 = <0x2ee0>;
|
||||||
|
xlnx,twp-ps-mem-3 = <0x2ee0>;
|
||||||
|
xlnx,xcl0-linesize = <0x4>;
|
||||||
|
xlnx,xcl0-writexfer = <0x1>;
|
||||||
|
xlnx,xcl1-linesize = <0x4>;
|
||||||
|
xlnx,xcl1-writexfer = <0x1>;
|
||||||
|
xlnx,xcl2-linesize = <0x4>;
|
||||||
|
xlnx,xcl2-writexfer = <0x1>;
|
||||||
|
xlnx,xcl3-linesize = <0x4>;
|
||||||
|
xlnx,xcl3-writexfer = <0x1>;
|
||||||
|
} ;
|
||||||
Hard_Ethernet_MAC: xps-ll-temac@81c00000 {
|
Hard_Ethernet_MAC: xps-ll-temac@81c00000 {
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <1>;
|
#size-cells = <1>;
|
||||||
|
|
@ -185,6 +274,19 @@
|
||||||
xlnx,txfifo = <0x1000>;
|
xlnx,txfifo = <0x1000>;
|
||||||
} ;
|
} ;
|
||||||
} ;
|
} ;
|
||||||
|
IIC_EEPROM: i2c@81600000 {
|
||||||
|
compatible = "xlnx,xps-iic-2.00.a";
|
||||||
|
interrupt-parent = <&xps_intc_0>;
|
||||||
|
interrupts = < 6 2 >;
|
||||||
|
reg = < 0x81600000 0x10000 >;
|
||||||
|
xlnx,clk-freq = <0x5f5e100>;
|
||||||
|
xlnx,family = "virtex5";
|
||||||
|
xlnx,gpo-width = <0x1>;
|
||||||
|
xlnx,iic-freq = <0x186a0>;
|
||||||
|
xlnx,scl-inertial-delay = <0x0>;
|
||||||
|
xlnx,sda-inertial-delay = <0x0>;
|
||||||
|
xlnx,ten-bit-adr = <0x0>;
|
||||||
|
} ;
|
||||||
LEDs_8Bit: gpio@81400000 {
|
LEDs_8Bit: gpio@81400000 {
|
||||||
compatible = "xlnx,xps-gpio-1.00.a";
|
compatible = "xlnx,xps-gpio-1.00.a";
|
||||||
reg = < 0x81400000 0x10000 >;
|
reg = < 0x81400000 0x10000 >;
|
||||||
|
|
@ -220,7 +322,7 @@
|
||||||
Push_Buttons_5Bit: gpio@81440000 {
|
Push_Buttons_5Bit: gpio@81440000 {
|
||||||
compatible = "xlnx,xps-gpio-1.00.a";
|
compatible = "xlnx,xps-gpio-1.00.a";
|
||||||
interrupt-parent = <&xps_intc_0>;
|
interrupt-parent = <&xps_intc_0>;
|
||||||
interrupts = < 7 2 >;
|
interrupts = < 8 2 >;
|
||||||
reg = < 0x81440000 0x10000 >;
|
reg = < 0x81440000 0x10000 >;
|
||||||
xlnx,all-inputs = <1>;
|
xlnx,all-inputs = <1>;
|
||||||
xlnx,all-inputs-2 = <0>;
|
xlnx,all-inputs-2 = <0>;
|
||||||
|
|
@ -237,13 +339,13 @@
|
||||||
} ;
|
} ;
|
||||||
RS232_Uart_1: serial@83e00000 {
|
RS232_Uart_1: serial@83e00000 {
|
||||||
clock-frequency = <100000000>;
|
clock-frequency = <100000000>;
|
||||||
compatible = "xlnx,xps-uart16550-2.00.a", "ns16550";
|
compatible = "xlnx,xps-uart16550-2.00.b", "ns16550";
|
||||||
current-speed = <0x2580>;
|
current-speed = <9600>;
|
||||||
device_type = "serial";
|
device_type = "serial";
|
||||||
interrupt-parent = <&xps_intc_0>;
|
interrupt-parent = <&xps_intc_0>;
|
||||||
interrupts = < 8 2 >;
|
interrupts = < 9 2 >;
|
||||||
reg = < 0x83e00000 0x10000 >;
|
reg = < 0x83e00000 0x10000 >;
|
||||||
reg-offset = <3>;
|
reg-offset = <0x1003>;
|
||||||
reg-shift = <2>;
|
reg-shift = <2>;
|
||||||
xlnx,family = "virtex5";
|
xlnx,family = "virtex5";
|
||||||
xlnx,has-external-rclk = <0>;
|
xlnx,has-external-rclk = <0>;
|
||||||
|
|
@ -268,7 +370,7 @@
|
||||||
compatible = "xlnx,xps-intc-1.00.a";
|
compatible = "xlnx,xps-intc-1.00.a";
|
||||||
interrupt-controller ;
|
interrupt-controller ;
|
||||||
reg = < 0x81800000 0x10000 >;
|
reg = < 0x81800000 0x10000 >;
|
||||||
xlnx,num-intr-inputs = <0xb>;
|
xlnx,num-intr-inputs = <0xc>;
|
||||||
} ;
|
} ;
|
||||||
xps_timebase_wdt_1: xps-timebase-wdt@83a00000 {
|
xps_timebase_wdt_1: xps-timebase-wdt@83a00000 {
|
||||||
compatible = "xlnx,xps-timebase-wdt-1.00.b";
|
compatible = "xlnx,xps-timebase-wdt-1.00.b";
|
||||||
|
|
|
||||||
|
|
@ -117,7 +117,8 @@ int serial_console_init(void)
|
||||||
if (devp == NULL)
|
if (devp == NULL)
|
||||||
goto err_out;
|
goto err_out;
|
||||||
|
|
||||||
if (dt_is_compatible(devp, "ns16550"))
|
if (dt_is_compatible(devp, "ns16550") ||
|
||||||
|
dt_is_compatible(devp, "pnpPNP,501"))
|
||||||
rc = ns16550_console_init(devp, &serial_cd);
|
rc = ns16550_console_init(devp, &serial_cd);
|
||||||
else if (dt_is_compatible(devp, "marvell,mv64360-mpsc"))
|
else if (dt_is_compatible(devp, "marvell,mv64360-mpsc"))
|
||||||
rc = mpsc_console_init(devp, &serial_cd);
|
rc = mpsc_console_init(devp, &serial_cd);
|
||||||
|
|
|
||||||
|
|
@ -186,6 +186,9 @@ cuboot*)
|
||||||
*-mpc85*|*-tqm85*|*-sbc85*)
|
*-mpc85*|*-tqm85*|*-sbc85*)
|
||||||
platformo=$object/cuboot-85xx.o
|
platformo=$object/cuboot-85xx.o
|
||||||
;;
|
;;
|
||||||
|
*-amigaone)
|
||||||
|
link_address='0x800000'
|
||||||
|
;;
|
||||||
esac
|
esac
|
||||||
;;
|
;;
|
||||||
ps3)
|
ps3)
|
||||||
|
|
@ -211,11 +214,11 @@ simpleboot-virtex405-*)
|
||||||
binary=y
|
binary=y
|
||||||
;;
|
;;
|
||||||
simpleboot-virtex440-*)
|
simpleboot-virtex440-*)
|
||||||
platformo="$object/simpleboot.o $object/virtex.o"
|
platformo="$object/fixed-head.o $object/simpleboot.o $object/virtex.o"
|
||||||
binary=y
|
binary=y
|
||||||
;;
|
;;
|
||||||
simpleboot-*)
|
simpleboot-*)
|
||||||
platformo="$object/simpleboot.o"
|
platformo="$object/fixed-head.o $object/simpleboot.o"
|
||||||
binary=y
|
binary=y
|
||||||
;;
|
;;
|
||||||
asp834x-redboot)
|
asp834x-redboot)
|
||||||
|
|
|
||||||
|
|
@ -1,7 +1,7 @@
|
||||||
#
|
#
|
||||||
# Automatically generated make config: don't edit
|
# Automatically generated make config: don't edit
|
||||||
# Linux kernel version: 2.6.29-rc2
|
# Linux kernel version: 2.6.29-rc3
|
||||||
# Tue Jan 20 08:22:35 2009
|
# Mon Feb 2 13:13:04 2009
|
||||||
#
|
#
|
||||||
# CONFIG_PPC64 is not set
|
# CONFIG_PPC64 is not set
|
||||||
|
|
||||||
|
|
@ -74,6 +74,15 @@ CONFIG_POSIX_MQUEUE=y
|
||||||
# CONFIG_BSD_PROCESS_ACCT is not set
|
# CONFIG_BSD_PROCESS_ACCT is not set
|
||||||
# CONFIG_TASKSTATS is not set
|
# CONFIG_TASKSTATS is not set
|
||||||
# CONFIG_AUDIT is not set
|
# CONFIG_AUDIT is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# RCU Subsystem
|
||||||
|
#
|
||||||
|
CONFIG_CLASSIC_RCU=y
|
||||||
|
# CONFIG_TREE_RCU is not set
|
||||||
|
# CONFIG_PREEMPT_RCU is not set
|
||||||
|
# CONFIG_TREE_RCU_TRACE is not set
|
||||||
|
# CONFIG_PREEMPT_RCU_TRACE is not set
|
||||||
# CONFIG_IKCONFIG is not set
|
# CONFIG_IKCONFIG is not set
|
||||||
CONFIG_LOG_BUF_SHIFT=14
|
CONFIG_LOG_BUF_SHIFT=14
|
||||||
# CONFIG_GROUP_SCHED is not set
|
# CONFIG_GROUP_SCHED is not set
|
||||||
|
|
@ -147,11 +156,6 @@ CONFIG_DEFAULT_AS=y
|
||||||
# CONFIG_DEFAULT_CFQ is not set
|
# CONFIG_DEFAULT_CFQ is not set
|
||||||
# CONFIG_DEFAULT_NOOP is not set
|
# CONFIG_DEFAULT_NOOP is not set
|
||||||
CONFIG_DEFAULT_IOSCHED="anticipatory"
|
CONFIG_DEFAULT_IOSCHED="anticipatory"
|
||||||
CONFIG_CLASSIC_RCU=y
|
|
||||||
# CONFIG_TREE_RCU is not set
|
|
||||||
# CONFIG_PREEMPT_RCU is not set
|
|
||||||
# CONFIG_TREE_RCU_TRACE is not set
|
|
||||||
# CONFIG_PREEMPT_RCU_TRACE is not set
|
|
||||||
# CONFIG_FREEZER is not set
|
# CONFIG_FREEZER is not set
|
||||||
CONFIG_PPC4xx_PCI_EXPRESS=y
|
CONFIG_PPC4xx_PCI_EXPRESS=y
|
||||||
|
|
||||||
|
|
@ -373,6 +377,7 @@ CONFIG_CONNECTOR=y
|
||||||
CONFIG_PROC_EVENTS=y
|
CONFIG_PROC_EVENTS=y
|
||||||
# CONFIG_MTD is not set
|
# CONFIG_MTD is not set
|
||||||
CONFIG_OF_DEVICE=y
|
CONFIG_OF_DEVICE=y
|
||||||
|
CONFIG_OF_I2C=y
|
||||||
# CONFIG_PARPORT is not set
|
# CONFIG_PARPORT is not set
|
||||||
CONFIG_BLK_DEV=y
|
CONFIG_BLK_DEV=y
|
||||||
# CONFIG_BLK_DEV_FD is not set
|
# CONFIG_BLK_DEV_FD is not set
|
||||||
|
|
@ -384,6 +389,7 @@ CONFIG_BLK_DEV=y
|
||||||
# CONFIG_BLK_DEV_LOOP is not set
|
# CONFIG_BLK_DEV_LOOP is not set
|
||||||
# CONFIG_BLK_DEV_NBD is not set
|
# CONFIG_BLK_DEV_NBD is not set
|
||||||
# CONFIG_BLK_DEV_SX8 is not set
|
# CONFIG_BLK_DEV_SX8 is not set
|
||||||
|
# CONFIG_BLK_DEV_UB is not set
|
||||||
CONFIG_BLK_DEV_RAM=y
|
CONFIG_BLK_DEV_RAM=y
|
||||||
CONFIG_BLK_DEV_RAM_COUNT=16
|
CONFIG_BLK_DEV_RAM_COUNT=16
|
||||||
CONFIG_BLK_DEV_RAM_SIZE=35000
|
CONFIG_BLK_DEV_RAM_SIZE=35000
|
||||||
|
|
@ -466,6 +472,15 @@ CONFIG_IBM_NEW_EMAC_EMAC4=y
|
||||||
#
|
#
|
||||||
# Enable WiMAX (Networking options) to see the WiMAX drivers
|
# Enable WiMAX (Networking options) to see the WiMAX drivers
|
||||||
#
|
#
|
||||||
|
|
||||||
|
#
|
||||||
|
# USB Network Adapters
|
||||||
|
#
|
||||||
|
# CONFIG_USB_CATC is not set
|
||||||
|
# CONFIG_USB_KAWETH is not set
|
||||||
|
# CONFIG_USB_PEGASUS is not set
|
||||||
|
# CONFIG_USB_RTL8150 is not set
|
||||||
|
# CONFIG_USB_USBNET is not set
|
||||||
# CONFIG_WAN is not set
|
# CONFIG_WAN is not set
|
||||||
# CONFIG_FDDI is not set
|
# CONFIG_FDDI is not set
|
||||||
# CONFIG_HIPPI is not set
|
# CONFIG_HIPPI is not set
|
||||||
|
|
@ -533,13 +548,136 @@ CONFIG_LEGACY_PTY_COUNT=256
|
||||||
# CONFIG_RAW_DRIVER is not set
|
# CONFIG_RAW_DRIVER is not set
|
||||||
# CONFIG_TCG_TPM is not set
|
# CONFIG_TCG_TPM is not set
|
||||||
CONFIG_DEVPORT=y
|
CONFIG_DEVPORT=y
|
||||||
# CONFIG_I2C is not set
|
CONFIG_I2C=y
|
||||||
|
CONFIG_I2C_BOARDINFO=y
|
||||||
|
CONFIG_I2C_CHARDEV=y
|
||||||
|
CONFIG_I2C_HELPER_AUTO=y
|
||||||
|
|
||||||
|
#
|
||||||
|
# I2C Hardware Bus support
|
||||||
|
#
|
||||||
|
|
||||||
|
#
|
||||||
|
# PC SMBus host controller drivers
|
||||||
|
#
|
||||||
|
# CONFIG_I2C_ALI1535 is not set
|
||||||
|
# CONFIG_I2C_ALI1563 is not set
|
||||||
|
# CONFIG_I2C_ALI15X3 is not set
|
||||||
|
# CONFIG_I2C_AMD756 is not set
|
||||||
|
# CONFIG_I2C_AMD8111 is not set
|
||||||
|
# CONFIG_I2C_I801 is not set
|
||||||
|
# CONFIG_I2C_ISCH is not set
|
||||||
|
# CONFIG_I2C_PIIX4 is not set
|
||||||
|
# CONFIG_I2C_NFORCE2 is not set
|
||||||
|
# CONFIG_I2C_SIS5595 is not set
|
||||||
|
# CONFIG_I2C_SIS630 is not set
|
||||||
|
# CONFIG_I2C_SIS96X is not set
|
||||||
|
# CONFIG_I2C_VIA is not set
|
||||||
|
# CONFIG_I2C_VIAPRO is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# I2C system bus drivers (mostly embedded / system-on-chip)
|
||||||
|
#
|
||||||
|
CONFIG_I2C_IBM_IIC=y
|
||||||
|
# CONFIG_I2C_MPC is not set
|
||||||
|
# CONFIG_I2C_OCORES is not set
|
||||||
|
# CONFIG_I2C_SIMTEC is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# External I2C/SMBus adapter drivers
|
||||||
|
#
|
||||||
|
# CONFIG_I2C_PARPORT_LIGHT is not set
|
||||||
|
# CONFIG_I2C_TAOS_EVM is not set
|
||||||
|
# CONFIG_I2C_TINY_USB is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# Graphics adapter I2C/DDC channel drivers
|
||||||
|
#
|
||||||
|
# CONFIG_I2C_VOODOO3 is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# Other I2C/SMBus bus drivers
|
||||||
|
#
|
||||||
|
# CONFIG_I2C_PCA_PLATFORM is not set
|
||||||
|
# CONFIG_I2C_STUB is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# Miscellaneous I2C Chip support
|
||||||
|
#
|
||||||
|
# CONFIG_DS1682 is not set
|
||||||
|
# CONFIG_SENSORS_PCF8574 is not set
|
||||||
|
# CONFIG_PCF8575 is not set
|
||||||
|
# CONFIG_SENSORS_PCA9539 is not set
|
||||||
|
# CONFIG_SENSORS_PCF8591 is not set
|
||||||
|
# CONFIG_SENSORS_MAX6875 is not set
|
||||||
|
# CONFIG_SENSORS_TSL2550 is not set
|
||||||
|
# CONFIG_I2C_DEBUG_CORE is not set
|
||||||
|
# CONFIG_I2C_DEBUG_ALGO is not set
|
||||||
|
# CONFIG_I2C_DEBUG_BUS is not set
|
||||||
|
# CONFIG_I2C_DEBUG_CHIP is not set
|
||||||
# CONFIG_SPI is not set
|
# CONFIG_SPI is not set
|
||||||
CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
|
CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
|
||||||
# CONFIG_GPIOLIB is not set
|
# CONFIG_GPIOLIB is not set
|
||||||
# CONFIG_W1 is not set
|
# CONFIG_W1 is not set
|
||||||
# CONFIG_POWER_SUPPLY is not set
|
# CONFIG_POWER_SUPPLY is not set
|
||||||
# CONFIG_HWMON is not set
|
CONFIG_HWMON=y
|
||||||
|
# CONFIG_HWMON_VID is not set
|
||||||
|
CONFIG_SENSORS_AD7414=y
|
||||||
|
# CONFIG_SENSORS_AD7418 is not set
|
||||||
|
# CONFIG_SENSORS_ADM1021 is not set
|
||||||
|
# CONFIG_SENSORS_ADM1025 is not set
|
||||||
|
# CONFIG_SENSORS_ADM1026 is not set
|
||||||
|
# CONFIG_SENSORS_ADM1029 is not set
|
||||||
|
# CONFIG_SENSORS_ADM1031 is not set
|
||||||
|
# CONFIG_SENSORS_ADM9240 is not set
|
||||||
|
# CONFIG_SENSORS_ADT7462 is not set
|
||||||
|
# CONFIG_SENSORS_ADT7470 is not set
|
||||||
|
# CONFIG_SENSORS_ADT7473 is not set
|
||||||
|
# CONFIG_SENSORS_ADT7475 is not set
|
||||||
|
# CONFIG_SENSORS_ATXP1 is not set
|
||||||
|
# CONFIG_SENSORS_DS1621 is not set
|
||||||
|
# CONFIG_SENSORS_I5K_AMB is not set
|
||||||
|
# CONFIG_SENSORS_F71805F is not set
|
||||||
|
# CONFIG_SENSORS_F71882FG is not set
|
||||||
|
# CONFIG_SENSORS_F75375S is not set
|
||||||
|
# CONFIG_SENSORS_GL518SM is not set
|
||||||
|
# CONFIG_SENSORS_GL520SM is not set
|
||||||
|
# CONFIG_SENSORS_IT87 is not set
|
||||||
|
# CONFIG_SENSORS_LM63 is not set
|
||||||
|
# CONFIG_SENSORS_LM75 is not set
|
||||||
|
# CONFIG_SENSORS_LM77 is not set
|
||||||
|
# CONFIG_SENSORS_LM78 is not set
|
||||||
|
# CONFIG_SENSORS_LM80 is not set
|
||||||
|
# CONFIG_SENSORS_LM83 is not set
|
||||||
|
# CONFIG_SENSORS_LM85 is not set
|
||||||
|
# CONFIG_SENSORS_LM87 is not set
|
||||||
|
# CONFIG_SENSORS_LM90 is not set
|
||||||
|
# CONFIG_SENSORS_LM92 is not set
|
||||||
|
# CONFIG_SENSORS_LM93 is not set
|
||||||
|
# CONFIG_SENSORS_LTC4245 is not set
|
||||||
|
# CONFIG_SENSORS_MAX1619 is not set
|
||||||
|
# CONFIG_SENSORS_MAX6650 is not set
|
||||||
|
# CONFIG_SENSORS_PC87360 is not set
|
||||||
|
# CONFIG_SENSORS_PC87427 is not set
|
||||||
|
# CONFIG_SENSORS_SIS5595 is not set
|
||||||
|
# CONFIG_SENSORS_DME1737 is not set
|
||||||
|
# CONFIG_SENSORS_SMSC47M1 is not set
|
||||||
|
# CONFIG_SENSORS_SMSC47M192 is not set
|
||||||
|
# CONFIG_SENSORS_SMSC47B397 is not set
|
||||||
|
# CONFIG_SENSORS_ADS7828 is not set
|
||||||
|
# CONFIG_SENSORS_THMC50 is not set
|
||||||
|
# CONFIG_SENSORS_VIA686A is not set
|
||||||
|
# CONFIG_SENSORS_VT1211 is not set
|
||||||
|
# CONFIG_SENSORS_VT8231 is not set
|
||||||
|
# CONFIG_SENSORS_W83781D is not set
|
||||||
|
# CONFIG_SENSORS_W83791D is not set
|
||||||
|
# CONFIG_SENSORS_W83792D is not set
|
||||||
|
# CONFIG_SENSORS_W83793 is not set
|
||||||
|
# CONFIG_SENSORS_W83L785TS is not set
|
||||||
|
# CONFIG_SENSORS_W83L786NG is not set
|
||||||
|
# CONFIG_SENSORS_W83627HF is not set
|
||||||
|
# CONFIG_SENSORS_W83627EHF is not set
|
||||||
|
# CONFIG_HWMON_DEBUG_CHIP is not set
|
||||||
# CONFIG_THERMAL is not set
|
# CONFIG_THERMAL is not set
|
||||||
# CONFIG_THERMAL_HWMON is not set
|
# CONFIG_THERMAL_HWMON is not set
|
||||||
# CONFIG_WATCHDOG is not set
|
# CONFIG_WATCHDOG is not set
|
||||||
|
|
@ -556,7 +694,12 @@ CONFIG_SSB_POSSIBLE=y
|
||||||
# CONFIG_MFD_CORE is not set
|
# CONFIG_MFD_CORE is not set
|
||||||
# CONFIG_MFD_SM501 is not set
|
# CONFIG_MFD_SM501 is not set
|
||||||
# CONFIG_HTC_PASIC3 is not set
|
# CONFIG_HTC_PASIC3 is not set
|
||||||
|
# CONFIG_TWL4030_CORE is not set
|
||||||
# CONFIG_MFD_TMIO is not set
|
# CONFIG_MFD_TMIO is not set
|
||||||
|
# CONFIG_PMIC_DA903X is not set
|
||||||
|
# CONFIG_MFD_WM8400 is not set
|
||||||
|
# CONFIG_MFD_WM8350_I2C is not set
|
||||||
|
# CONFIG_MFD_PCF50633 is not set
|
||||||
# CONFIG_REGULATOR is not set
|
# CONFIG_REGULATOR is not set
|
||||||
|
|
||||||
#
|
#
|
||||||
|
|
@ -574,6 +717,7 @@ CONFIG_SSB_POSSIBLE=y
|
||||||
# Multimedia drivers
|
# Multimedia drivers
|
||||||
#
|
#
|
||||||
CONFIG_DAB=y
|
CONFIG_DAB=y
|
||||||
|
# CONFIG_USB_DABUSB is not set
|
||||||
|
|
||||||
#
|
#
|
||||||
# Graphics support
|
# Graphics support
|
||||||
|
|
@ -590,7 +734,109 @@ CONFIG_VIDEO_OUTPUT_CONTROL=m
|
||||||
#
|
#
|
||||||
# CONFIG_DISPLAY_SUPPORT is not set
|
# CONFIG_DISPLAY_SUPPORT is not set
|
||||||
# CONFIG_SOUND is not set
|
# CONFIG_SOUND is not set
|
||||||
# CONFIG_USB_SUPPORT is not set
|
CONFIG_USB_SUPPORT=y
|
||||||
|
CONFIG_USB_ARCH_HAS_HCD=y
|
||||||
|
CONFIG_USB_ARCH_HAS_OHCI=y
|
||||||
|
CONFIG_USB_ARCH_HAS_EHCI=y
|
||||||
|
CONFIG_USB=y
|
||||||
|
# CONFIG_USB_DEBUG is not set
|
||||||
|
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
|
||||||
|
|
||||||
|
#
|
||||||
|
# Miscellaneous USB options
|
||||||
|
#
|
||||||
|
CONFIG_USB_DEVICEFS=y
|
||||||
|
CONFIG_USB_DEVICE_CLASS=y
|
||||||
|
# CONFIG_USB_DYNAMIC_MINORS is not set
|
||||||
|
# CONFIG_USB_OTG is not set
|
||||||
|
# CONFIG_USB_OTG_WHITELIST is not set
|
||||||
|
# CONFIG_USB_OTG_BLACKLIST_HUB is not set
|
||||||
|
CONFIG_USB_MON=y
|
||||||
|
# CONFIG_USB_WUSB is not set
|
||||||
|
# CONFIG_USB_WUSB_CBAF is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# USB Host Controller Drivers
|
||||||
|
#
|
||||||
|
# CONFIG_USB_C67X00_HCD is not set
|
||||||
|
CONFIG_USB_EHCI_HCD=m
|
||||||
|
# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
|
||||||
|
# CONFIG_USB_EHCI_TT_NEWSCHED is not set
|
||||||
|
CONFIG_USB_EHCI_HCD_PPC_OF=y
|
||||||
|
# CONFIG_USB_OXU210HP_HCD is not set
|
||||||
|
# CONFIG_USB_ISP116X_HCD is not set
|
||||||
|
# CONFIG_USB_ISP1760_HCD is not set
|
||||||
|
CONFIG_USB_OHCI_HCD=y
|
||||||
|
CONFIG_USB_OHCI_HCD_PPC_OF=y
|
||||||
|
CONFIG_USB_OHCI_HCD_PPC_OF_BE=y
|
||||||
|
CONFIG_USB_OHCI_HCD_PPC_OF_LE=y
|
||||||
|
CONFIG_USB_OHCI_HCD_PCI=y
|
||||||
|
CONFIG_USB_OHCI_BIG_ENDIAN_DESC=y
|
||||||
|
CONFIG_USB_OHCI_BIG_ENDIAN_MMIO=y
|
||||||
|
CONFIG_USB_OHCI_LITTLE_ENDIAN=y
|
||||||
|
# CONFIG_USB_UHCI_HCD is not set
|
||||||
|
# CONFIG_USB_SL811_HCD is not set
|
||||||
|
# CONFIG_USB_R8A66597_HCD is not set
|
||||||
|
# CONFIG_USB_WHCI_HCD is not set
|
||||||
|
# CONFIG_USB_HWA_HCD is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# USB Device Class drivers
|
||||||
|
#
|
||||||
|
# CONFIG_USB_ACM is not set
|
||||||
|
# CONFIG_USB_PRINTER is not set
|
||||||
|
# CONFIG_USB_WDM is not set
|
||||||
|
# CONFIG_USB_TMC is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
|
||||||
|
#
|
||||||
|
|
||||||
|
#
|
||||||
|
# see USB_STORAGE Help for more information
|
||||||
|
#
|
||||||
|
CONFIG_USB_LIBUSUAL=y
|
||||||
|
|
||||||
|
#
|
||||||
|
# USB Imaging devices
|
||||||
|
#
|
||||||
|
# CONFIG_USB_MDC800 is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# USB port drivers
|
||||||
|
#
|
||||||
|
# CONFIG_USB_SERIAL is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# USB Miscellaneous drivers
|
||||||
|
#
|
||||||
|
# CONFIG_USB_EMI62 is not set
|
||||||
|
# CONFIG_USB_EMI26 is not set
|
||||||
|
# CONFIG_USB_ADUTUX is not set
|
||||||
|
# CONFIG_USB_SEVSEG is not set
|
||||||
|
# CONFIG_USB_RIO500 is not set
|
||||||
|
# CONFIG_USB_LEGOTOWER is not set
|
||||||
|
# CONFIG_USB_LCD is not set
|
||||||
|
# CONFIG_USB_BERRY_CHARGE is not set
|
||||||
|
# CONFIG_USB_LED is not set
|
||||||
|
# CONFIG_USB_CYPRESS_CY7C63 is not set
|
||||||
|
# CONFIG_USB_CYTHERM is not set
|
||||||
|
# CONFIG_USB_PHIDGET is not set
|
||||||
|
# CONFIG_USB_IDMOUSE is not set
|
||||||
|
# CONFIG_USB_FTDI_ELAN is not set
|
||||||
|
# CONFIG_USB_APPLEDISPLAY is not set
|
||||||
|
# CONFIG_USB_SISUSBVGA is not set
|
||||||
|
# CONFIG_USB_LD is not set
|
||||||
|
# CONFIG_USB_TRANCEVIBRATOR is not set
|
||||||
|
# CONFIG_USB_IOWARRIOR is not set
|
||||||
|
# CONFIG_USB_TEST is not set
|
||||||
|
# CONFIG_USB_ISIGHTFW is not set
|
||||||
|
# CONFIG_USB_VST is not set
|
||||||
|
# CONFIG_USB_GADGET is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# OTG and related infrastructure
|
||||||
|
#
|
||||||
# CONFIG_UWB is not set
|
# CONFIG_UWB is not set
|
||||||
# CONFIG_MMC is not set
|
# CONFIG_MMC is not set
|
||||||
# CONFIG_MEMSTICK is not set
|
# CONFIG_MEMSTICK is not set
|
||||||
|
|
|
||||||
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
|
@ -1,7 +1,7 @@
|
||||||
#
|
#
|
||||||
# Automatically generated make config: don't edit
|
# Automatically generated make config: don't edit
|
||||||
# Linux kernel version: 2.6.29-rc2
|
# Linux kernel version: 2.6.29-rc3
|
||||||
# Mon Jan 26 21:40:44 2009
|
# Fri Feb 6 09:48:53 2009
|
||||||
#
|
#
|
||||||
# CONFIG_PPC64 is not set
|
# CONFIG_PPC64 is not set
|
||||||
|
|
||||||
|
|
@ -388,7 +388,10 @@ CONFIG_MTD=y
|
||||||
CONFIG_MTD_CONCAT=y
|
CONFIG_MTD_CONCAT=y
|
||||||
CONFIG_MTD_PARTITIONS=y
|
CONFIG_MTD_PARTITIONS=y
|
||||||
# CONFIG_MTD_TESTS is not set
|
# CONFIG_MTD_TESTS is not set
|
||||||
# CONFIG_MTD_REDBOOT_PARTS is not set
|
CONFIG_MTD_REDBOOT_PARTS=y
|
||||||
|
CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
|
||||||
|
# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set
|
||||||
|
# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
|
||||||
CONFIG_MTD_CMDLINE_PARTS=y
|
CONFIG_MTD_CMDLINE_PARTS=y
|
||||||
# CONFIG_MTD_OF_PARTS is not set
|
# CONFIG_MTD_OF_PARTS is not set
|
||||||
# CONFIG_MTD_AR7_PARTS is not set
|
# CONFIG_MTD_AR7_PARTS is not set
|
||||||
|
|
@ -502,7 +505,7 @@ CONFIG_MISC_DEVICES=y
|
||||||
#
|
#
|
||||||
# EEPROM support
|
# EEPROM support
|
||||||
#
|
#
|
||||||
# CONFIG_EEPROM_AT24 is not set
|
CONFIG_EEPROM_AT24=y
|
||||||
# CONFIG_EEPROM_LEGACY is not set
|
# CONFIG_EEPROM_LEGACY is not set
|
||||||
# CONFIG_EEPROM_93CX6 is not set
|
# CONFIG_EEPROM_93CX6 is not set
|
||||||
CONFIG_HAVE_IDE=y
|
CONFIG_HAVE_IDE=y
|
||||||
|
|
@ -678,7 +681,7 @@ CONFIG_PHYLIB=y
|
||||||
# CONFIG_MARVELL_PHY is not set
|
# CONFIG_MARVELL_PHY is not set
|
||||||
# CONFIG_DAVICOM_PHY is not set
|
# CONFIG_DAVICOM_PHY is not set
|
||||||
# CONFIG_QSEMI_PHY is not set
|
# CONFIG_QSEMI_PHY is not set
|
||||||
# CONFIG_LXT_PHY is not set
|
CONFIG_LXT_PHY=y
|
||||||
# CONFIG_CICADA_PHY is not set
|
# CONFIG_CICADA_PHY is not set
|
||||||
# CONFIG_VITESSE_PHY is not set
|
# CONFIG_VITESSE_PHY is not set
|
||||||
# CONFIG_SMSC_PHY is not set
|
# CONFIG_SMSC_PHY is not set
|
||||||
|
|
@ -815,8 +818,6 @@ CONFIG_LEGACY_PTY_COUNT=256
|
||||||
# CONFIG_IPMI_HANDLER is not set
|
# CONFIG_IPMI_HANDLER is not set
|
||||||
# CONFIG_HW_RANDOM is not set
|
# CONFIG_HW_RANDOM is not set
|
||||||
# CONFIG_NVRAM is not set
|
# CONFIG_NVRAM is not set
|
||||||
CONFIG_GEN_RTC=y
|
|
||||||
# CONFIG_GEN_RTC_X is not set
|
|
||||||
# CONFIG_R3964 is not set
|
# CONFIG_R3964 is not set
|
||||||
# CONFIG_APPLICOM is not set
|
# CONFIG_APPLICOM is not set
|
||||||
# CONFIG_RAW_DRIVER is not set
|
# CONFIG_RAW_DRIVER is not set
|
||||||
|
|
@ -1281,7 +1282,61 @@ CONFIG_NEW_LEDS=y
|
||||||
# CONFIG_ACCESSIBILITY is not set
|
# CONFIG_ACCESSIBILITY is not set
|
||||||
# CONFIG_INFINIBAND is not set
|
# CONFIG_INFINIBAND is not set
|
||||||
# CONFIG_EDAC is not set
|
# CONFIG_EDAC is not set
|
||||||
# CONFIG_RTC_CLASS is not set
|
CONFIG_RTC_LIB=y
|
||||||
|
CONFIG_RTC_CLASS=y
|
||||||
|
CONFIG_RTC_HCTOSYS=y
|
||||||
|
CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
|
||||||
|
# CONFIG_RTC_DEBUG is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# RTC interfaces
|
||||||
|
#
|
||||||
|
CONFIG_RTC_INTF_SYSFS=y
|
||||||
|
CONFIG_RTC_INTF_PROC=y
|
||||||
|
CONFIG_RTC_INTF_DEV=y
|
||||||
|
# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
|
||||||
|
# CONFIG_RTC_DRV_TEST is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# I2C RTC drivers
|
||||||
|
#
|
||||||
|
CONFIG_RTC_DRV_DS1307=y
|
||||||
|
# CONFIG_RTC_DRV_DS1374 is not set
|
||||||
|
# CONFIG_RTC_DRV_DS1672 is not set
|
||||||
|
# CONFIG_RTC_DRV_MAX6900 is not set
|
||||||
|
# CONFIG_RTC_DRV_RS5C372 is not set
|
||||||
|
# CONFIG_RTC_DRV_ISL1208 is not set
|
||||||
|
# CONFIG_RTC_DRV_X1205 is not set
|
||||||
|
# CONFIG_RTC_DRV_PCF8563 is not set
|
||||||
|
# CONFIG_RTC_DRV_PCF8583 is not set
|
||||||
|
# CONFIG_RTC_DRV_M41T80 is not set
|
||||||
|
# CONFIG_RTC_DRV_S35390A is not set
|
||||||
|
# CONFIG_RTC_DRV_FM3130 is not set
|
||||||
|
# CONFIG_RTC_DRV_RX8581 is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# SPI RTC drivers
|
||||||
|
#
|
||||||
|
|
||||||
|
#
|
||||||
|
# Platform RTC drivers
|
||||||
|
#
|
||||||
|
# CONFIG_RTC_DRV_CMOS is not set
|
||||||
|
# CONFIG_RTC_DRV_DS1286 is not set
|
||||||
|
# CONFIG_RTC_DRV_DS1511 is not set
|
||||||
|
# CONFIG_RTC_DRV_DS1553 is not set
|
||||||
|
# CONFIG_RTC_DRV_DS1742 is not set
|
||||||
|
# CONFIG_RTC_DRV_STK17TA8 is not set
|
||||||
|
# CONFIG_RTC_DRV_M48T86 is not set
|
||||||
|
# CONFIG_RTC_DRV_M48T35 is not set
|
||||||
|
# CONFIG_RTC_DRV_M48T59 is not set
|
||||||
|
# CONFIG_RTC_DRV_BQ4802 is not set
|
||||||
|
# CONFIG_RTC_DRV_V3020 is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# on-CPU RTC drivers
|
||||||
|
#
|
||||||
|
# CONFIG_RTC_DRV_PPC is not set
|
||||||
# CONFIG_DMADEVICES is not set
|
# CONFIG_DMADEVICES is not set
|
||||||
# CONFIG_UIO is not set
|
# CONFIG_UIO is not set
|
||||||
# CONFIG_STAGING is not set
|
# CONFIG_STAGING is not set
|
||||||
|
|
|
||||||
|
|
@ -2067,9 +2067,9 @@ CONFIG_DEBUG_STACKOVERFLOW=y
|
||||||
CONFIG_DEBUG_STACK_USAGE=y
|
CONFIG_DEBUG_STACK_USAGE=y
|
||||||
# CONFIG_DEBUG_PAGEALLOC is not set
|
# CONFIG_DEBUG_PAGEALLOC is not set
|
||||||
# CONFIG_HCALL_STATS is not set
|
# CONFIG_HCALL_STATS is not set
|
||||||
# CONFIG_CODE_PATCHING_SELFTEST is not set
|
CONFIG_CODE_PATCHING_SELFTEST=y
|
||||||
# CONFIG_FTR_FIXUP_SELFTEST is not set
|
CONFIG_FTR_FIXUP_SELFTEST=y
|
||||||
# CONFIG_MSI_BITMAP_SELFTEST is not set
|
CONFIG_MSI_BITMAP_SELFTEST=y
|
||||||
CONFIG_XMON=y
|
CONFIG_XMON=y
|
||||||
# CONFIG_XMON_DEFAULT is not set
|
# CONFIG_XMON_DEFAULT is not set
|
||||||
CONFIG_XMON_DISASSEMBLY=y
|
CONFIG_XMON_DISASSEMBLY=y
|
||||||
|
|
|
||||||
|
|
@ -11,9 +11,7 @@
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include <asm/types.h>
|
#include <asm/types.h>
|
||||||
|
#include <asm/ppc-opcode.h>
|
||||||
#define PPC_NOP_INSTR 0x60000000
|
|
||||||
#define PPC_LWSYNC_INSTR 0x7c2004ac
|
|
||||||
|
|
||||||
/* Flags for create_branch:
|
/* Flags for create_branch:
|
||||||
* "b" == create_branch(addr, target, 0);
|
* "b" == create_branch(addr, target, 0);
|
||||||
|
|
|
||||||
|
|
@ -145,6 +145,7 @@ extern const char *powerpc_base_platform;
|
||||||
#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
|
#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
|
||||||
#define CPU_FTR_L2CSR ASM_CONST(0x0000000000000080)
|
#define CPU_FTR_L2CSR ASM_CONST(0x0000000000000080)
|
||||||
#define CPU_FTR_601 ASM_CONST(0x0000000000000100)
|
#define CPU_FTR_601 ASM_CONST(0x0000000000000100)
|
||||||
|
#define CPU_FTR_DBELL ASM_CONST(0x0000000000000200)
|
||||||
#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
|
#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
|
||||||
#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
|
#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
|
||||||
#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
|
#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
|
||||||
|
|
@ -375,7 +376,8 @@ extern const char *powerpc_base_platform;
|
||||||
CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
|
CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
|
||||||
#define CPU_FTRS_E500MC (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
|
#define CPU_FTRS_E500MC (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
|
||||||
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \
|
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \
|
||||||
CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE)
|
CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
|
||||||
|
CPU_FTR_DBELL)
|
||||||
#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
|
#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
|
||||||
|
|
||||||
/* 64-bit CPUs */
|
/* 64-bit CPUs */
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,43 @@
|
||||||
|
/*
|
||||||
|
* Copyright 2009 Freescale Semicondutor, Inc.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License
|
||||||
|
* as published by the Free Software Foundation; either version
|
||||||
|
* 2 of the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* provides masks and opcode images for use by code generation, emulation
|
||||||
|
* and for instructions that older assemblers might not know about
|
||||||
|
*/
|
||||||
|
#ifndef _ASM_POWERPC_DBELL_H
|
||||||
|
#define _ASM_POWERPC_DBELL_H
|
||||||
|
|
||||||
|
#include <linux/smp.h>
|
||||||
|
#include <linux/threads.h>
|
||||||
|
|
||||||
|
#include <asm/ppc-opcode.h>
|
||||||
|
|
||||||
|
#define PPC_DBELL_MSG_BRDCAST (0x04000000)
|
||||||
|
#define PPC_DBELL_TYPE(x) (((x) & 0xf) << 28)
|
||||||
|
enum ppc_dbell {
|
||||||
|
PPC_DBELL = 0, /* doorbell */
|
||||||
|
PPC_DBELL_CRIT = 1, /* critical doorbell */
|
||||||
|
PPC_G_DBELL = 2, /* guest doorbell */
|
||||||
|
PPC_G_DBELL_CRIT = 3, /* guest critical doorbell */
|
||||||
|
PPC_G_DBELL_MC = 4, /* guest mcheck doorbell */
|
||||||
|
};
|
||||||
|
|
||||||
|
#ifdef CONFIG_SMP
|
||||||
|
extern unsigned long dbell_smp_message[NR_CPUS];
|
||||||
|
extern void smp_dbell_message_pass(int target, int msg);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
static inline void ppc_msgsnd(enum ppc_dbell type, u32 flags, u32 tag)
|
||||||
|
{
|
||||||
|
u32 msg = PPC_DBELL_TYPE(type) | (flags & PPC_DBELL_MSG_BRDCAST) |
|
||||||
|
(tag & 0x07ffffff);
|
||||||
|
|
||||||
|
__asm__ __volatile__ (PPC_MSGSND(%0) : : "r" (msg));
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* _ASM_POWERPC_DBELL_H */
|
||||||
|
|
@ -109,18 +109,8 @@ static inline struct dma_mapping_ops *get_dma_ops(struct device *dev)
|
||||||
* only ISA DMA device we support is the floppy and we have a hack
|
* only ISA DMA device we support is the floppy and we have a hack
|
||||||
* in the floppy driver directly to get a device for us.
|
* in the floppy driver directly to get a device for us.
|
||||||
*/
|
*/
|
||||||
|
if (unlikely(dev == NULL))
|
||||||
if (unlikely(dev == NULL) || dev->archdata.dma_ops == NULL) {
|
|
||||||
#ifdef CONFIG_PPC64
|
|
||||||
return NULL;
|
return NULL;
|
||||||
#else
|
|
||||||
/* Use default on 32-bit if dma_ops is not set up */
|
|
||||||
/* TODO: Long term, we should fix drivers so that dev and
|
|
||||||
* archdata dma_ops are set up for all buses.
|
|
||||||
*/
|
|
||||||
return &dma_direct_ops;
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
return dev->archdata.dma_ops;
|
return dev->archdata.dma_ops;
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -8,6 +8,7 @@
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#include <linux/types.h>
|
#include <linux/types.h>
|
||||||
|
|
||||||
#include <asm/ptrace.h>
|
#include <asm/ptrace.h>
|
||||||
#include <asm/cputable.h>
|
#include <asm/cputable.h>
|
||||||
#include <asm/auxvec.h>
|
#include <asm/auxvec.h>
|
||||||
|
|
@ -178,7 +179,8 @@ typedef elf_fpreg_t elf_vsrreghalf_t32[ELF_NVSRHALFREG];
|
||||||
the loader. We need to make sure that it is out of the way of the program
|
the loader. We need to make sure that it is out of the way of the program
|
||||||
that it will "exec", and that there is sufficient room for the brk. */
|
that it will "exec", and that there is sufficient room for the brk. */
|
||||||
|
|
||||||
#define ELF_ET_DYN_BASE (0x20000000)
|
extern unsigned long randomize_et_dyn(unsigned long base);
|
||||||
|
#define ELF_ET_DYN_BASE (randomize_et_dyn(0x20000000))
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Our registers are always unsigned longs, whether we're a 32 bit
|
* Our registers are always unsigned longs, whether we're a 32 bit
|
||||||
|
|
@ -270,6 +272,14 @@ extern int arch_setup_additional_pages(struct linux_binprm *bprm,
|
||||||
int uses_interp);
|
int uses_interp);
|
||||||
#define VDSO_AUX_ENT(a,b) NEW_AUX_ENT(a,b);
|
#define VDSO_AUX_ENT(a,b) NEW_AUX_ENT(a,b);
|
||||||
|
|
||||||
|
/* 1GB for 64bit, 8MB for 32bit */
|
||||||
|
#define STACK_RND_MASK (is_32bit_task() ? \
|
||||||
|
(0x7ff >> (PAGE_SHIFT - 12)) : \
|
||||||
|
(0x3ffff >> (PAGE_SHIFT - 12)))
|
||||||
|
|
||||||
|
extern unsigned long arch_randomize_brk(struct mm_struct *mm);
|
||||||
|
#define arch_randomize_brk arch_randomize_brk
|
||||||
|
|
||||||
#endif /* __KERNEL__ */
|
#endif /* __KERNEL__ */
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
||||||
|
|
@ -61,7 +61,7 @@ extern void __set_fixmap (enum fixed_addresses idx,
|
||||||
* Some hardware wants to get fixmapped without caching.
|
* Some hardware wants to get fixmapped without caching.
|
||||||
*/
|
*/
|
||||||
#define set_fixmap_nocache(idx, phys) \
|
#define set_fixmap_nocache(idx, phys) \
|
||||||
__set_fixmap(idx, phys, PAGE_KERNEL_NOCACHE)
|
__set_fixmap(idx, phys, PAGE_KERNEL_NCG)
|
||||||
|
|
||||||
#define clear_fixmap(idx) \
|
#define clear_fixmap(idx) \
|
||||||
__set_fixmap(idx, 0, __pgprot(0))
|
__set_fixmap(idx, 0, __pgprot(0))
|
||||||
|
|
|
||||||
|
|
@ -5,7 +5,44 @@
|
||||||
#define MCOUNT_ADDR ((long)(_mcount))
|
#define MCOUNT_ADDR ((long)(_mcount))
|
||||||
#define MCOUNT_INSN_SIZE 4 /* sizeof mcount call */
|
#define MCOUNT_INSN_SIZE 4 /* sizeof mcount call */
|
||||||
|
|
||||||
#ifndef __ASSEMBLY__
|
#ifdef __ASSEMBLY__
|
||||||
|
|
||||||
|
/* Based off of objdump optput from glibc */
|
||||||
|
|
||||||
|
#define MCOUNT_SAVE_FRAME \
|
||||||
|
stwu r1,-48(r1); \
|
||||||
|
stw r3, 12(r1); \
|
||||||
|
stw r4, 16(r1); \
|
||||||
|
stw r5, 20(r1); \
|
||||||
|
stw r6, 24(r1); \
|
||||||
|
mflr r3; \
|
||||||
|
lwz r4, 52(r1); \
|
||||||
|
mfcr r5; \
|
||||||
|
stw r7, 28(r1); \
|
||||||
|
stw r8, 32(r1); \
|
||||||
|
stw r9, 36(r1); \
|
||||||
|
stw r10,40(r1); \
|
||||||
|
stw r3, 44(r1); \
|
||||||
|
stw r5, 8(r1)
|
||||||
|
|
||||||
|
#define MCOUNT_RESTORE_FRAME \
|
||||||
|
lwz r6, 8(r1); \
|
||||||
|
lwz r0, 44(r1); \
|
||||||
|
lwz r3, 12(r1); \
|
||||||
|
mtctr r0; \
|
||||||
|
lwz r4, 16(r1); \
|
||||||
|
mtcr r6; \
|
||||||
|
lwz r5, 20(r1); \
|
||||||
|
lwz r6, 24(r1); \
|
||||||
|
lwz r0, 52(r1); \
|
||||||
|
lwz r7, 28(r1); \
|
||||||
|
lwz r8, 32(r1); \
|
||||||
|
mtlr r0; \
|
||||||
|
lwz r9, 36(r1); \
|
||||||
|
lwz r10,40(r1); \
|
||||||
|
addi r1, r1, 48
|
||||||
|
|
||||||
|
#else /* !__ASSEMBLY__ */
|
||||||
extern void _mcount(void);
|
extern void _mcount(void);
|
||||||
|
|
||||||
#ifdef CONFIG_DYNAMIC_FTRACE
|
#ifdef CONFIG_DYNAMIC_FTRACE
|
||||||
|
|
|
||||||
|
|
@ -39,15 +39,15 @@ extern pte_t *pkmap_page_table;
|
||||||
* chunk of RAM.
|
* chunk of RAM.
|
||||||
*/
|
*/
|
||||||
/*
|
/*
|
||||||
* We use one full pte table with 4K pages. And with 16K/64K pages pte
|
* We use one full pte table with 4K pages. And with 16K/64K/256K pages pte
|
||||||
* table covers enough memory (32MB and 512MB resp.) that both FIXMAP
|
* table covers enough memory (32MB/512MB/2GB resp.), so that both FIXMAP
|
||||||
* and PKMAP can be placed in single pte table. We use 1024 pages for
|
* and PKMAP can be placed in a single pte table. We use 512 pages for PKMAP
|
||||||
* PKMAP in case of 16K/64K pages.
|
* in case of 16K/64K/256K page sizes.
|
||||||
*/
|
*/
|
||||||
#ifdef CONFIG_PPC_4K_PAGES
|
#ifdef CONFIG_PPC_4K_PAGES
|
||||||
#define PKMAP_ORDER PTE_SHIFT
|
#define PKMAP_ORDER PTE_SHIFT
|
||||||
#else
|
#else
|
||||||
#define PKMAP_ORDER 10
|
#define PKMAP_ORDER 9
|
||||||
#endif
|
#endif
|
||||||
#define LAST_PKMAP (1 << PKMAP_ORDER)
|
#define LAST_PKMAP (1 << PKMAP_ORDER)
|
||||||
#ifndef CONFIG_PPC_4K_PAGES
|
#ifndef CONFIG_PPC_4K_PAGES
|
||||||
|
|
@ -99,7 +99,7 @@ static inline void *kmap_atomic_prot(struct page *page, enum km_type type, pgpro
|
||||||
#ifdef CONFIG_DEBUG_HIGHMEM
|
#ifdef CONFIG_DEBUG_HIGHMEM
|
||||||
BUG_ON(!pte_none(*(kmap_pte-idx)));
|
BUG_ON(!pte_none(*(kmap_pte-idx)));
|
||||||
#endif
|
#endif
|
||||||
__set_pte_at(&init_mm, vaddr, kmap_pte-idx, mk_pte(page, prot));
|
__set_pte_at(&init_mm, vaddr, kmap_pte-idx, mk_pte(page, prot), 1);
|
||||||
local_flush_tlb_page(NULL, vaddr);
|
local_flush_tlb_page(NULL, vaddr);
|
||||||
|
|
||||||
return (void*) vaddr;
|
return (void*) vaddr;
|
||||||
|
|
|
||||||
|
|
@ -129,7 +129,7 @@ static inline int irqs_disabled_flags(unsigned long flags)
|
||||||
* interrupt-retrigger: should we handle this via lost interrupts and IPIs
|
* interrupt-retrigger: should we handle this via lost interrupts and IPIs
|
||||||
* or should we not care like we do now ? --BenH.
|
* or should we not care like we do now ? --BenH.
|
||||||
*/
|
*/
|
||||||
struct hw_interrupt_type;
|
struct irq_chip;
|
||||||
|
|
||||||
#endif /* __KERNEL__ */
|
#endif /* __KERNEL__ */
|
||||||
#endif /* _ASM_POWERPC_HW_IRQ_H */
|
#endif /* _ASM_POWERPC_HW_IRQ_H */
|
||||||
|
|
|
||||||
|
|
@ -632,6 +632,9 @@ static inline void iosync(void)
|
||||||
* ioremap_flags and cannot be hooked (but can be used by a hook on one
|
* ioremap_flags and cannot be hooked (but can be used by a hook on one
|
||||||
* of the previous ones)
|
* of the previous ones)
|
||||||
*
|
*
|
||||||
|
* * __ioremap_caller is the same as above but takes an explicit caller
|
||||||
|
* reference rather than using __builtin_return_address(0)
|
||||||
|
*
|
||||||
* * __iounmap, is the low level implementation used by iounmap and cannot
|
* * __iounmap, is the low level implementation used by iounmap and cannot
|
||||||
* be hooked (but can be used by a hook on iounmap)
|
* be hooked (but can be used by a hook on iounmap)
|
||||||
*
|
*
|
||||||
|
|
@ -646,6 +649,9 @@ extern void iounmap(volatile void __iomem *addr);
|
||||||
|
|
||||||
extern void __iomem *__ioremap(phys_addr_t, unsigned long size,
|
extern void __iomem *__ioremap(phys_addr_t, unsigned long size,
|
||||||
unsigned long flags);
|
unsigned long flags);
|
||||||
|
extern void __iomem *__ioremap_caller(phys_addr_t, unsigned long size,
|
||||||
|
unsigned long flags, void *caller);
|
||||||
|
|
||||||
extern void __iounmap(volatile void __iomem *addr);
|
extern void __iounmap(volatile void __iomem *addr);
|
||||||
|
|
||||||
extern void __iomem * __ioremap_at(phys_addr_t pa, void *ea,
|
extern void __iomem * __ioremap_at(phys_addr_t pa, void *ea,
|
||||||
|
|
|
||||||
|
|
@ -97,7 +97,7 @@ struct lppaca {
|
||||||
u64 saved_gpr4; // Saved GPR4 x28-x2F
|
u64 saved_gpr4; // Saved GPR4 x28-x2F
|
||||||
u64 saved_gpr5; // Saved GPR5 x30-x37
|
u64 saved_gpr5; // Saved GPR5 x30-x37
|
||||||
|
|
||||||
u8 reserved4; // Reserved x38-x38
|
u8 dtl_enable_mask; // Dispatch Trace Log mask x38-x38
|
||||||
u8 donate_dedicated_cpu; // Donate dedicated CPU cycles x39-x39
|
u8 donate_dedicated_cpu; // Donate dedicated CPU cycles x39-x39
|
||||||
u8 fpregs_in_use; // FP regs in use x3A-x3A
|
u8 fpregs_in_use; // FP regs in use x3A-x3A
|
||||||
u8 pmcregs_in_use; // PMC regs in use x3B-x3B
|
u8 pmcregs_in_use; // PMC regs in use x3B-x3B
|
||||||
|
|
@ -133,8 +133,10 @@ struct lppaca {
|
||||||
//=============================================================================
|
//=============================================================================
|
||||||
// CACHE_LINE_4-5 0x0180 - 0x027F Contains PMC interrupt data
|
// CACHE_LINE_4-5 0x0180 - 0x027F Contains PMC interrupt data
|
||||||
//=============================================================================
|
//=============================================================================
|
||||||
u32 page_ins; // CMO Hint - # page ins by OS x00-x04
|
u32 page_ins; // CMO Hint - # page ins by OS x00-x03
|
||||||
u8 pmc_save_area[252]; // PMC interrupt Area x04-xFF
|
u8 reserved8[148]; // Reserved x04-x97
|
||||||
|
volatile u64 dtl_idx; // Dispatch Trace Log head idx x98-x9F
|
||||||
|
u8 reserved9[96]; // Reserved xA0-xFF
|
||||||
} __attribute__((__aligned__(0x400)));
|
} __attribute__((__aligned__(0x400)));
|
||||||
|
|
||||||
extern struct lppaca lppaca[];
|
extern struct lppaca lppaca[];
|
||||||
|
|
|
||||||
|
|
@ -90,7 +90,7 @@ struct machdep_calls {
|
||||||
void (*tce_flush)(struct iommu_table *tbl);
|
void (*tce_flush)(struct iommu_table *tbl);
|
||||||
|
|
||||||
void __iomem * (*ioremap)(phys_addr_t addr, unsigned long size,
|
void __iomem * (*ioremap)(phys_addr_t addr, unsigned long size,
|
||||||
unsigned long flags);
|
unsigned long flags, void *caller);
|
||||||
void (*iounmap)(volatile void __iomem *token);
|
void (*iounmap)(volatile void __iomem *token);
|
||||||
|
|
||||||
#ifdef CONFIG_PM
|
#ifdef CONFIG_PM
|
||||||
|
|
@ -327,8 +327,6 @@ extern void __devinit smp_generic_take_timebase(void);
|
||||||
*/
|
*/
|
||||||
/* Print a boot progress message. */
|
/* Print a boot progress message. */
|
||||||
void ppc64_boot_msg(unsigned int src, const char *msg);
|
void ppc64_boot_msg(unsigned int src, const char *msg);
|
||||||
/* Print a termination message (print only -- does not stop the kernel) */
|
|
||||||
void ppc64_terminate_msg(unsigned int src, const char *msg);
|
|
||||||
|
|
||||||
static inline void log_error(char *buf, unsigned int err_type, int fatal)
|
static inline void log_error(char *buf, unsigned int err_type, int fatal)
|
||||||
{
|
{
|
||||||
|
|
|
||||||
|
|
@ -83,6 +83,8 @@ typedef struct {
|
||||||
#define PPC44x_TLBE_SIZE PPC44x_TLB_16K
|
#define PPC44x_TLBE_SIZE PPC44x_TLB_16K
|
||||||
#elif (PAGE_SHIFT == 16)
|
#elif (PAGE_SHIFT == 16)
|
||||||
#define PPC44x_TLBE_SIZE PPC44x_TLB_64K
|
#define PPC44x_TLBE_SIZE PPC44x_TLB_64K
|
||||||
|
#elif (PAGE_SHIFT == 18)
|
||||||
|
#define PPC44x_TLBE_SIZE PPC44x_TLB_256K
|
||||||
#else
|
#else
|
||||||
#error "Unsupported PAGE_SIZE"
|
#error "Unsupported PAGE_SIZE"
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -1,26 +1,42 @@
|
||||||
#ifndef _ASM_POWERPC_MMU_FSL_BOOKE_H_
|
#ifndef _ASM_POWERPC_MMU_BOOK3E_H_
|
||||||
#define _ASM_POWERPC_MMU_FSL_BOOKE_H_
|
#define _ASM_POWERPC_MMU_BOOK3E_H_
|
||||||
/*
|
/*
|
||||||
* Freescale Book-E MMU support
|
* Freescale Book-E/Book-3e (ISA 2.06+) MMU support
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Book-E defined page sizes */
|
/* Book-3e defined page sizes */
|
||||||
#define BOOKE_PAGESZ_1K 0
|
#define BOOK3E_PAGESZ_1K 0
|
||||||
#define BOOKE_PAGESZ_4K 1
|
#define BOOK3E_PAGESZ_2K 1
|
||||||
#define BOOKE_PAGESZ_16K 2
|
#define BOOK3E_PAGESZ_4K 2
|
||||||
#define BOOKE_PAGESZ_64K 3
|
#define BOOK3E_PAGESZ_8K 3
|
||||||
#define BOOKE_PAGESZ_256K 4
|
#define BOOK3E_PAGESZ_16K 4
|
||||||
#define BOOKE_PAGESZ_1M 5
|
#define BOOK3E_PAGESZ_32K 5
|
||||||
#define BOOKE_PAGESZ_4M 6
|
#define BOOK3E_PAGESZ_64K 6
|
||||||
#define BOOKE_PAGESZ_16M 7
|
#define BOOK3E_PAGESZ_128K 7
|
||||||
#define BOOKE_PAGESZ_64M 8
|
#define BOOK3E_PAGESZ_256K 8
|
||||||
#define BOOKE_PAGESZ_256M 9
|
#define BOOK3E_PAGESZ_512K 9
|
||||||
#define BOOKE_PAGESZ_1GB 10
|
#define BOOK3E_PAGESZ_1M 10
|
||||||
#define BOOKE_PAGESZ_4GB 11
|
#define BOOK3E_PAGESZ_2M 11
|
||||||
#define BOOKE_PAGESZ_16GB 12
|
#define BOOK3E_PAGESZ_4M 12
|
||||||
#define BOOKE_PAGESZ_64GB 13
|
#define BOOK3E_PAGESZ_8M 13
|
||||||
#define BOOKE_PAGESZ_256GB 14
|
#define BOOK3E_PAGESZ_16M 14
|
||||||
#define BOOKE_PAGESZ_1TB 15
|
#define BOOK3E_PAGESZ_32M 15
|
||||||
|
#define BOOK3E_PAGESZ_64M 16
|
||||||
|
#define BOOK3E_PAGESZ_128M 17
|
||||||
|
#define BOOK3E_PAGESZ_256M 18
|
||||||
|
#define BOOK3E_PAGESZ_512M 19
|
||||||
|
#define BOOK3E_PAGESZ_1GB 20
|
||||||
|
#define BOOK3E_PAGESZ_2GB 21
|
||||||
|
#define BOOK3E_PAGESZ_4GB 22
|
||||||
|
#define BOOK3E_PAGESZ_8GB 23
|
||||||
|
#define BOOK3E_PAGESZ_16GB 24
|
||||||
|
#define BOOK3E_PAGESZ_32GB 25
|
||||||
|
#define BOOK3E_PAGESZ_64GB 26
|
||||||
|
#define BOOK3E_PAGESZ_128GB 27
|
||||||
|
#define BOOK3E_PAGESZ_256GB 28
|
||||||
|
#define BOOK3E_PAGESZ_512GB 29
|
||||||
|
#define BOOK3E_PAGESZ_1TB 30
|
||||||
|
#define BOOK3E_PAGESZ_2TB 31
|
||||||
|
|
||||||
#define MAS0_TLBSEL(x) ((x << 28) & 0x30000000)
|
#define MAS0_TLBSEL(x) ((x << 28) & 0x30000000)
|
||||||
#define MAS0_ESEL(x) ((x << 16) & 0x0FFF0000)
|
#define MAS0_ESEL(x) ((x << 16) & 0x0FFF0000)
|
||||||
|
|
@ -29,8 +45,9 @@
|
||||||
#define MAS1_VALID 0x80000000
|
#define MAS1_VALID 0x80000000
|
||||||
#define MAS1_IPROT 0x40000000
|
#define MAS1_IPROT 0x40000000
|
||||||
#define MAS1_TID(x) ((x << 16) & 0x3FFF0000)
|
#define MAS1_TID(x) ((x << 16) & 0x3FFF0000)
|
||||||
|
#define MAS1_IND 0x00002000
|
||||||
#define MAS1_TS 0x00001000
|
#define MAS1_TS 0x00001000
|
||||||
#define MAS1_TSIZE(x) ((x << 8) & 0x00000F00)
|
#define MAS1_TSIZE(x) ((x << 7) & 0x00000F80)
|
||||||
|
|
||||||
#define MAS2_EPN 0xFFFFF000
|
#define MAS2_EPN 0xFFFFF000
|
||||||
#define MAS2_X0 0x00000040
|
#define MAS2_X0 0x00000040
|
||||||
|
|
@ -40,7 +57,7 @@
|
||||||
#define MAS2_M 0x00000004
|
#define MAS2_M 0x00000004
|
||||||
#define MAS2_G 0x00000002
|
#define MAS2_G 0x00000002
|
||||||
#define MAS2_E 0x00000001
|
#define MAS2_E 0x00000001
|
||||||
#define MAS2_EPN_MASK(size) (~0 << (2*(size) + 10))
|
#define MAS2_EPN_MASK(size) (~0 << (size + 10))
|
||||||
#define MAS2_VAL(addr, size, flags) ((addr) & MAS2_EPN_MASK(size) | (flags))
|
#define MAS2_VAL(addr, size, flags) ((addr) & MAS2_EPN_MASK(size) | (flags))
|
||||||
|
|
||||||
#define MAS3_RPN 0xFFFFF000
|
#define MAS3_RPN 0xFFFFF000
|
||||||
|
|
@ -56,7 +73,7 @@
|
||||||
#define MAS3_SR 0x00000001
|
#define MAS3_SR 0x00000001
|
||||||
|
|
||||||
#define MAS4_TLBSELD(x) MAS0_TLBSEL(x)
|
#define MAS4_TLBSELD(x) MAS0_TLBSEL(x)
|
||||||
#define MAS4_TIDDSEL 0x000F0000
|
#define MAS4_INDD 0x00008000
|
||||||
#define MAS4_TSIZED(x) MAS1_TSIZE(x)
|
#define MAS4_TSIZED(x) MAS1_TSIZE(x)
|
||||||
#define MAS4_X0D 0x00000040
|
#define MAS4_X0D 0x00000040
|
||||||
#define MAS4_X1D 0x00000020
|
#define MAS4_X1D 0x00000020
|
||||||
|
|
@ -68,6 +85,7 @@
|
||||||
|
|
||||||
#define MAS6_SPID0 0x3FFF0000
|
#define MAS6_SPID0 0x3FFF0000
|
||||||
#define MAS6_SPID1 0x00007FFE
|
#define MAS6_SPID1 0x00007FFE
|
||||||
|
#define MAS6_ISIZE(x) MAS1_TSIZE(x)
|
||||||
#define MAS6_SAS 0x00000001
|
#define MAS6_SAS 0x00000001
|
||||||
#define MAS6_SPID MAS6_SPID0
|
#define MAS6_SPID MAS6_SPID0
|
||||||
|
|
||||||
|
|
@ -84,4 +102,4 @@ typedef struct {
|
||||||
} mm_context_t;
|
} mm_context_t;
|
||||||
#endif /* !__ASSEMBLY__ */
|
#endif /* !__ASSEMBLY__ */
|
||||||
|
|
||||||
#endif /* _ASM_POWERPC_MMU_FSL_BOOKE_H_ */
|
#endif /* _ASM_POWERPC_MMU_BOOK3E_H_ */
|
||||||
|
|
@ -284,8 +284,6 @@ extern void add_gpage(unsigned long addr, unsigned long page_size,
|
||||||
unsigned long number_of_pages);
|
unsigned long number_of_pages);
|
||||||
extern void demote_segment_4k(struct mm_struct *mm, unsigned long addr);
|
extern void demote_segment_4k(struct mm_struct *mm, unsigned long addr);
|
||||||
|
|
||||||
extern void htab_initialize(void);
|
|
||||||
extern void htab_initialize_secondary(void);
|
|
||||||
extern void hpte_init_native(void);
|
extern void hpte_init_native(void);
|
||||||
extern void hpte_init_lpar(void);
|
extern void hpte_init_lpar(void);
|
||||||
extern void hpte_init_iSeries(void);
|
extern void hpte_init_iSeries(void);
|
||||||
|
|
|
||||||
|
|
@ -36,9 +36,9 @@
|
||||||
*/
|
*/
|
||||||
#define MMU_FTR_USE_TLBIVAX_BCAST ASM_CONST(0x00040000)
|
#define MMU_FTR_USE_TLBIVAX_BCAST ASM_CONST(0x00040000)
|
||||||
|
|
||||||
/* Enable use of tlbilx invalidate-by-PID variant.
|
/* Enable use of tlbilx invalidate instructions.
|
||||||
*/
|
*/
|
||||||
#define MMU_FTR_USE_TLBILX_PID ASM_CONST(0x00080000)
|
#define MMU_FTR_USE_TLBILX ASM_CONST(0x00080000)
|
||||||
|
|
||||||
/* This indicates that the processor cannot handle multiple outstanding
|
/* This indicates that the processor cannot handle multiple outstanding
|
||||||
* broadcast tlbivax or tlbsync. This makes the code use a spinlock
|
* broadcast tlbivax or tlbsync. This makes the code use a spinlock
|
||||||
|
|
@ -46,6 +46,12 @@
|
||||||
*/
|
*/
|
||||||
#define MMU_FTR_LOCK_BCAST_INVAL ASM_CONST(0x00100000)
|
#define MMU_FTR_LOCK_BCAST_INVAL ASM_CONST(0x00100000)
|
||||||
|
|
||||||
|
/* This indicates that the processor doesn't handle way selection
|
||||||
|
* properly and needs SW to track and update the LRU state. This
|
||||||
|
* is specific to an errata on e300c2/c3/c4 class parts
|
||||||
|
*/
|
||||||
|
#define MMU_FTR_NEED_DTLB_SW_LRU ASM_CONST(0x00200000)
|
||||||
|
|
||||||
#ifndef __ASSEMBLY__
|
#ifndef __ASSEMBLY__
|
||||||
#include <asm/cputable.h>
|
#include <asm/cputable.h>
|
||||||
|
|
||||||
|
|
@ -56,6 +62,10 @@ static inline int mmu_has_feature(unsigned long feature)
|
||||||
|
|
||||||
extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup;
|
extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup;
|
||||||
|
|
||||||
|
/* MMU initialization (64-bit only fo now) */
|
||||||
|
extern void early_init_mmu(void);
|
||||||
|
extern void early_init_mmu_secondary(void);
|
||||||
|
|
||||||
#endif /* !__ASSEMBLY__ */
|
#endif /* !__ASSEMBLY__ */
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -71,9 +81,9 @@ extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup;
|
||||||
#elif defined(CONFIG_44x)
|
#elif defined(CONFIG_44x)
|
||||||
/* 44x-style software loaded TLB */
|
/* 44x-style software loaded TLB */
|
||||||
# include <asm/mmu-44x.h>
|
# include <asm/mmu-44x.h>
|
||||||
#elif defined(CONFIG_FSL_BOOKE)
|
#elif defined(CONFIG_PPC_BOOK3E_MMU)
|
||||||
/* Freescale Book-E software loaded TLB */
|
/* Freescale Book-E software loaded TLB or Book-3e (ISA 2.06+) MMU */
|
||||||
# include <asm/mmu-fsl-booke.h>
|
# include <asm/mmu-book3e.h>
|
||||||
#elif defined (CONFIG_PPC_8xx)
|
#elif defined (CONFIG_PPC_8xx)
|
||||||
/* Motorola/Freescale 8xx software loaded TLB */
|
/* Motorola/Freescale 8xx software loaded TLB */
|
||||||
# include <asm/mmu-8xx.h>
|
# include <asm/mmu-8xx.h>
|
||||||
|
|
|
||||||
|
|
@ -31,7 +31,7 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
|
||||||
struct task_struct *tsk)
|
struct task_struct *tsk)
|
||||||
{
|
{
|
||||||
/* Mark this context has been used on the new CPU */
|
/* Mark this context has been used on the new CPU */
|
||||||
cpu_set(smp_processor_id(), next->cpu_vm_mask);
|
cpumask_set_cpu(smp_processor_id(), mm_cpumask(next));
|
||||||
|
|
||||||
/* 32-bit keeps track of the current PGDIR in the thread struct */
|
/* 32-bit keeps track of the current PGDIR in the thread struct */
|
||||||
#ifdef CONFIG_PPC32
|
#ifdef CONFIG_PPC32
|
||||||
|
|
|
||||||
|
|
@ -273,6 +273,7 @@ extern void mpc5200_setup_xlb_arbiter(void);
|
||||||
extern void mpc52xx_declare_of_platform_devices(void);
|
extern void mpc52xx_declare_of_platform_devices(void);
|
||||||
extern void mpc52xx_map_common_devices(void);
|
extern void mpc52xx_map_common_devices(void);
|
||||||
extern int mpc52xx_set_psc_clkdiv(int psc_id, int clkdiv);
|
extern int mpc52xx_set_psc_clkdiv(int psc_id, int clkdiv);
|
||||||
|
extern unsigned int mpc52xx_get_xtal_freq(struct device_node *node);
|
||||||
extern void mpc52xx_restart(char *cmd);
|
extern void mpc52xx_restart(char *cmd);
|
||||||
|
|
||||||
/* mpc52xx_pic.c */
|
/* mpc52xx_pic.c */
|
||||||
|
|
|
||||||
|
|
@ -19,12 +19,14 @@
|
||||||
#include <asm/kdump.h>
|
#include <asm/kdump.h>
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* On regular PPC32 page size is 4K (but we support 4K/16K/64K pages
|
* On regular PPC32 page size is 4K (but we support 4K/16K/64K/256K pages
|
||||||
* on PPC44x). For PPC64 we support either 4K or 64K software
|
* on PPC44x). For PPC64 we support either 4K or 64K software
|
||||||
* page size. When using 64K pages however, whether we are really supporting
|
* page size. When using 64K pages however, whether we are really supporting
|
||||||
* 64K pages in HW or not is irrelevant to those definitions.
|
* 64K pages in HW or not is irrelevant to those definitions.
|
||||||
*/
|
*/
|
||||||
#if defined(CONFIG_PPC_64K_PAGES)
|
#if defined(CONFIG_PPC_256K_PAGES)
|
||||||
|
#define PAGE_SHIFT 18
|
||||||
|
#elif defined(CONFIG_PPC_64K_PAGES)
|
||||||
#define PAGE_SHIFT 16
|
#define PAGE_SHIFT 16
|
||||||
#elif defined(CONFIG_PPC_16K_PAGES)
|
#elif defined(CONFIG_PPC_16K_PAGES)
|
||||||
#define PAGE_SHIFT 14
|
#define PAGE_SHIFT 14
|
||||||
|
|
|
||||||
|
|
@ -19,7 +19,11 @@
|
||||||
#define PTE_FLAGS_OFFSET 0
|
#define PTE_FLAGS_OFFSET 0
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#ifdef CONFIG_PPC_256K_PAGES
|
||||||
|
#define PTE_SHIFT (PAGE_SHIFT - PTE_T_LOG2 - 2) /* 1/4 of a page */
|
||||||
|
#else
|
||||||
#define PTE_SHIFT (PAGE_SHIFT - PTE_T_LOG2) /* full page */
|
#define PTE_SHIFT (PAGE_SHIFT - PTE_T_LOG2) /* full page */
|
||||||
|
#endif
|
||||||
|
|
||||||
#ifndef __ASSEMBLY__
|
#ifndef __ASSEMBLY__
|
||||||
/*
|
/*
|
||||||
|
|
|
||||||
|
|
@ -18,55 +18,6 @@ extern int icache_44x_need_flush;
|
||||||
|
|
||||||
#endif /* __ASSEMBLY__ */
|
#endif /* __ASSEMBLY__ */
|
||||||
|
|
||||||
/*
|
|
||||||
* The PowerPC MMU uses a hash table containing PTEs, together with
|
|
||||||
* a set of 16 segment registers (on 32-bit implementations), to define
|
|
||||||
* the virtual to physical address mapping.
|
|
||||||
*
|
|
||||||
* We use the hash table as an extended TLB, i.e. a cache of currently
|
|
||||||
* active mappings. We maintain a two-level page table tree, much
|
|
||||||
* like that used by the i386, for the sake of the Linux memory
|
|
||||||
* management code. Low-level assembler code in hashtable.S
|
|
||||||
* (procedure hash_page) is responsible for extracting ptes from the
|
|
||||||
* tree and putting them into the hash table when necessary, and
|
|
||||||
* updating the accessed and modified bits in the page table tree.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* The PowerPC MPC8xx uses a TLB with hardware assisted, software tablewalk.
|
|
||||||
* We also use the two level tables, but we can put the real bits in them
|
|
||||||
* needed for the TLB and tablewalk. These definitions require Mx_CTR.PPM = 0,
|
|
||||||
* Mx_CTR.PPCS = 0, and MD_CTR.TWAM = 1. The level 2 descriptor has
|
|
||||||
* additional page protection (when Mx_CTR.PPCS = 1) that allows TLB hit
|
|
||||||
* based upon user/super access. The TLB does not have accessed nor write
|
|
||||||
* protect. We assume that if the TLB get loaded with an entry it is
|
|
||||||
* accessed, and overload the changed bit for write protect. We use
|
|
||||||
* two bits in the software pte that are supposed to be set to zero in
|
|
||||||
* the TLB entry (24 and 25) for these indicators. Although the level 1
|
|
||||||
* descriptor contains the guarded and writethrough/copyback bits, we can
|
|
||||||
* set these at the page level since they get copied from the Mx_TWC
|
|
||||||
* register when the TLB entry is loaded. We will use bit 27 for guard, since
|
|
||||||
* that is where it exists in the MD_TWC, and bit 26 for writethrough.
|
|
||||||
* These will get masked from the level 2 descriptor at TLB load time, and
|
|
||||||
* copied to the MD_TWC before it gets loaded.
|
|
||||||
* Large page sizes added. We currently support two sizes, 4K and 8M.
|
|
||||||
* This also allows a TLB hander optimization because we can directly
|
|
||||||
* load the PMD into MD_TWC. The 8M pages are only used for kernel
|
|
||||||
* mapping of well known areas. The PMD (PGD) entries contain control
|
|
||||||
* flags in addition to the address, so care must be taken that the
|
|
||||||
* software no longer assumes these are only pointers.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* At present, all PowerPC 400-class processors share a similar TLB
|
|
||||||
* architecture. The instruction and data sides share a unified,
|
|
||||||
* 64-entry, fully-associative TLB which is maintained totally under
|
|
||||||
* software control. In addition, the instruction side has a
|
|
||||||
* hardware-managed, 4-entry, fully-associative TLB which serves as a
|
|
||||||
* first level to the shared TLB. These two TLBs are known as the UTLB
|
|
||||||
* and ITLB, respectively (see "mmu.h" for definitions).
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* The normal case is that PTEs are 32-bits and we have a 1-page
|
* The normal case is that PTEs are 32-bits and we have a 1-page
|
||||||
* 1024-entry pgdir pointing to 1-page 1024-entry PTE pages. -- paulus
|
* 1024-entry pgdir pointing to 1-page 1024-entry PTE pages. -- paulus
|
||||||
|
|
@ -135,409 +86,22 @@ extern int icache_44x_need_flush;
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#if defined(CONFIG_40x)
|
#if defined(CONFIG_40x)
|
||||||
|
#include <asm/pte-40x.h>
|
||||||
/* There are several potential gotchas here. The 40x hardware TLBLO
|
|
||||||
field looks like this:
|
|
||||||
|
|
||||||
0 1 2 3 4 ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31
|
|
||||||
RPN..................... 0 0 EX WR ZSEL....... W I M G
|
|
||||||
|
|
||||||
Where possible we make the Linux PTE bits match up with this
|
|
||||||
|
|
||||||
- bits 20 and 21 must be cleared, because we use 4k pages (40x can
|
|
||||||
support down to 1k pages), this is done in the TLBMiss exception
|
|
||||||
handler.
|
|
||||||
- We use only zones 0 (for kernel pages) and 1 (for user pages)
|
|
||||||
of the 16 available. Bit 24-26 of the TLB are cleared in the TLB
|
|
||||||
miss handler. Bit 27 is PAGE_USER, thus selecting the correct
|
|
||||||
zone.
|
|
||||||
- PRESENT *must* be in the bottom two bits because swap cache
|
|
||||||
entries use the top 30 bits. Because 40x doesn't support SMP
|
|
||||||
anyway, M is irrelevant so we borrow it for PAGE_PRESENT. Bit 30
|
|
||||||
is cleared in the TLB miss handler before the TLB entry is loaded.
|
|
||||||
- All other bits of the PTE are loaded into TLBLO without
|
|
||||||
modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for
|
|
||||||
software PTE bits. We actually use use bits 21, 24, 25, and
|
|
||||||
30 respectively for the software bits: ACCESSED, DIRTY, RW, and
|
|
||||||
PRESENT.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Definitions for 40x embedded chips. */
|
|
||||||
#define _PAGE_GUARDED 0x001 /* G: page is guarded from prefetch */
|
|
||||||
#define _PAGE_FILE 0x001 /* when !present: nonlinear file mapping */
|
|
||||||
#define _PAGE_PRESENT 0x002 /* software: PTE contains a translation */
|
|
||||||
#define _PAGE_NO_CACHE 0x004 /* I: caching is inhibited */
|
|
||||||
#define _PAGE_WRITETHRU 0x008 /* W: caching is write-through */
|
|
||||||
#define _PAGE_USER 0x010 /* matches one of the zone permission bits */
|
|
||||||
#define _PAGE_RW 0x040 /* software: Writes permitted */
|
|
||||||
#define _PAGE_DIRTY 0x080 /* software: dirty page */
|
|
||||||
#define _PAGE_HWWRITE 0x100 /* hardware: Dirty & RW, set in exception */
|
|
||||||
#define _PAGE_HWEXEC 0x200 /* hardware: EX permission */
|
|
||||||
#define _PAGE_ACCESSED 0x400 /* software: R: page referenced */
|
|
||||||
|
|
||||||
#define _PMD_PRESENT 0x400 /* PMD points to page of PTEs */
|
|
||||||
#define _PMD_BAD 0x802
|
|
||||||
#define _PMD_SIZE 0x0e0 /* size field, != 0 for large-page PMD entry */
|
|
||||||
#define _PMD_SIZE_4M 0x0c0
|
|
||||||
#define _PMD_SIZE_16M 0x0e0
|
|
||||||
#define PMD_PAGE_SIZE(pmdval) (1024 << (((pmdval) & _PMD_SIZE) >> 4))
|
|
||||||
|
|
||||||
/* Until my rework is finished, 40x still needs atomic PTE updates */
|
|
||||||
#define PTE_ATOMIC_UPDATES 1
|
|
||||||
|
|
||||||
#elif defined(CONFIG_44x)
|
#elif defined(CONFIG_44x)
|
||||||
/*
|
#include <asm/pte-44x.h>
|
||||||
* Definitions for PPC440
|
|
||||||
*
|
|
||||||
* Because of the 3 word TLB entries to support 36-bit addressing,
|
|
||||||
* the attribute are difficult to map in such a fashion that they
|
|
||||||
* are easily loaded during exception processing. I decided to
|
|
||||||
* organize the entry so the ERPN is the only portion in the
|
|
||||||
* upper word of the PTE and the attribute bits below are packed
|
|
||||||
* in as sensibly as they can be in the area below a 4KB page size
|
|
||||||
* oriented RPN. This at least makes it easy to load the RPN and
|
|
||||||
* ERPN fields in the TLB. -Matt
|
|
||||||
*
|
|
||||||
* Note that these bits preclude future use of a page size
|
|
||||||
* less than 4KB.
|
|
||||||
*
|
|
||||||
*
|
|
||||||
* PPC 440 core has following TLB attribute fields;
|
|
||||||
*
|
|
||||||
* TLB1:
|
|
||||||
* 0 1 2 3 4 ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
|
|
||||||
* RPN................................. - - - - - - ERPN.......
|
|
||||||
*
|
|
||||||
* TLB2:
|
|
||||||
* 0 1 2 3 4 ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
|
|
||||||
* - - - - - - U0 U1 U2 U3 W I M G E - UX UW UR SX SW SR
|
|
||||||
*
|
|
||||||
* Newer 440 cores (440x6 as used on AMCC 460EX/460GT) have additional
|
|
||||||
* TLB2 storage attibute fields. Those are:
|
|
||||||
*
|
|
||||||
* TLB2:
|
|
||||||
* 0...10 11 12 13 14 15 16...31
|
|
||||||
* no change WL1 IL1I IL1D IL2I IL2D no change
|
|
||||||
*
|
|
||||||
* There are some constrains and options, to decide mapping software bits
|
|
||||||
* into TLB entry.
|
|
||||||
*
|
|
||||||
* - PRESENT *must* be in the bottom three bits because swap cache
|
|
||||||
* entries use the top 29 bits for TLB2.
|
|
||||||
*
|
|
||||||
* - FILE *must* be in the bottom three bits because swap cache
|
|
||||||
* entries use the top 29 bits for TLB2.
|
|
||||||
*
|
|
||||||
* - CACHE COHERENT bit (M) has no effect on original PPC440 cores,
|
|
||||||
* because it doesn't support SMP. However, some later 460 variants
|
|
||||||
* have -some- form of SMP support and so I keep the bit there for
|
|
||||||
* future use
|
|
||||||
*
|
|
||||||
* With the PPC 44x Linux implementation, the 0-11th LSBs of the PTE are used
|
|
||||||
* for memory protection related functions (see PTE structure in
|
|
||||||
* include/asm-ppc/mmu.h). The _PAGE_XXX definitions in this file map to the
|
|
||||||
* above bits. Note that the bit values are CPU specific, not architecture
|
|
||||||
* specific.
|
|
||||||
*
|
|
||||||
* The kernel PTE entry holds an arch-dependent swp_entry structure under
|
|
||||||
* certain situations. In other words, in such situations some portion of
|
|
||||||
* the PTE bits are used as a swp_entry. In the PPC implementation, the
|
|
||||||
* 3-24th LSB are shared with swp_entry, however the 0-2nd three LSB still
|
|
||||||
* hold protection values. That means the three protection bits are
|
|
||||||
* reserved for both PTE and SWAP entry at the most significant three
|
|
||||||
* LSBs.
|
|
||||||
*
|
|
||||||
* There are three protection bits available for SWAP entry:
|
|
||||||
* _PAGE_PRESENT
|
|
||||||
* _PAGE_FILE
|
|
||||||
* _PAGE_HASHPTE (if HW has)
|
|
||||||
*
|
|
||||||
* So those three bits have to be inside of 0-2nd LSB of PTE.
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define _PAGE_PRESENT 0x00000001 /* S: PTE valid */
|
|
||||||
#define _PAGE_RW 0x00000002 /* S: Write permission */
|
|
||||||
#define _PAGE_FILE 0x00000004 /* S: nonlinear file mapping */
|
|
||||||
#define _PAGE_HWEXEC 0x00000004 /* H: Execute permission */
|
|
||||||
#define _PAGE_ACCESSED 0x00000008 /* S: Page referenced */
|
|
||||||
#define _PAGE_DIRTY 0x00000010 /* S: Page dirty */
|
|
||||||
#define _PAGE_SPECIAL 0x00000020 /* S: Special page */
|
|
||||||
#define _PAGE_USER 0x00000040 /* S: User page */
|
|
||||||
#define _PAGE_ENDIAN 0x00000080 /* H: E bit */
|
|
||||||
#define _PAGE_GUARDED 0x00000100 /* H: G bit */
|
|
||||||
#define _PAGE_COHERENT 0x00000200 /* H: M bit */
|
|
||||||
#define _PAGE_NO_CACHE 0x00000400 /* H: I bit */
|
|
||||||
#define _PAGE_WRITETHRU 0x00000800 /* H: W bit */
|
|
||||||
|
|
||||||
/* TODO: Add large page lowmem mapping support */
|
|
||||||
#define _PMD_PRESENT 0
|
|
||||||
#define _PMD_PRESENT_MASK (PAGE_MASK)
|
|
||||||
#define _PMD_BAD (~PAGE_MASK)
|
|
||||||
|
|
||||||
/* ERPN in a PTE never gets cleared, ignore it */
|
|
||||||
#define _PTE_NONE_MASK 0xffffffff00000000ULL
|
|
||||||
|
|
||||||
#define __HAVE_ARCH_PTE_SPECIAL
|
|
||||||
|
|
||||||
#elif defined(CONFIG_FSL_BOOKE)
|
#elif defined(CONFIG_FSL_BOOKE)
|
||||||
/*
|
#include <asm/pte-fsl-booke.h>
|
||||||
MMU Assist Register 3:
|
|
||||||
|
|
||||||
32 33 34 35 36 ... 50 51 52 53 54 55 56 57 58 59 60 61 62 63
|
|
||||||
RPN...................... 0 0 U0 U1 U2 U3 UX SX UW SW UR SR
|
|
||||||
|
|
||||||
- PRESENT *must* be in the bottom three bits because swap cache
|
|
||||||
entries use the top 29 bits.
|
|
||||||
|
|
||||||
- FILE *must* be in the bottom three bits because swap cache
|
|
||||||
entries use the top 29 bits.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Definitions for FSL Book-E Cores */
|
|
||||||
#define _PAGE_PRESENT 0x00001 /* S: PTE contains a translation */
|
|
||||||
#define _PAGE_USER 0x00002 /* S: User page (maps to UR) */
|
|
||||||
#define _PAGE_FILE 0x00002 /* S: when !present: nonlinear file mapping */
|
|
||||||
#define _PAGE_RW 0x00004 /* S: Write permission (SW) */
|
|
||||||
#define _PAGE_DIRTY 0x00008 /* S: Page dirty */
|
|
||||||
#define _PAGE_HWEXEC 0x00010 /* H: SX permission */
|
|
||||||
#define _PAGE_ACCESSED 0x00020 /* S: Page referenced */
|
|
||||||
|
|
||||||
#define _PAGE_ENDIAN 0x00040 /* H: E bit */
|
|
||||||
#define _PAGE_GUARDED 0x00080 /* H: G bit */
|
|
||||||
#define _PAGE_COHERENT 0x00100 /* H: M bit */
|
|
||||||
#define _PAGE_NO_CACHE 0x00200 /* H: I bit */
|
|
||||||
#define _PAGE_WRITETHRU 0x00400 /* H: W bit */
|
|
||||||
#define _PAGE_SPECIAL 0x00800 /* S: Special page */
|
|
||||||
|
|
||||||
#ifdef CONFIG_PTE_64BIT
|
|
||||||
/* ERPN in a PTE never gets cleared, ignore it */
|
|
||||||
#define _PTE_NONE_MASK 0xffffffffffff0000ULL
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#define _PMD_PRESENT 0
|
|
||||||
#define _PMD_PRESENT_MASK (PAGE_MASK)
|
|
||||||
#define _PMD_BAD (~PAGE_MASK)
|
|
||||||
|
|
||||||
#define __HAVE_ARCH_PTE_SPECIAL
|
|
||||||
|
|
||||||
#elif defined(CONFIG_8xx)
|
#elif defined(CONFIG_8xx)
|
||||||
/* Definitions for 8xx embedded chips. */
|
#include <asm/pte-8xx.h>
|
||||||
#define _PAGE_PRESENT 0x0001 /* Page is valid */
|
|
||||||
#define _PAGE_FILE 0x0002 /* when !present: nonlinear file mapping */
|
|
||||||
#define _PAGE_NO_CACHE 0x0002 /* I: cache inhibit */
|
|
||||||
#define _PAGE_SHARED 0x0004 /* No ASID (context) compare */
|
|
||||||
|
|
||||||
/* These five software bits must be masked out when the entry is loaded
|
|
||||||
* into the TLB.
|
|
||||||
*/
|
|
||||||
#define _PAGE_EXEC 0x0008 /* software: i-cache coherency required */
|
|
||||||
#define _PAGE_GUARDED 0x0010 /* software: guarded access */
|
|
||||||
#define _PAGE_DIRTY 0x0020 /* software: page changed */
|
|
||||||
#define _PAGE_RW 0x0040 /* software: user write access allowed */
|
|
||||||
#define _PAGE_ACCESSED 0x0080 /* software: page referenced */
|
|
||||||
|
|
||||||
/* Setting any bits in the nibble with the follow two controls will
|
|
||||||
* require a TLB exception handler change. It is assumed unused bits
|
|
||||||
* are always zero.
|
|
||||||
*/
|
|
||||||
#define _PAGE_HWWRITE 0x0100 /* h/w write enable: never set in Linux PTE */
|
|
||||||
#define _PAGE_USER 0x0800 /* One of the PP bits, the other is USER&~RW */
|
|
||||||
|
|
||||||
#define _PMD_PRESENT 0x0001
|
|
||||||
#define _PMD_BAD 0x0ff0
|
|
||||||
#define _PMD_PAGE_MASK 0x000c
|
|
||||||
#define _PMD_PAGE_8M 0x000c
|
|
||||||
|
|
||||||
#define _PTE_NONE_MASK _PAGE_ACCESSED
|
|
||||||
|
|
||||||
/* Until my rework is finished, 8xx still needs atomic PTE updates */
|
|
||||||
#define PTE_ATOMIC_UPDATES 1
|
|
||||||
|
|
||||||
#else /* CONFIG_6xx */
|
#else /* CONFIG_6xx */
|
||||||
/* Definitions for 60x, 740/750, etc. */
|
#include <asm/pte-hash32.h>
|
||||||
#define _PAGE_PRESENT 0x001 /* software: pte contains a translation */
|
|
||||||
#define _PAGE_HASHPTE 0x002 /* hash_page has made an HPTE for this pte */
|
|
||||||
#define _PAGE_FILE 0x004 /* when !present: nonlinear file mapping */
|
|
||||||
#define _PAGE_USER 0x004 /* usermode access allowed */
|
|
||||||
#define _PAGE_GUARDED 0x008 /* G: prohibit speculative access */
|
|
||||||
#define _PAGE_COHERENT 0x010 /* M: enforce memory coherence (SMP systems) */
|
|
||||||
#define _PAGE_NO_CACHE 0x020 /* I: cache inhibit */
|
|
||||||
#define _PAGE_WRITETHRU 0x040 /* W: cache write-through */
|
|
||||||
#define _PAGE_DIRTY 0x080 /* C: page changed */
|
|
||||||
#define _PAGE_ACCESSED 0x100 /* R: page referenced */
|
|
||||||
#define _PAGE_EXEC 0x200 /* software: i-cache coherency required */
|
|
||||||
#define _PAGE_RW 0x400 /* software: user write access allowed */
|
|
||||||
#define _PAGE_SPECIAL 0x800 /* software: Special page */
|
|
||||||
|
|
||||||
#ifdef CONFIG_PTE_64BIT
|
|
||||||
/* We never clear the high word of the pte */
|
|
||||||
#define _PTE_NONE_MASK (0xffffffff00000000ULL | _PAGE_HASHPTE)
|
|
||||||
#else
|
|
||||||
#define _PTE_NONE_MASK _PAGE_HASHPTE
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#define _PMD_PRESENT 0
|
/* And here we include common definitions */
|
||||||
#define _PMD_PRESENT_MASK (PAGE_MASK)
|
#include <asm/pte-common.h>
|
||||||
#define _PMD_BAD (~PAGE_MASK)
|
|
||||||
|
|
||||||
/* Hash table based platforms need atomic updates of the linux PTE */
|
|
||||||
#define PTE_ATOMIC_UPDATES 1
|
|
||||||
|
|
||||||
#define __HAVE_ARCH_PTE_SPECIAL
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Some bits are only used on some cpu families...
|
|
||||||
*/
|
|
||||||
#ifndef _PAGE_HASHPTE
|
|
||||||
#define _PAGE_HASHPTE 0
|
|
||||||
#endif
|
|
||||||
#ifndef _PTE_NONE_MASK
|
|
||||||
#define _PTE_NONE_MASK 0
|
|
||||||
#endif
|
|
||||||
#ifndef _PAGE_SHARED
|
|
||||||
#define _PAGE_SHARED 0
|
|
||||||
#endif
|
|
||||||
#ifndef _PAGE_HWWRITE
|
|
||||||
#define _PAGE_HWWRITE 0
|
|
||||||
#endif
|
|
||||||
#ifndef _PAGE_HWEXEC
|
|
||||||
#define _PAGE_HWEXEC 0
|
|
||||||
#endif
|
|
||||||
#ifndef _PAGE_EXEC
|
|
||||||
#define _PAGE_EXEC 0
|
|
||||||
#endif
|
|
||||||
#ifndef _PAGE_ENDIAN
|
|
||||||
#define _PAGE_ENDIAN 0
|
|
||||||
#endif
|
|
||||||
#ifndef _PAGE_COHERENT
|
|
||||||
#define _PAGE_COHERENT 0
|
|
||||||
#endif
|
|
||||||
#ifndef _PAGE_WRITETHRU
|
|
||||||
#define _PAGE_WRITETHRU 0
|
|
||||||
#endif
|
|
||||||
#ifndef _PAGE_SPECIAL
|
|
||||||
#define _PAGE_SPECIAL 0
|
|
||||||
#endif
|
|
||||||
#ifndef _PMD_PRESENT_MASK
|
|
||||||
#define _PMD_PRESENT_MASK _PMD_PRESENT
|
|
||||||
#endif
|
|
||||||
#ifndef _PMD_SIZE
|
|
||||||
#define _PMD_SIZE 0
|
|
||||||
#define PMD_PAGE_SIZE(pmd) bad_call_to_PMD_PAGE_SIZE()
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY | \
|
|
||||||
_PAGE_SPECIAL)
|
|
||||||
|
|
||||||
|
|
||||||
#define PAGE_PROT_BITS (_PAGE_GUARDED | _PAGE_COHERENT | _PAGE_NO_CACHE | \
|
|
||||||
_PAGE_WRITETHRU | _PAGE_ENDIAN | \
|
|
||||||
_PAGE_USER | _PAGE_ACCESSED | \
|
|
||||||
_PAGE_RW | _PAGE_HWWRITE | _PAGE_DIRTY | \
|
|
||||||
_PAGE_EXEC | _PAGE_HWEXEC)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* We define 2 sets of base prot bits, one for basic pages (ie,
|
|
||||||
* cacheable kernel and user pages) and one for non cacheable
|
|
||||||
* pages. We always set _PAGE_COHERENT when SMP is enabled or
|
|
||||||
* the processor might need it for DMA coherency.
|
|
||||||
*/
|
|
||||||
#if defined(CONFIG_SMP) || defined(CONFIG_PPC_STD_MMU)
|
|
||||||
#define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_COHERENT)
|
|
||||||
#else
|
|
||||||
#define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED)
|
|
||||||
#endif
|
|
||||||
#define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_NO_CACHE)
|
|
||||||
|
|
||||||
#define _PAGE_WRENABLE (_PAGE_RW | _PAGE_DIRTY | _PAGE_HWWRITE)
|
|
||||||
#define _PAGE_KERNEL (_PAGE_BASE | _PAGE_SHARED | _PAGE_WRENABLE)
|
|
||||||
#define _PAGE_KERNEL_NC (_PAGE_BASE_NC | _PAGE_SHARED | _PAGE_WRENABLE)
|
|
||||||
|
|
||||||
#ifdef CONFIG_PPC_STD_MMU
|
|
||||||
/* On standard PPC MMU, no user access implies kernel read/write access,
|
|
||||||
* so to write-protect kernel memory we must turn on user access */
|
|
||||||
#define _PAGE_KERNEL_RO (_PAGE_BASE | _PAGE_SHARED | _PAGE_USER)
|
|
||||||
#else
|
|
||||||
#define _PAGE_KERNEL_RO (_PAGE_BASE | _PAGE_SHARED)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#define _PAGE_IO (_PAGE_KERNEL_NC | _PAGE_GUARDED)
|
|
||||||
#define _PAGE_RAM (_PAGE_KERNEL | _PAGE_HWEXEC)
|
|
||||||
|
|
||||||
#if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) ||\
|
|
||||||
defined(CONFIG_KPROBES)
|
|
||||||
/* We want the debuggers to be able to set breakpoints anywhere, so
|
|
||||||
* don't write protect the kernel text */
|
|
||||||
#define _PAGE_RAM_TEXT _PAGE_RAM
|
|
||||||
#else
|
|
||||||
#define _PAGE_RAM_TEXT (_PAGE_KERNEL_RO | _PAGE_HWEXEC)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#define PAGE_NONE __pgprot(_PAGE_BASE)
|
|
||||||
#define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER)
|
|
||||||
#define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
|
|
||||||
#define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW)
|
|
||||||
#define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC)
|
|
||||||
#define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER)
|
|
||||||
#define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
|
|
||||||
|
|
||||||
#define PAGE_KERNEL __pgprot(_PAGE_RAM)
|
|
||||||
#define PAGE_KERNEL_NOCACHE __pgprot(_PAGE_IO)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* The PowerPC can only do execute protection on a segment (256MB) basis,
|
|
||||||
* not on a page basis. So we consider execute permission the same as read.
|
|
||||||
* Also, write permissions imply read permissions.
|
|
||||||
* This is the closest we can get..
|
|
||||||
*/
|
|
||||||
#define __P000 PAGE_NONE
|
|
||||||
#define __P001 PAGE_READONLY_X
|
|
||||||
#define __P010 PAGE_COPY
|
|
||||||
#define __P011 PAGE_COPY_X
|
|
||||||
#define __P100 PAGE_READONLY
|
|
||||||
#define __P101 PAGE_READONLY_X
|
|
||||||
#define __P110 PAGE_COPY
|
|
||||||
#define __P111 PAGE_COPY_X
|
|
||||||
|
|
||||||
#define __S000 PAGE_NONE
|
|
||||||
#define __S001 PAGE_READONLY_X
|
|
||||||
#define __S010 PAGE_SHARED
|
|
||||||
#define __S011 PAGE_SHARED_X
|
|
||||||
#define __S100 PAGE_READONLY
|
|
||||||
#define __S101 PAGE_READONLY_X
|
|
||||||
#define __S110 PAGE_SHARED
|
|
||||||
#define __S111 PAGE_SHARED_X
|
|
||||||
|
|
||||||
#ifndef __ASSEMBLY__
|
#ifndef __ASSEMBLY__
|
||||||
/* Make sure we get a link error if PMD_PAGE_SIZE is ever called on a
|
|
||||||
* kernel without large page PMD support */
|
|
||||||
extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Conversions between PTE values and page frame numbers.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* in some case we want to additionaly adjust where the pfn is in the pte to
|
|
||||||
* allow room for more flags */
|
|
||||||
#if defined(CONFIG_FSL_BOOKE) && defined(CONFIG_PTE_64BIT)
|
|
||||||
#define PFN_SHIFT_OFFSET (PAGE_SHIFT + 8)
|
|
||||||
#else
|
|
||||||
#define PFN_SHIFT_OFFSET (PAGE_SHIFT)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#define pte_pfn(x) (pte_val(x) >> PFN_SHIFT_OFFSET)
|
|
||||||
#define pte_page(x) pfn_to_page(pte_pfn(x))
|
|
||||||
|
|
||||||
#define pfn_pte(pfn, prot) __pte(((pte_basic_t)(pfn) << PFN_SHIFT_OFFSET) |\
|
|
||||||
pgprot_val(prot))
|
|
||||||
#define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot)
|
|
||||||
#endif /* __ASSEMBLY__ */
|
|
||||||
|
|
||||||
#define pte_none(pte) ((pte_val(pte) & ~_PTE_NONE_MASK) == 0)
|
|
||||||
#define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT)
|
|
||||||
#define pte_clear(mm, addr, ptep) \
|
#define pte_clear(mm, addr, ptep) \
|
||||||
do { pte_update(ptep, ~_PAGE_HASHPTE, 0); } while (0)
|
do { pte_update(ptep, ~_PAGE_HASHPTE, 0); } while (0)
|
||||||
|
|
||||||
|
|
@ -546,43 +110,6 @@ extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);
|
||||||
#define pmd_present(pmd) (pmd_val(pmd) & _PMD_PRESENT_MASK)
|
#define pmd_present(pmd) (pmd_val(pmd) & _PMD_PRESENT_MASK)
|
||||||
#define pmd_clear(pmdp) do { pmd_val(*(pmdp)) = 0; } while (0)
|
#define pmd_clear(pmdp) do { pmd_val(*(pmdp)) = 0; } while (0)
|
||||||
|
|
||||||
#ifndef __ASSEMBLY__
|
|
||||||
/*
|
|
||||||
* The following only work if pte_present() is true.
|
|
||||||
* Undefined behaviour if not..
|
|
||||||
*/
|
|
||||||
static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW; }
|
|
||||||
static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
|
|
||||||
static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
|
|
||||||
static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; }
|
|
||||||
static inline int pte_special(pte_t pte) { return pte_val(pte) & _PAGE_SPECIAL; }
|
|
||||||
|
|
||||||
static inline pte_t pte_wrprotect(pte_t pte) {
|
|
||||||
pte_val(pte) &= ~(_PAGE_RW | _PAGE_HWWRITE); return pte; }
|
|
||||||
static inline pte_t pte_mkclean(pte_t pte) {
|
|
||||||
pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HWWRITE); return pte; }
|
|
||||||
static inline pte_t pte_mkold(pte_t pte) {
|
|
||||||
pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
|
|
||||||
|
|
||||||
static inline pte_t pte_mkwrite(pte_t pte) {
|
|
||||||
pte_val(pte) |= _PAGE_RW; return pte; }
|
|
||||||
static inline pte_t pte_mkdirty(pte_t pte) {
|
|
||||||
pte_val(pte) |= _PAGE_DIRTY; return pte; }
|
|
||||||
static inline pte_t pte_mkyoung(pte_t pte) {
|
|
||||||
pte_val(pte) |= _PAGE_ACCESSED; return pte; }
|
|
||||||
static inline pte_t pte_mkspecial(pte_t pte) {
|
|
||||||
pte_val(pte) |= _PAGE_SPECIAL; return pte; }
|
|
||||||
static inline pgprot_t pte_pgprot(pte_t pte)
|
|
||||||
{
|
|
||||||
return __pgprot(pte_val(pte) & PAGE_PROT_BITS);
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
|
|
||||||
{
|
|
||||||
pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot);
|
|
||||||
return pte;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* When flushing the tlb entry for a page, we also need to flush the hash
|
* When flushing the tlb entry for a page, we also need to flush the hash
|
||||||
* table entry. flush_hash_pages is assembler (for speed) in hashtable.S.
|
* table entry. flush_hash_pages is assembler (for speed) in hashtable.S.
|
||||||
|
|
@ -599,11 +126,19 @@ extern void flush_hash_entry(struct mm_struct *mm, pte_t *ptep,
|
||||||
unsigned long address);
|
unsigned long address);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Atomic PTE updates.
|
* PTE updates. This function is called whenever an existing
|
||||||
|
* valid PTE is updated. This does -not- include set_pte_at()
|
||||||
|
* which nowadays only sets a new PTE.
|
||||||
*
|
*
|
||||||
* pte_update clears and sets bit atomically, and returns
|
* Depending on the type of MMU, we may need to use atomic updates
|
||||||
* the old pte value. In the 64-bit PTE case we lock around the
|
* and the PTE may be either 32 or 64 bit wide. In the later case,
|
||||||
* low PTE word since we expect ALL flag bits to be there
|
* when using atomic updates, only the low part of the PTE is
|
||||||
|
* accessed atomically.
|
||||||
|
*
|
||||||
|
* In addition, on 44x, we also maintain a global flag indicating
|
||||||
|
* that an executable user mapping was modified, which is needed
|
||||||
|
* to properly flush the virtually tagged instruction cache of
|
||||||
|
* those implementations.
|
||||||
*/
|
*/
|
||||||
#ifndef CONFIG_PTE_64BIT
|
#ifndef CONFIG_PTE_64BIT
|
||||||
static inline unsigned long pte_update(pte_t *p,
|
static inline unsigned long pte_update(pte_t *p,
|
||||||
|
|
@ -667,44 +202,6 @@ static inline unsigned long long pte_update(pte_t *p,
|
||||||
}
|
}
|
||||||
#endif /* CONFIG_PTE_64BIT */
|
#endif /* CONFIG_PTE_64BIT */
|
||||||
|
|
||||||
/*
|
|
||||||
* set_pte stores a linux PTE into the linux page table.
|
|
||||||
* On machines which use an MMU hash table we avoid changing the
|
|
||||||
* _PAGE_HASHPTE bit.
|
|
||||||
*/
|
|
||||||
|
|
||||||
static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
|
|
||||||
pte_t *ptep, pte_t pte)
|
|
||||||
{
|
|
||||||
#if (_PAGE_HASHPTE != 0) && defined(CONFIG_SMP) && !defined(CONFIG_PTE_64BIT)
|
|
||||||
pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte) & ~_PAGE_HASHPTE);
|
|
||||||
#elif defined(CONFIG_PTE_64BIT) && defined(CONFIG_SMP)
|
|
||||||
#if _PAGE_HASHPTE != 0
|
|
||||||
if (pte_val(*ptep) & _PAGE_HASHPTE)
|
|
||||||
flush_hash_entry(mm, ptep, addr);
|
|
||||||
#endif
|
|
||||||
__asm__ __volatile__("\
|
|
||||||
stw%U0%X0 %2,%0\n\
|
|
||||||
eieio\n\
|
|
||||||
stw%U0%X0 %L2,%1"
|
|
||||||
: "=m" (*ptep), "=m" (*((unsigned char *)ptep+4))
|
|
||||||
: "r" (pte) : "memory");
|
|
||||||
#else
|
|
||||||
*ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE)
|
|
||||||
| (pte_val(pte) & ~_PAGE_HASHPTE));
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
|
|
||||||
pte_t *ptep, pte_t pte)
|
|
||||||
{
|
|
||||||
#if defined(CONFIG_PTE_64BIT) && defined(CONFIG_SMP) && defined(CONFIG_DEBUG_VM)
|
|
||||||
WARN_ON(pte_present(*ptep));
|
|
||||||
#endif
|
|
||||||
__set_pte_at(mm, addr, ptep, pte);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* 2.6 calls this without flushing the TLB entry; this is wrong
|
* 2.6 calls this without flushing the TLB entry; this is wrong
|
||||||
* for our hash-based implementation, we fix that up here.
|
* for our hash-based implementation, we fix that up here.
|
||||||
|
|
@ -745,24 +242,14 @@ static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
|
static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry)
|
||||||
static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty)
|
|
||||||
{
|
{
|
||||||
unsigned long bits = pte_val(entry) &
|
unsigned long bits = pte_val(entry) &
|
||||||
(_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW);
|
(_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW |
|
||||||
|
_PAGE_HWEXEC | _PAGE_EXEC);
|
||||||
pte_update(ptep, 0, bits);
|
pte_update(ptep, 0, bits);
|
||||||
}
|
}
|
||||||
|
|
||||||
#define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
|
|
||||||
({ \
|
|
||||||
int __changed = !pte_same(*(__ptep), __entry); \
|
|
||||||
if (__changed) { \
|
|
||||||
__ptep_set_access_flags(__ptep, __entry, __dirty); \
|
|
||||||
flush_tlb_page_nohash(__vma, __address); \
|
|
||||||
} \
|
|
||||||
__changed; \
|
|
||||||
})
|
|
||||||
|
|
||||||
#define __HAVE_ARCH_PTE_SAME
|
#define __HAVE_ARCH_PTE_SAME
|
||||||
#define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0)
|
#define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0)
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,5 +1,5 @@
|
||||||
#ifndef _ASM_POWERPC_PGTABLE_4K_H
|
#ifndef _ASM_POWERPC_PGTABLE_PPC64_4K_H
|
||||||
#define _ASM_POWERPC_PGTABLE_4K_H
|
#define _ASM_POWERPC_PGTABLE_PPC64_4K_H
|
||||||
/*
|
/*
|
||||||
* Entries per page directory level. The PTE level must use a 64b record
|
* Entries per page directory level. The PTE level must use a 64b record
|
||||||
* for each page table entry. The PMD and PGD level use a 32b record for
|
* for each page table entry. The PMD and PGD level use a 32b record for
|
||||||
|
|
@ -40,28 +40,6 @@
|
||||||
#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
|
#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
|
||||||
#define PGDIR_MASK (~(PGDIR_SIZE-1))
|
#define PGDIR_MASK (~(PGDIR_SIZE-1))
|
||||||
|
|
||||||
/* PTE bits */
|
|
||||||
#define _PAGE_HASHPTE 0x0400 /* software: pte has an associated HPTE */
|
|
||||||
#define _PAGE_SECONDARY 0x8000 /* software: HPTE is in secondary group */
|
|
||||||
#define _PAGE_GROUP_IX 0x7000 /* software: HPTE index within group */
|
|
||||||
#define _PAGE_F_SECOND _PAGE_SECONDARY
|
|
||||||
#define _PAGE_F_GIX _PAGE_GROUP_IX
|
|
||||||
#define _PAGE_SPECIAL 0x10000 /* software: special page */
|
|
||||||
#define __HAVE_ARCH_PTE_SPECIAL
|
|
||||||
|
|
||||||
/* PTE flags to conserve for HPTE identification */
|
|
||||||
#define _PAGE_HPTEFLAGS (_PAGE_BUSY | _PAGE_HASHPTE | \
|
|
||||||
_PAGE_SECONDARY | _PAGE_GROUP_IX)
|
|
||||||
|
|
||||||
/* There is no 4K PFN hack on 4K pages */
|
|
||||||
#define _PAGE_4K_PFN 0
|
|
||||||
|
|
||||||
/* PAGE_MASK gives the right answer below, but only by accident */
|
|
||||||
/* It should be preserving the high 48 bits and then specifically */
|
|
||||||
/* preserving _PAGE_SECONDARY | _PAGE_GROUP_IX */
|
|
||||||
#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY | \
|
|
||||||
_PAGE_HPTEFLAGS | _PAGE_SPECIAL)
|
|
||||||
|
|
||||||
/* Bits to mask out from a PMD to get to the PTE page */
|
/* Bits to mask out from a PMD to get to the PTE page */
|
||||||
#define PMD_MASKED_BITS 0
|
#define PMD_MASKED_BITS 0
|
||||||
/* Bits to mask out from a PUD to get to the PMD page */
|
/* Bits to mask out from a PUD to get to the PMD page */
|
||||||
|
|
@ -69,30 +47,6 @@
|
||||||
/* Bits to mask out from a PGD to get to the PUD page */
|
/* Bits to mask out from a PGD to get to the PUD page */
|
||||||
#define PGD_MASKED_BITS 0
|
#define PGD_MASKED_BITS 0
|
||||||
|
|
||||||
/* shift to put page number into pte */
|
|
||||||
#define PTE_RPN_SHIFT (17)
|
|
||||||
|
|
||||||
#ifdef STRICT_MM_TYPECHECKS
|
|
||||||
#define __real_pte(e,p) ((real_pte_t){(e)})
|
|
||||||
#define __rpte_to_pte(r) ((r).pte)
|
|
||||||
#else
|
|
||||||
#define __real_pte(e,p) (e)
|
|
||||||
#define __rpte_to_pte(r) (__pte(r))
|
|
||||||
#endif
|
|
||||||
#define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> 12)
|
|
||||||
|
|
||||||
#define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \
|
|
||||||
do { \
|
|
||||||
index = 0; \
|
|
||||||
shift = mmu_psize_defs[psize].shift; \
|
|
||||||
|
|
||||||
#define pte_iterate_hashed_end() } while(0)
|
|
||||||
|
|
||||||
#ifdef CONFIG_PPC_HAS_HASH_64K
|
|
||||||
#define pte_pagesize_index(mm, addr, pte) get_slice_psize(mm, addr)
|
|
||||||
#else
|
|
||||||
#define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* 4-level page tables related bits
|
* 4-level page tables related bits
|
||||||
|
|
@ -112,6 +66,9 @@
|
||||||
#define pud_ERROR(e) \
|
#define pud_ERROR(e) \
|
||||||
printk("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e))
|
printk("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e))
|
||||||
|
|
||||||
|
/*
|
||||||
|
* On all 4K setups, remap_4k_pfn() equates to remap_pfn_range() */
|
||||||
#define remap_4k_pfn(vma, addr, pfn, prot) \
|
#define remap_4k_pfn(vma, addr, pfn, prot) \
|
||||||
remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE, (prot))
|
remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE, (prot))
|
||||||
#endif /* _ASM_POWERPC_PGTABLE_4K_H */
|
|
||||||
|
#endif /* _ASM_POWERPC_PGTABLE_PPC64_4K_H */
|
||||||
|
|
@ -0,0 +1,42 @@
|
||||||
|
#ifndef _ASM_POWERPC_PGTABLE_PPC64_64K_H
|
||||||
|
#define _ASM_POWERPC_PGTABLE_PPC64_64K_H
|
||||||
|
|
||||||
|
#include <asm-generic/pgtable-nopud.h>
|
||||||
|
|
||||||
|
|
||||||
|
#define PTE_INDEX_SIZE 12
|
||||||
|
#define PMD_INDEX_SIZE 12
|
||||||
|
#define PUD_INDEX_SIZE 0
|
||||||
|
#define PGD_INDEX_SIZE 4
|
||||||
|
|
||||||
|
#ifndef __ASSEMBLY__
|
||||||
|
|
||||||
|
#define PTE_TABLE_SIZE (sizeof(real_pte_t) << PTE_INDEX_SIZE)
|
||||||
|
#define PMD_TABLE_SIZE (sizeof(pmd_t) << PMD_INDEX_SIZE)
|
||||||
|
#define PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE)
|
||||||
|
|
||||||
|
#define PTRS_PER_PTE (1 << PTE_INDEX_SIZE)
|
||||||
|
#define PTRS_PER_PMD (1 << PMD_INDEX_SIZE)
|
||||||
|
#define PTRS_PER_PGD (1 << PGD_INDEX_SIZE)
|
||||||
|
|
||||||
|
/* With 4k base page size, hugepage PTEs go at the PMD level */
|
||||||
|
#define MIN_HUGEPTE_SHIFT PAGE_SHIFT
|
||||||
|
|
||||||
|
/* PMD_SHIFT determines what a second-level page table entry can map */
|
||||||
|
#define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE)
|
||||||
|
#define PMD_SIZE (1UL << PMD_SHIFT)
|
||||||
|
#define PMD_MASK (~(PMD_SIZE-1))
|
||||||
|
|
||||||
|
/* PGDIR_SHIFT determines what a third-level page table entry can map */
|
||||||
|
#define PGDIR_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE)
|
||||||
|
#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
|
||||||
|
#define PGDIR_MASK (~(PGDIR_SIZE-1))
|
||||||
|
|
||||||
|
#endif /* __ASSEMBLY__ */
|
||||||
|
|
||||||
|
/* Bits to mask out from a PMD to get to the PTE page */
|
||||||
|
#define PMD_MASKED_BITS 0x1ff
|
||||||
|
/* Bits to mask out from a PGD/PUD to get to the PMD page */
|
||||||
|
#define PUD_MASKED_BITS 0x1ff
|
||||||
|
|
||||||
|
#endif /* _ASM_POWERPC_PGTABLE_PPC64_64K_H */
|
||||||
|
|
@ -11,9 +11,9 @@
|
||||||
#endif /* __ASSEMBLY__ */
|
#endif /* __ASSEMBLY__ */
|
||||||
|
|
||||||
#ifdef CONFIG_PPC_64K_PAGES
|
#ifdef CONFIG_PPC_64K_PAGES
|
||||||
#include <asm/pgtable-64k.h>
|
#include <asm/pgtable-ppc64-64k.h>
|
||||||
#else
|
#else
|
||||||
#include <asm/pgtable-4k.h>
|
#include <asm/pgtable-ppc64-4k.h>
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#define FIRST_USER_ADDRESS 0
|
#define FIRST_USER_ADDRESS 0
|
||||||
|
|
@ -25,6 +25,8 @@
|
||||||
PUD_INDEX_SIZE + PGD_INDEX_SIZE + PAGE_SHIFT)
|
PUD_INDEX_SIZE + PGD_INDEX_SIZE + PAGE_SHIFT)
|
||||||
#define PGTABLE_RANGE (ASM_CONST(1) << PGTABLE_EADDR_SIZE)
|
#define PGTABLE_RANGE (ASM_CONST(1) << PGTABLE_EADDR_SIZE)
|
||||||
|
|
||||||
|
|
||||||
|
/* Some sanity checking */
|
||||||
#if TASK_SIZE_USER64 > PGTABLE_RANGE
|
#if TASK_SIZE_USER64 > PGTABLE_RANGE
|
||||||
#error TASK_SIZE_USER64 exceeds pagetable range
|
#error TASK_SIZE_USER64 exceeds pagetable range
|
||||||
#endif
|
#endif
|
||||||
|
|
@ -33,7 +35,6 @@
|
||||||
#error TASK_SIZE_USER64 exceeds user VSID range
|
#error TASK_SIZE_USER64 exceeds user VSID range
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Define the address range of the vmalloc VM area.
|
* Define the address range of the vmalloc VM area.
|
||||||
*/
|
*/
|
||||||
|
|
@ -76,82 +77,11 @@
|
||||||
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Common bits in a linux-style PTE. These match the bits in the
|
* Include the PTE bits definitions
|
||||||
* (hardware-defined) PowerPC PTE as closely as possible. Additional
|
|
||||||
* bits may be defined in pgtable-*.h
|
|
||||||
*/
|
*/
|
||||||
#define _PAGE_PRESENT 0x0001 /* software: pte contains a translation */
|
#include <asm/pte-hash64.h>
|
||||||
#define _PAGE_USER 0x0002 /* matches one of the PP bits */
|
#include <asm/pte-common.h>
|
||||||
#define _PAGE_FILE 0x0002 /* (!present only) software: pte holds file offset */
|
|
||||||
#define _PAGE_EXEC 0x0004 /* No execute on POWER4 and newer (we invert) */
|
|
||||||
#define _PAGE_GUARDED 0x0008
|
|
||||||
#define _PAGE_COHERENT 0x0010 /* M: enforce memory coherence (SMP systems) */
|
|
||||||
#define _PAGE_NO_CACHE 0x0020 /* I: cache inhibit */
|
|
||||||
#define _PAGE_WRITETHRU 0x0040 /* W: cache write-through */
|
|
||||||
#define _PAGE_DIRTY 0x0080 /* C: page changed */
|
|
||||||
#define _PAGE_ACCESSED 0x0100 /* R: page referenced */
|
|
||||||
#define _PAGE_RW 0x0200 /* software: user write access allowed */
|
|
||||||
#define _PAGE_BUSY 0x0800 /* software: PTE & hash are busy */
|
|
||||||
|
|
||||||
/* Strong Access Ordering */
|
|
||||||
#define _PAGE_SAO (_PAGE_WRITETHRU | _PAGE_NO_CACHE | _PAGE_COHERENT)
|
|
||||||
|
|
||||||
#define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_COHERENT)
|
|
||||||
|
|
||||||
#define _PAGE_WRENABLE (_PAGE_RW | _PAGE_DIRTY)
|
|
||||||
|
|
||||||
/* __pgprot defined in arch/powerpc/include/asm/page.h */
|
|
||||||
#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED)
|
|
||||||
|
|
||||||
#define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_USER)
|
|
||||||
#define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_USER | _PAGE_EXEC)
|
|
||||||
#define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER)
|
|
||||||
#define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
|
|
||||||
#define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER)
|
|
||||||
#define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
|
|
||||||
#define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_WRENABLE)
|
|
||||||
#define PAGE_KERNEL_CI __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
|
|
||||||
_PAGE_WRENABLE | _PAGE_NO_CACHE | _PAGE_GUARDED)
|
|
||||||
#define PAGE_KERNEL_EXEC __pgprot(_PAGE_BASE | _PAGE_WRENABLE | _PAGE_EXEC)
|
|
||||||
|
|
||||||
#define PAGE_AGP __pgprot(_PAGE_BASE | _PAGE_WRENABLE | _PAGE_NO_CACHE)
|
|
||||||
#define HAVE_PAGE_AGP
|
|
||||||
|
|
||||||
#define PAGE_PROT_BITS (_PAGE_GUARDED | _PAGE_COHERENT | \
|
|
||||||
_PAGE_NO_CACHE | _PAGE_WRITETHRU | \
|
|
||||||
_PAGE_4K_PFN | _PAGE_RW | _PAGE_USER | \
|
|
||||||
_PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_EXEC)
|
|
||||||
/* PTEIDX nibble */
|
|
||||||
#define _PTEIDX_SECONDARY 0x8
|
|
||||||
#define _PTEIDX_GROUP_IX 0x7
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* POWER4 and newer have per page execute protection, older chips can only
|
|
||||||
* do this on a segment (256MB) basis.
|
|
||||||
*
|
|
||||||
* Also, write permissions imply read permissions.
|
|
||||||
* This is the closest we can get..
|
|
||||||
*
|
|
||||||
* Note due to the way vm flags are laid out, the bits are XWR
|
|
||||||
*/
|
|
||||||
#define __P000 PAGE_NONE
|
|
||||||
#define __P001 PAGE_READONLY
|
|
||||||
#define __P010 PAGE_COPY
|
|
||||||
#define __P011 PAGE_COPY
|
|
||||||
#define __P100 PAGE_READONLY_X
|
|
||||||
#define __P101 PAGE_READONLY_X
|
|
||||||
#define __P110 PAGE_COPY_X
|
|
||||||
#define __P111 PAGE_COPY_X
|
|
||||||
|
|
||||||
#define __S000 PAGE_NONE
|
|
||||||
#define __S001 PAGE_READONLY
|
|
||||||
#define __S010 PAGE_SHARED
|
|
||||||
#define __S011 PAGE_SHARED
|
|
||||||
#define __S100 PAGE_READONLY_X
|
|
||||||
#define __S101 PAGE_READONLY_X
|
|
||||||
#define __S110 PAGE_SHARED_X
|
|
||||||
#define __S111 PAGE_SHARED_X
|
|
||||||
|
|
||||||
#ifdef CONFIG_PPC_MM_SLICES
|
#ifdef CONFIG_PPC_MM_SLICES
|
||||||
#define HAVE_ARCH_UNMAPPED_AREA
|
#define HAVE_ARCH_UNMAPPED_AREA
|
||||||
|
|
@ -161,33 +91,39 @@
|
||||||
#ifndef __ASSEMBLY__
|
#ifndef __ASSEMBLY__
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Conversion functions: convert a page and protection to a page entry,
|
* This is the default implementation of various PTE accessors, it's
|
||||||
* and a page entry and page directory to the page they refer to.
|
* used in all cases except Book3S with 64K pages where we have a
|
||||||
*
|
* concept of sub-pages
|
||||||
* mk_pte takes a (struct page *) as input
|
|
||||||
*/
|
*/
|
||||||
#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
|
#ifndef __real_pte
|
||||||
|
|
||||||
static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
|
#ifdef STRICT_MM_TYPECHECKS
|
||||||
{
|
#define __real_pte(e,p) ((real_pte_t){(e)})
|
||||||
pte_t pte;
|
#define __rpte_to_pte(r) ((r).pte)
|
||||||
|
#else
|
||||||
|
#define __real_pte(e,p) (e)
|
||||||
|
#define __rpte_to_pte(r) (__pte(r))
|
||||||
|
#endif
|
||||||
|
#define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> 12)
|
||||||
|
|
||||||
|
#define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \
|
||||||
|
do { \
|
||||||
|
index = 0; \
|
||||||
|
shift = mmu_psize_defs[psize].shift; \
|
||||||
|
|
||||||
pte_val(pte) = (pfn << PTE_RPN_SHIFT) | pgprot_val(pgprot);
|
#define pte_iterate_hashed_end() } while(0)
|
||||||
return pte;
|
|
||||||
}
|
|
||||||
|
|
||||||
#define pte_modify(_pte, newprot) \
|
#ifdef CONFIG_PPC_HAS_HASH_64K
|
||||||
(__pte((pte_val(_pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)))
|
#define pte_pagesize_index(mm, addr, pte) get_slice_psize(mm, addr)
|
||||||
|
#else
|
||||||
|
#define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __real_pte */
|
||||||
|
|
||||||
#define pte_none(pte) ((pte_val(pte) & ~_PAGE_HPTEFLAGS) == 0)
|
|
||||||
#define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT)
|
|
||||||
|
|
||||||
/* pte_clear moved to later in this file */
|
/* pte_clear moved to later in this file */
|
||||||
|
|
||||||
#define pte_pfn(x) ((unsigned long)((pte_val(x)>>PTE_RPN_SHIFT)))
|
|
||||||
#define pte_page(x) pfn_to_page(pte_pfn(x))
|
|
||||||
|
|
||||||
#define PMD_BAD_BITS (PTE_TABLE_SIZE-1)
|
#define PMD_BAD_BITS (PTE_TABLE_SIZE-1)
|
||||||
#define PUD_BAD_BITS (PMD_TABLE_SIZE-1)
|
#define PUD_BAD_BITS (PMD_TABLE_SIZE-1)
|
||||||
|
|
||||||
|
|
@ -235,36 +171,6 @@ static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
|
||||||
/* This now only contains the vmalloc pages */
|
/* This now only contains the vmalloc pages */
|
||||||
#define pgd_offset_k(address) pgd_offset(&init_mm, address)
|
#define pgd_offset_k(address) pgd_offset(&init_mm, address)
|
||||||
|
|
||||||
/*
|
|
||||||
* The following only work if pte_present() is true.
|
|
||||||
* Undefined behaviour if not..
|
|
||||||
*/
|
|
||||||
static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW;}
|
|
||||||
static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY;}
|
|
||||||
static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED;}
|
|
||||||
static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE;}
|
|
||||||
static inline int pte_special(pte_t pte) { return pte_val(pte) & _PAGE_SPECIAL; }
|
|
||||||
|
|
||||||
static inline pte_t pte_wrprotect(pte_t pte) {
|
|
||||||
pte_val(pte) &= ~(_PAGE_RW); return pte; }
|
|
||||||
static inline pte_t pte_mkclean(pte_t pte) {
|
|
||||||
pte_val(pte) &= ~(_PAGE_DIRTY); return pte; }
|
|
||||||
static inline pte_t pte_mkold(pte_t pte) {
|
|
||||||
pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
|
|
||||||
static inline pte_t pte_mkwrite(pte_t pte) {
|
|
||||||
pte_val(pte) |= _PAGE_RW; return pte; }
|
|
||||||
static inline pte_t pte_mkdirty(pte_t pte) {
|
|
||||||
pte_val(pte) |= _PAGE_DIRTY; return pte; }
|
|
||||||
static inline pte_t pte_mkyoung(pte_t pte) {
|
|
||||||
pte_val(pte) |= _PAGE_ACCESSED; return pte; }
|
|
||||||
static inline pte_t pte_mkhuge(pte_t pte) {
|
|
||||||
return pte; }
|
|
||||||
static inline pte_t pte_mkspecial(pte_t pte) {
|
|
||||||
pte_val(pte) |= _PAGE_SPECIAL; return pte; }
|
|
||||||
static inline pgprot_t pte_pgprot(pte_t pte)
|
|
||||||
{
|
|
||||||
return __pgprot(pte_val(pte) & PAGE_PROT_BITS);
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Atomic PTE updates */
|
/* Atomic PTE updates */
|
||||||
static inline unsigned long pte_update(struct mm_struct *mm,
|
static inline unsigned long pte_update(struct mm_struct *mm,
|
||||||
|
|
@ -272,6 +178,7 @@ static inline unsigned long pte_update(struct mm_struct *mm,
|
||||||
pte_t *ptep, unsigned long clr,
|
pte_t *ptep, unsigned long clr,
|
||||||
int huge)
|
int huge)
|
||||||
{
|
{
|
||||||
|
#ifdef PTE_ATOMIC_UPDATES
|
||||||
unsigned long old, tmp;
|
unsigned long old, tmp;
|
||||||
|
|
||||||
__asm__ __volatile__(
|
__asm__ __volatile__(
|
||||||
|
|
@ -284,6 +191,13 @@ static inline unsigned long pte_update(struct mm_struct *mm,
|
||||||
: "=&r" (old), "=&r" (tmp), "=m" (*ptep)
|
: "=&r" (old), "=&r" (tmp), "=m" (*ptep)
|
||||||
: "r" (ptep), "r" (clr), "m" (*ptep), "i" (_PAGE_BUSY)
|
: "r" (ptep), "r" (clr), "m" (*ptep), "i" (_PAGE_BUSY)
|
||||||
: "cc" );
|
: "cc" );
|
||||||
|
#else
|
||||||
|
unsigned long old = pte_val(*ptep);
|
||||||
|
*ptep = __pte(old & ~clr);
|
||||||
|
#endif
|
||||||
|
/* huge pages use the old page table lock */
|
||||||
|
if (!huge)
|
||||||
|
assert_pte_locked(mm, addr);
|
||||||
|
|
||||||
if (old & _PAGE_HASHPTE)
|
if (old & _PAGE_HASHPTE)
|
||||||
hpte_need_flush(mm, addr, ptep, old, huge);
|
hpte_need_flush(mm, addr, ptep, old, huge);
|
||||||
|
|
@ -359,26 +273,17 @@ static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
|
||||||
pte_update(mm, addr, ptep, ~0UL, 0);
|
pte_update(mm, addr, ptep, ~0UL, 0);
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
|
||||||
* set_pte stores a linux PTE into the linux page table.
|
|
||||||
*/
|
|
||||||
static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
|
|
||||||
pte_t *ptep, pte_t pte)
|
|
||||||
{
|
|
||||||
if (pte_present(*ptep))
|
|
||||||
pte_clear(mm, addr, ptep);
|
|
||||||
pte = __pte(pte_val(pte) & ~_PAGE_HPTEFLAGS);
|
|
||||||
*ptep = pte;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Set the dirty and/or accessed bits atomically in a linux PTE, this
|
/* Set the dirty and/or accessed bits atomically in a linux PTE, this
|
||||||
* function doesn't need to flush the hash entry
|
* function doesn't need to flush the hash entry
|
||||||
*/
|
*/
|
||||||
#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
|
static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry)
|
||||||
static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty)
|
|
||||||
{
|
{
|
||||||
unsigned long bits = pte_val(entry) &
|
unsigned long bits = pte_val(entry) &
|
||||||
(_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW | _PAGE_EXEC);
|
(_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW |
|
||||||
|
_PAGE_EXEC | _PAGE_HWEXEC);
|
||||||
|
|
||||||
|
#ifdef PTE_ATOMIC_UPDATES
|
||||||
unsigned long old, tmp;
|
unsigned long old, tmp;
|
||||||
|
|
||||||
__asm__ __volatile__(
|
__asm__ __volatile__(
|
||||||
|
|
@ -391,16 +296,11 @@ static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty)
|
||||||
:"=&r" (old), "=&r" (tmp), "=m" (*ptep)
|
:"=&r" (old), "=&r" (tmp), "=m" (*ptep)
|
||||||
:"r" (bits), "r" (ptep), "m" (*ptep), "i" (_PAGE_BUSY)
|
:"r" (bits), "r" (ptep), "m" (*ptep), "i" (_PAGE_BUSY)
|
||||||
:"cc");
|
:"cc");
|
||||||
|
#else
|
||||||
|
unsigned long old = pte_val(*ptep);
|
||||||
|
*ptep = __pte(old | bits);
|
||||||
|
#endif
|
||||||
}
|
}
|
||||||
#define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
|
|
||||||
({ \
|
|
||||||
int __changed = !pte_same(*(__ptep), __entry); \
|
|
||||||
if (__changed) { \
|
|
||||||
__ptep_set_access_flags(__ptep, __entry, __dirty); \
|
|
||||||
flush_tlb_page_nohash(__vma, __address); \
|
|
||||||
} \
|
|
||||||
__changed; \
|
|
||||||
})
|
|
||||||
|
|
||||||
#define __HAVE_ARCH_PTE_SAME
|
#define __HAVE_ARCH_PTE_SAME
|
||||||
#define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HPTEFLAGS) == 0)
|
#define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HPTEFLAGS) == 0)
|
||||||
|
|
|
||||||
|
|
@ -6,7 +6,17 @@
|
||||||
#include <asm/processor.h> /* For TASK_SIZE */
|
#include <asm/processor.h> /* For TASK_SIZE */
|
||||||
#include <asm/mmu.h>
|
#include <asm/mmu.h>
|
||||||
#include <asm/page.h>
|
#include <asm/page.h>
|
||||||
|
|
||||||
struct mm_struct;
|
struct mm_struct;
|
||||||
|
|
||||||
|
#ifdef CONFIG_DEBUG_VM
|
||||||
|
extern void assert_pte_locked(struct mm_struct *mm, unsigned long addr);
|
||||||
|
#else /* CONFIG_DEBUG_VM */
|
||||||
|
static inline void assert_pte_locked(struct mm_struct *mm, unsigned long addr)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
#endif /* !CONFIG_DEBUG_VM */
|
||||||
|
|
||||||
#endif /* !__ASSEMBLY__ */
|
#endif /* !__ASSEMBLY__ */
|
||||||
|
|
||||||
#if defined(CONFIG_PPC64)
|
#if defined(CONFIG_PPC64)
|
||||||
|
|
@ -17,6 +27,130 @@ struct mm_struct;
|
||||||
|
|
||||||
#ifndef __ASSEMBLY__
|
#ifndef __ASSEMBLY__
|
||||||
|
|
||||||
|
/* Generic accessors to PTE bits */
|
||||||
|
static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW; }
|
||||||
|
static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
|
||||||
|
static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
|
||||||
|
static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; }
|
||||||
|
static inline int pte_special(pte_t pte) { return pte_val(pte) & _PAGE_SPECIAL; }
|
||||||
|
static inline int pte_present(pte_t pte) { return pte_val(pte) & _PAGE_PRESENT; }
|
||||||
|
static inline int pte_none(pte_t pte) { return (pte_val(pte) & ~_PTE_NONE_MASK) == 0; }
|
||||||
|
static inline pgprot_t pte_pgprot(pte_t pte) { return __pgprot(pte_val(pte) & PAGE_PROT_BITS); }
|
||||||
|
|
||||||
|
/* Conversion functions: convert a page and protection to a page entry,
|
||||||
|
* and a page entry and page directory to the page they refer to.
|
||||||
|
*
|
||||||
|
* Even if PTEs can be unsigned long long, a PFN is always an unsigned
|
||||||
|
* long for now.
|
||||||
|
*/
|
||||||
|
static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) {
|
||||||
|
return __pte(((pte_basic_t)(pfn) << PTE_RPN_SHIFT) |
|
||||||
|
pgprot_val(pgprot)); }
|
||||||
|
static inline unsigned long pte_pfn(pte_t pte) {
|
||||||
|
return pte_val(pte) >> PTE_RPN_SHIFT; }
|
||||||
|
|
||||||
|
/* Keep these as a macros to avoid include dependency mess */
|
||||||
|
#define pte_page(x) pfn_to_page(pte_pfn(x))
|
||||||
|
#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
|
||||||
|
|
||||||
|
/* Generic modifiers for PTE bits */
|
||||||
|
static inline pte_t pte_wrprotect(pte_t pte) {
|
||||||
|
pte_val(pte) &= ~(_PAGE_RW | _PAGE_HWWRITE); return pte; }
|
||||||
|
static inline pte_t pte_mkclean(pte_t pte) {
|
||||||
|
pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HWWRITE); return pte; }
|
||||||
|
static inline pte_t pte_mkold(pte_t pte) {
|
||||||
|
pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
|
||||||
|
static inline pte_t pte_mkwrite(pte_t pte) {
|
||||||
|
pte_val(pte) |= _PAGE_RW; return pte; }
|
||||||
|
static inline pte_t pte_mkdirty(pte_t pte) {
|
||||||
|
pte_val(pte) |= _PAGE_DIRTY; return pte; }
|
||||||
|
static inline pte_t pte_mkyoung(pte_t pte) {
|
||||||
|
pte_val(pte) |= _PAGE_ACCESSED; return pte; }
|
||||||
|
static inline pte_t pte_mkspecial(pte_t pte) {
|
||||||
|
pte_val(pte) |= _PAGE_SPECIAL; return pte; }
|
||||||
|
static inline pte_t pte_mkhuge(pte_t pte) {
|
||||||
|
return pte; }
|
||||||
|
static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
|
||||||
|
{
|
||||||
|
pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot);
|
||||||
|
return pte;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/* Insert a PTE, top-level function is out of line. It uses an inline
|
||||||
|
* low level function in the respective pgtable-* files
|
||||||
|
*/
|
||||||
|
extern void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep,
|
||||||
|
pte_t pte);
|
||||||
|
|
||||||
|
/* This low level function performs the actual PTE insertion
|
||||||
|
* Setting the PTE depends on the MMU type and other factors. It's
|
||||||
|
* an horrible mess that I'm not going to try to clean up now but
|
||||||
|
* I'm keeping it in one place rather than spread around
|
||||||
|
*/
|
||||||
|
static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
|
||||||
|
pte_t *ptep, pte_t pte, int percpu)
|
||||||
|
{
|
||||||
|
#if defined(CONFIG_PPC_STD_MMU_32) && defined(CONFIG_SMP) && !defined(CONFIG_PTE_64BIT)
|
||||||
|
/* First case is 32-bit Hash MMU in SMP mode with 32-bit PTEs. We use the
|
||||||
|
* helper pte_update() which does an atomic update. We need to do that
|
||||||
|
* because a concurrent invalidation can clear _PAGE_HASHPTE. If it's a
|
||||||
|
* per-CPU PTE such as a kmap_atomic, we do a simple update preserving
|
||||||
|
* the hash bits instead (ie, same as the non-SMP case)
|
||||||
|
*/
|
||||||
|
if (percpu)
|
||||||
|
*ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE)
|
||||||
|
| (pte_val(pte) & ~_PAGE_HASHPTE));
|
||||||
|
else
|
||||||
|
pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte));
|
||||||
|
|
||||||
|
#elif defined(CONFIG_PPC32) && defined(CONFIG_PTE_64BIT) && defined(CONFIG_SMP)
|
||||||
|
/* Second case is 32-bit with 64-bit PTE in SMP mode. In this case, we
|
||||||
|
* can just store as long as we do the two halves in the right order
|
||||||
|
* with a barrier in between. This is possible because we take care,
|
||||||
|
* in the hash code, to pre-invalidate if the PTE was already hashed,
|
||||||
|
* which synchronizes us with any concurrent invalidation.
|
||||||
|
* In the percpu case, we also fallback to the simple update preserving
|
||||||
|
* the hash bits
|
||||||
|
*/
|
||||||
|
if (percpu) {
|
||||||
|
*ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE)
|
||||||
|
| (pte_val(pte) & ~_PAGE_HASHPTE));
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
#if _PAGE_HASHPTE != 0
|
||||||
|
if (pte_val(*ptep) & _PAGE_HASHPTE)
|
||||||
|
flush_hash_entry(mm, ptep, addr);
|
||||||
|
#endif
|
||||||
|
__asm__ __volatile__("\
|
||||||
|
stw%U0%X0 %2,%0\n\
|
||||||
|
eieio\n\
|
||||||
|
stw%U0%X0 %L2,%1"
|
||||||
|
: "=m" (*ptep), "=m" (*((unsigned char *)ptep+4))
|
||||||
|
: "r" (pte) : "memory");
|
||||||
|
|
||||||
|
#elif defined(CONFIG_PPC_STD_MMU_32)
|
||||||
|
/* Third case is 32-bit hash table in UP mode, we need to preserve
|
||||||
|
* the _PAGE_HASHPTE bit since we may not have invalidated the previous
|
||||||
|
* translation in the hash yet (done in a subsequent flush_tlb_xxx())
|
||||||
|
* and see we need to keep track that this PTE needs invalidating
|
||||||
|
*/
|
||||||
|
*ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE)
|
||||||
|
| (pte_val(pte) & ~_PAGE_HASHPTE));
|
||||||
|
|
||||||
|
#else
|
||||||
|
/* Anything else just stores the PTE normally. That covers all 64-bit
|
||||||
|
* cases, and 32-bit non-hash with 64-bit PTEs in UP mode
|
||||||
|
*/
|
||||||
|
*ptep = pte;
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
|
||||||
|
extern int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long address,
|
||||||
|
pte_t *ptep, pte_t entry, int dirty);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Macro to mark a page protection value as "uncacheable".
|
* Macro to mark a page protection value as "uncacheable".
|
||||||
*/
|
*/
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,73 @@
|
||||||
|
/*
|
||||||
|
* Copyright 2009 Freescale Semicondutor, Inc.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License
|
||||||
|
* as published by the Free Software Foundation; either version
|
||||||
|
* 2 of the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* provides masks and opcode images for use by code generation, emulation
|
||||||
|
* and for instructions that older assemblers might not know about
|
||||||
|
*/
|
||||||
|
#ifndef _ASM_POWERPC_PPC_OPCODE_H
|
||||||
|
#define _ASM_POWERPC_PPC_OPCODE_H
|
||||||
|
|
||||||
|
#include <linux/stringify.h>
|
||||||
|
#include <asm/asm-compat.h>
|
||||||
|
|
||||||
|
/* sorted alphabetically */
|
||||||
|
#define PPC_INST_DCBA 0x7c0005ec
|
||||||
|
#define PPC_INST_DCBA_MASK 0xfc0007fe
|
||||||
|
#define PPC_INST_DCBAL 0x7c2005ec
|
||||||
|
#define PPC_INST_DCBZL 0x7c2007ec
|
||||||
|
#define PPC_INST_ISEL 0x7c00001e
|
||||||
|
#define PPC_INST_ISEL_MASK 0xfc00003e
|
||||||
|
#define PPC_INST_LSWI 0x7c0004aa
|
||||||
|
#define PPC_INST_LSWX 0x7c00042a
|
||||||
|
#define PPC_INST_LWSYNC 0x7c2004ac
|
||||||
|
#define PPC_INST_MCRXR 0x7c000400
|
||||||
|
#define PPC_INST_MCRXR_MASK 0xfc0007fe
|
||||||
|
#define PPC_INST_MFSPR_PVR 0x7c1f42a6
|
||||||
|
#define PPC_INST_MFSPR_PVR_MASK 0xfc1fffff
|
||||||
|
#define PPC_INST_MSGSND 0x7c00019c
|
||||||
|
#define PPC_INST_NOP 0x60000000
|
||||||
|
#define PPC_INST_POPCNTB 0x7c0000f4
|
||||||
|
#define PPC_INST_POPCNTB_MASK 0xfc0007fe
|
||||||
|
#define PPC_INST_RFCI 0x4c000066
|
||||||
|
#define PPC_INST_RFDI 0x4c00004e
|
||||||
|
#define PPC_INST_RFMCI 0x4c00004c
|
||||||
|
|
||||||
|
#define PPC_INST_STRING 0x7c00042a
|
||||||
|
#define PPC_INST_STRING_MASK 0xfc0007fe
|
||||||
|
#define PPC_INST_STRING_GEN_MASK 0xfc00067e
|
||||||
|
|
||||||
|
#define PPC_INST_STSWI 0x7c0005aa
|
||||||
|
#define PPC_INST_STSWX 0x7c00052a
|
||||||
|
#define PPC_INST_TLBILX 0x7c000626
|
||||||
|
#define PPC_INST_WAIT 0x7c00007c
|
||||||
|
|
||||||
|
/* macros to insert fields into opcodes */
|
||||||
|
#define __PPC_RA(a) ((a & 0x1f) << 16)
|
||||||
|
#define __PPC_RB(b) ((b & 0x1f) << 11)
|
||||||
|
#define __PPC_T_TLB(t) ((t & 0x3) << 21)
|
||||||
|
#define __PPC_WC(w) ((w & 0x3) << 21)
|
||||||
|
|
||||||
|
/* Deal with instructions that older assemblers aren't aware of */
|
||||||
|
#define PPC_DCBAL(a, b) stringify_in_c(.long PPC_INST_DCBAL | \
|
||||||
|
__PPC_RA(a) | __PPC_RB(b))
|
||||||
|
#define PPC_DCBZL(a, b) stringify_in_c(.long PPC_INST_DCBZL | \
|
||||||
|
__PPC_RA(a) | __PPC_RB(b))
|
||||||
|
#define PPC_MSGSND(b) stringify_in_c(.long PPC_INST_MSGSND | \
|
||||||
|
__PPC_RB(b))
|
||||||
|
#define PPC_RFCI stringify_in_c(.long PPC_INST_RFCI)
|
||||||
|
#define PPC_RFDI stringify_in_c(.long PPC_INST_RFDI)
|
||||||
|
#define PPC_RFMCI stringify_in_c(.long PPC_INST_RFMCI)
|
||||||
|
#define PPC_TLBILX(t, a, b) stringify_in_c(.long PPC_INST_TLBILX | \
|
||||||
|
__PPC_T_TLB(t) | __PPC_RA(a) | __PPC_RB(b))
|
||||||
|
#define PPC_TLBILX_ALL(a, b) PPC_TLBILX(0, a, b)
|
||||||
|
#define PPC_TLBILX_PID(a, b) PPC_TLBILX(1, a, b)
|
||||||
|
#define PPC_TLBILX_VA(a, b) PPC_TLBILX(3, a, b)
|
||||||
|
#define PPC_WAIT(w) stringify_in_c(.long PPC_INST_WAIT | \
|
||||||
|
__PPC_WC(w))
|
||||||
|
|
||||||
|
#endif /* _ASM_POWERPC_PPC_OPCODE_H */
|
||||||
|
|
@ -7,6 +7,7 @@
|
||||||
#include <linux/stringify.h>
|
#include <linux/stringify.h>
|
||||||
#include <asm/asm-compat.h>
|
#include <asm/asm-compat.h>
|
||||||
#include <asm/processor.h>
|
#include <asm/processor.h>
|
||||||
|
#include <asm/ppc-opcode.h>
|
||||||
|
|
||||||
#ifndef __ASSEMBLY__
|
#ifndef __ASSEMBLY__
|
||||||
#error __FILE__ should only be used in assembler files
|
#error __FILE__ should only be used in assembler files
|
||||||
|
|
@ -167,11 +168,6 @@ END_FTR_SECTION_IFCLR(CPU_FTR_PURR); \
|
||||||
#define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority
|
#define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority
|
||||||
#define HMT_HIGH or 3,3,3
|
#define HMT_HIGH or 3,3,3
|
||||||
|
|
||||||
/* handle instructions that older assemblers may not know */
|
|
||||||
#define RFCI .long 0x4c000066 /* rfci instruction */
|
|
||||||
#define RFDI .long 0x4c00004e /* rfdi instruction */
|
|
||||||
#define RFMCI .long 0x4c00004c /* rfmci instruction */
|
|
||||||
|
|
||||||
#ifdef __KERNEL__
|
#ifdef __KERNEL__
|
||||||
#ifdef CONFIG_PPC64
|
#ifdef CONFIG_PPC64
|
||||||
|
|
||||||
|
|
|
||||||
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