igb: consolidate creation of Tx buffer info and data descriptor
This change will combine the writes of tx_buffer_info and the Tx data descriptors into a single function. The advantage of this is that we can avoid needless memory reads from the buffer info struct and speed things up by keeping the accesses to the local registers. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Tested-by: Aaron Brown <aaron.f.brown@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
This commit is contained in:
Alexander Duyck
Jeff Kirsher
Родитель
2bbfebe2db
Коммит
ebe42d169b
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@ -135,7 +135,6 @@ struct vf_data_storage {
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#define IGB_TX_FLAGS_TSO 0x00000004
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#define IGB_TX_FLAGS_IPV4 0x00000008
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#define IGB_TX_FLAGS_TSTAMP 0x00000010
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#define IGB_TX_FLAGS_MAPPED_AS_PAGE 0x00000020
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#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
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#define IGB_TX_FLAGS_VLAN_SHIFT 16
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@ -144,13 +143,12 @@ struct vf_data_storage {
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struct igb_tx_buffer {
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union e1000_adv_tx_desc *next_to_watch;
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unsigned long time_stamp;
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dma_addr_t dma;
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u32 length;
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u32 tx_flags;
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struct sk_buff *skb;
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unsigned int bytecount;
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u16 gso_segs;
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u8 mapped_as_page;
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dma_addr_t dma;
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u32 length;
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u32 tx_flags;
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};
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struct igb_rx_buffer {
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@ -3139,29 +3139,26 @@ static void igb_free_all_tx_resources(struct igb_adapter *adapter)
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igb_free_tx_resources(adapter->tx_ring[i]);
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}
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void igb_unmap_and_free_tx_resource(struct igb_ring *tx_ring,
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struct igb_tx_buffer *buffer_info)
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void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
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struct igb_tx_buffer *tx_buffer)
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{
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if (buffer_info->dma) {
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if (buffer_info->tx_flags & IGB_TX_FLAGS_MAPPED_AS_PAGE)
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dma_unmap_page(tx_ring->dev,
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buffer_info->dma,
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buffer_info->length,
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DMA_TO_DEVICE);
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else
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dma_unmap_single(tx_ring->dev,
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buffer_info->dma,
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buffer_info->length,
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DMA_TO_DEVICE);
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buffer_info->dma = 0;
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if (tx_buffer->skb) {
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dev_kfree_skb_any(tx_buffer->skb);
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if (tx_buffer->dma)
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dma_unmap_single(ring->dev,
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tx_buffer->dma,
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tx_buffer->length,
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DMA_TO_DEVICE);
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} else if (tx_buffer->dma) {
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dma_unmap_page(ring->dev,
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tx_buffer->dma,
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tx_buffer->length,
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DMA_TO_DEVICE);
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}
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if (buffer_info->skb) {
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dev_kfree_skb_any(buffer_info->skb);
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buffer_info->skb = NULL;
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}
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buffer_info->time_stamp = 0;
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buffer_info->length = 0;
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buffer_info->next_to_watch = NULL;
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tx_buffer->next_to_watch = NULL;
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tx_buffer->skb = NULL;
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tx_buffer->dma = 0;
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/* buffer_info must be completely set up in the transmit path */
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}
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/**
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@ -4138,124 +4135,153 @@ static __le32 igb_tx_olinfo_status(u32 tx_flags, unsigned int paylen,
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return cpu_to_le32(olinfo_status);
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}
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#define IGB_MAX_TXD_PWR 16
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#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
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/*
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* The largest size we can write to the descriptor is 65535. In order to
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* maintain a power of two alignment we have to limit ourselves to 32K.
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*/
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#define IGB_MAX_TXD_PWR 15
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#define IGB_MAX_DATA_PER_TXD (1 << IGB_MAX_TXD_PWR)
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static inline int igb_tx_map(struct igb_ring *tx_ring, struct sk_buff *skb,
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struct igb_tx_buffer *first, u32 tx_flags)
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static void igb_tx_map(struct igb_ring *tx_ring, struct sk_buff *skb,
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struct igb_tx_buffer *first, u32 tx_flags,
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const u8 hdr_len)
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{
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struct igb_tx_buffer *buffer_info;
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struct device *dev = tx_ring->dev;
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unsigned int hlen = skb_headlen(skb);
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unsigned int count = 0, i;
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unsigned int f;
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u16 gso_segs = skb_shinfo(skb)->gso_segs ?: 1;
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struct igb_tx_buffer *tx_buffer_info;
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union e1000_adv_tx_desc *tx_desc;
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dma_addr_t dma;
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struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
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unsigned int data_len = skb->data_len;
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unsigned int size = skb_headlen(skb);
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unsigned int paylen = skb->len - hdr_len;
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__le32 cmd_type;
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u16 i = tx_ring->next_to_use;
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u16 gso_segs;
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i = tx_ring->next_to_use;
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if (tx_flags & IGB_TX_FLAGS_TSO)
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gso_segs = skb_shinfo(skb)->gso_segs;
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else
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gso_segs = 1;
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buffer_info = &tx_ring->tx_buffer_info[i];
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BUG_ON(hlen >= IGB_MAX_DATA_PER_TXD);
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buffer_info->length = hlen;
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buffer_info->tx_flags = tx_flags;
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buffer_info->dma = dma_map_single(dev, skb->data, hlen,
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DMA_TO_DEVICE);
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if (dma_mapping_error(dev, buffer_info->dma))
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/* multiply data chunks by size of headers */
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first->bytecount = paylen + (gso_segs * hdr_len);
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first->gso_segs = gso_segs;
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first->skb = skb;
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tx_desc = IGB_TX_DESC(tx_ring, i);
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tx_desc->read.olinfo_status =
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igb_tx_olinfo_status(tx_flags, paylen, tx_ring);
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cmd_type = igb_tx_cmd_type(tx_flags);
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dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
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if (dma_mapping_error(tx_ring->dev, dma))
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goto dma_error;
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tx_flags |= IGB_TX_FLAGS_MAPPED_AS_PAGE;
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/* record length, and DMA address */
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first->length = size;
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first->dma = dma;
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first->tx_flags = tx_flags;
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tx_desc->read.buffer_addr = cpu_to_le64(dma);
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for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
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struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[f];
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unsigned int len = frag->size;
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for (;;) {
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while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
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tx_desc->read.cmd_type_len =
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cmd_type | cpu_to_le32(IGB_MAX_DATA_PER_TXD);
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i++;
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tx_desc++;
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if (i == tx_ring->count) {
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tx_desc = IGB_TX_DESC(tx_ring, 0);
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i = 0;
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}
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dma += IGB_MAX_DATA_PER_TXD;
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size -= IGB_MAX_DATA_PER_TXD;
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tx_desc->read.olinfo_status = 0;
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tx_desc->read.buffer_addr = cpu_to_le64(dma);
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}
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if (likely(!data_len))
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break;
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tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
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count++;
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i++;
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if (i == tx_ring->count)
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tx_desc++;
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if (i == tx_ring->count) {
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tx_desc = IGB_TX_DESC(tx_ring, 0);
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i = 0;
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}
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buffer_info = &tx_ring->tx_buffer_info[i];
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BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
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buffer_info->length = len;
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buffer_info->tx_flags = tx_flags;
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buffer_info->dma = skb_frag_dma_map(dev, frag, 0, len,
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DMA_TO_DEVICE);
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if (dma_mapping_error(dev, buffer_info->dma))
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size = frag->size;
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data_len -= size;
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dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
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size, DMA_TO_DEVICE);
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if (dma_mapping_error(tx_ring->dev, dma))
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goto dma_error;
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tx_buffer_info = &tx_ring->tx_buffer_info[i];
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tx_buffer_info->length = size;
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tx_buffer_info->dma = dma;
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tx_desc->read.olinfo_status = 0;
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tx_desc->read.buffer_addr = cpu_to_le64(dma);
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frag++;
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}
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buffer_info->skb = skb;
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/* multiply data chunks by size of headers */
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buffer_info->bytecount = ((gso_segs - 1) * hlen) + skb->len;
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buffer_info->gso_segs = gso_segs;
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/* write last descriptor with RS and EOP bits */
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cmd_type |= cpu_to_le32(size) | cpu_to_le32(IGB_TXD_DCMD);
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tx_desc->read.cmd_type_len = cmd_type;
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/* set the timestamp */
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first->time_stamp = jiffies;
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/* set next_to_watch value indicating a packet is present */
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first->next_to_watch = IGB_TX_DESC(tx_ring, i);
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return ++count;
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dma_error:
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dev_err(dev, "TX DMA map failed\n");
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/* clear timestamp and dma mappings for failed buffer_info mapping */
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buffer_info->dma = 0;
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buffer_info->time_stamp = 0;
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buffer_info->length = 0;
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/* clear timestamp and dma mappings for remaining portion of packet */
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while (count--) {
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if (i == 0)
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i = tx_ring->count;
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i--;
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buffer_info = &tx_ring->tx_buffer_info[i];
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igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
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}
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return 0;
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}
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static inline void igb_tx_queue(struct igb_ring *tx_ring,
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u32 tx_flags, int count, u32 paylen,
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u8 hdr_len)
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{
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union e1000_adv_tx_desc *tx_desc;
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struct igb_tx_buffer *buffer_info;
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__le32 olinfo_status, cmd_type;
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unsigned int i = tx_ring->next_to_use;
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cmd_type = igb_tx_cmd_type(tx_flags);
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olinfo_status = igb_tx_olinfo_status(tx_flags,
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paylen - hdr_len,
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tx_ring);
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do {
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buffer_info = &tx_ring->tx_buffer_info[i];
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tx_desc = IGB_TX_DESC(tx_ring, i);
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tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
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tx_desc->read.cmd_type_len = cmd_type |
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cpu_to_le32(buffer_info->length);
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tx_desc->read.olinfo_status = olinfo_status;
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count--;
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i++;
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if (i == tx_ring->count)
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i = 0;
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} while (count > 0);
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tx_desc->read.cmd_type_len |= cpu_to_le32(IGB_TXD_DCMD);
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/* Force memory writes to complete before letting h/w
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* know there are new descriptors to fetch. (Only
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* applicable for weak-ordered memory model archs,
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* such as IA-64). */
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/*
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* Force memory writes to complete before letting h/w know there
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* are new descriptors to fetch. (Only applicable for weak-ordered
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* memory model archs, such as IA-64).
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*
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* We also need this memory barrier to make certain all of the
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* status bits have been updated before next_to_watch is written.
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*/
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wmb();
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/* set next_to_watch value indicating a packet is present */
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first->next_to_watch = tx_desc;
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i++;
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if (i == tx_ring->count)
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i = 0;
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tx_ring->next_to_use = i;
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writel(i, tx_ring->tail);
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/* we need this if more than one processor can write to our tail
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* at a time, it syncronizes IO on IA64/Altix systems */
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mmiowb();
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return;
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dma_error:
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dev_err(tx_ring->dev, "TX DMA map failed\n");
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/* clear dma mappings for failed tx_buffer_info map */
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for (;;) {
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tx_buffer_info = &tx_ring->tx_buffer_info[i];
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igb_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
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if (tx_buffer_info == first)
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break;
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if (i == 0)
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i = tx_ring->count;
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i--;
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}
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tx_ring->next_to_use = i;
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}
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static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, int size)
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@ -4295,7 +4321,7 @@ netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
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struct igb_ring *tx_ring)
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{
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struct igb_tx_buffer *first;
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int tso, count;
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int tso;
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u32 tx_flags = 0;
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__be16 protocol = vlan_get_protocol(skb);
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u8 hdr_len = 0;
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@ -4335,19 +4361,7 @@ netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
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tx_flags |= IGB_TX_FLAGS_CSUM;
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}
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/*
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* count reflects descriptors mapped, if 0 or less then mapping error
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* has occurred and we need to rewind the descriptor queue
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*/
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count = igb_tx_map(tx_ring, skb, first, tx_flags);
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if (!count) {
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dev_kfree_skb_any(skb);
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first->time_stamp = 0;
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tx_ring->next_to_use = first - tx_ring->tx_buffer_info;
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return NETDEV_TX_OK;
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}
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igb_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len);
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igb_tx_map(tx_ring, skb, first, tx_flags, hdr_len);
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/* Make sure there is space in the ring for the next send. */
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igb_maybe_stop_tx(tx_ring, MAX_SKB_FRAGS + 4);
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@ -5609,17 +5623,26 @@ static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
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/* clear next_to_watch to prevent false hangs */
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tx_buffer->next_to_watch = NULL;
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do {
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tx_desc->wb.status = 0;
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if (likely(tx_desc == eop_desc)) {
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eop_desc = NULL;
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/* update the statistics for this packet */
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total_bytes += tx_buffer->bytecount;
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total_packets += tx_buffer->gso_segs;
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total_bytes += tx_buffer->bytecount;
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total_packets += tx_buffer->gso_segs;
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igb_tx_hwtstamp(q_vector, tx_buffer);
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}
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/* retrieve hardware timestamp */
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igb_tx_hwtstamp(q_vector, tx_buffer);
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igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
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/* free the skb */
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dev_kfree_skb_any(tx_buffer->skb);
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tx_buffer->skb = NULL;
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/* unmap skb header data */
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dma_unmap_single(tx_ring->dev,
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tx_buffer->dma,
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tx_buffer->length,
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DMA_TO_DEVICE);
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/* clear last DMA location and unmap remaining buffers */
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while (tx_desc != eop_desc) {
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tx_buffer->dma = 0;
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tx_buffer++;
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tx_desc++;
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@ -5629,7 +5652,28 @@ static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
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tx_buffer = tx_ring->tx_buffer_info;
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tx_desc = IGB_TX_DESC(tx_ring, 0);
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}
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} while (eop_desc);
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/* unmap any remaining paged data */
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if (tx_buffer->dma) {
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dma_unmap_page(tx_ring->dev,
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tx_buffer->dma,
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tx_buffer->length,
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DMA_TO_DEVICE);
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}
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}
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/* clear last DMA location */
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tx_buffer->dma = 0;
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/* move us one more past the eop_desc for start of next pkt */
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tx_buffer++;
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tx_desc++;
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i++;
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if (unlikely(!i)) {
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i -= tx_ring->count;
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tx_buffer = tx_ring->tx_buffer_info;
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tx_desc = IGB_TX_DESC(tx_ring, 0);
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}
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}
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i += tx_ring->count;
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