Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc
* 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc: [POWERPC] Fix crashkernel= handling when no crashkernel= specified [POWERPC] Make emergency stack safe for current_thread_info() use [POWERPC] spufs: add .gitignore for spu_save_dump.h & spu_restore_dump.h [POWERPC] spufs: trace spu_acquire_saved events [POWERPC] spufs: fix marker name for find_victim [POWERPC] spufs: add marker for destroy_spu_context [POWERPC] spufs: add sputrace marker parameter names [POWERPC] spufs: add context switch notification log [POWERPC] mpc5200: defconfigs for CM5200, Lite5200B, Motion-PRO and TQM5200 [POWERPC] mpc5200: Switch mpc5200 dts files to dts-v1 format [POWERPC] mpc5200: Fix FEC error handling on FIFO errors [POWERPC] mpc5200: add Phytec pcm030 board support [POWERPC] mpc5200: add gpiolib support for mpc5200 [POWERPC] mpc5200: add interrupt type function [POWERPC] mpc5200: Fix unterminated of_device_id table
This commit is contained in:
Коммит
ec31b21241
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@ -186,6 +186,12 @@ Recommended soc5200 child nodes; populate as needed for your board
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name device_type compatible Description
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---- ----------- ---------- -----------
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gpt@<addr> gpt fsl,mpc5200-gpt General purpose timers
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gpt@<addr> gpt fsl,mpc5200-gpt-gpio General purpose
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timers in GPIO mode
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gpio@<addr> fsl,mpc5200-gpio MPC5200 simple gpio
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controller
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gpio@<addr> fsl,mpc5200-gpio-wkup MPC5200 wakeup gpio
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controller
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rtc@<addr> rtc mpc5200-rtc Real time clock
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mscan@<addr> mscan mpc5200-mscan CAN bus controller
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pci@<addr> pci mpc5200-pci PCI bridge
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@ -225,6 +231,12 @@ PSC in i2s mode: The mpc5200 and mpc5200b PSCs are not compatible when in
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i2s mode. An 'mpc5200b-psc-i2s' node cannot include 'mpc5200-psc-i2s' in the
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compatible field.
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7) GPIO controller nodes
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Each GPIO controller node should have the empty property gpio-controller and
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#gpio-cells set to 2. First cell is the GPIO number which is interpreted
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according to the bit numbers in the GPIO control registers. The second cell
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is for flags which is currently unsused.
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IV - Extra Notes
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================
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@ -10,11 +10,7 @@
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* option) any later version.
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*/
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/*
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* WARNING: Do not depend on this tree layout remaining static just yet.
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* The MPC5200 device tree conventions are still in flux
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* Keep an eye on the linuxppc-dev mailing list for more details
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*/
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/dts-v1/;
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/ {
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model = "schindler,cm5200";
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@ -29,10 +25,10 @@
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PowerPC,5200@0 {
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device_type = "cpu";
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reg = <0>;
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d-cache-line-size = <20>;
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i-cache-line-size = <20>;
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d-cache-size = <4000>; // L1, 16K
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i-cache-size = <4000>; // L1, 16K
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d-cache-line-size = <32>;
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i-cache-line-size = <32>;
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d-cache-size = <0x4000>; // L1, 16K
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i-cache-size = <0x4000>; // L1, 16K
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timebase-frequency = <0>; // from bootloader
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bus-frequency = <0>; // from bootloader
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clock-frequency = <0>; // from bootloader
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@ -41,34 +37,34 @@
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memory {
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device_type = "memory";
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reg = <00000000 04000000>; // 64MB
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reg = <0x00000000 0x04000000>; // 64MB
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};
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soc5200@f0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc5200b-immr";
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ranges = <0 f0000000 0000c000>;
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reg = <f0000000 00000100>;
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ranges = <0 0xf0000000 0x0000c000>;
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reg = <0xf0000000 0x00000100>;
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bus-frequency = <0>; // from bootloader
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system-frequency = <0>; // from bootloader
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cdm@200 {
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compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
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reg = <200 38>;
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reg = <0x200 0x38>;
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};
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mpc5200_pic: pic@500 {
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mpc5200_pic: interrupt-controller@500 {
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// 5200 interrupts are encoded into two levels;
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interrupt-controller;
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#interrupt-cells = <3>;
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compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
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reg = <500 80>;
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reg = <0x500 0x80>;
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};
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timer@600 { // General Purpose Timer
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compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
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reg = <600 10>;
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reg = <0x600 0x10>;
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interrupts = <1 9 0>;
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interrupt-parent = <&mpc5200_pic>;
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fsl,has-wdt;
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@ -76,108 +72,108 @@
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timer@610 { // General Purpose Timer
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compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
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reg = <610 10>;
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interrupts = <1 a 0>;
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reg = <0x610 0x10>;
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interrupts = <1 10 0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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timer@620 { // General Purpose Timer
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compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
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reg = <620 10>;
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interrupts = <1 b 0>;
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reg = <0x620 0x10>;
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interrupts = <1 11 0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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timer@630 { // General Purpose Timer
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compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
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reg = <630 10>;
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interrupts = <1 c 0>;
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reg = <0x630 0x10>;
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interrupts = <1 12 0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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timer@640 { // General Purpose Timer
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compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
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reg = <640 10>;
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interrupts = <1 d 0>;
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reg = <0x640 0x10>;
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interrupts = <1 13 0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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timer@650 { // General Purpose Timer
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compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
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reg = <650 10>;
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interrupts = <1 e 0>;
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reg = <0x650 0x10>;
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interrupts = <1 14 0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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timer@660 { // General Purpose Timer
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compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
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reg = <660 10>;
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interrupts = <1 f 0>;
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reg = <0x660 0x10>;
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interrupts = <1 15 0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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timer@670 { // General Purpose Timer
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compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
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reg = <670 10>;
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interrupts = <1 10 0>;
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reg = <0x670 0x10>;
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interrupts = <1 16 0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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rtc@800 { // Real time clock
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compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
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reg = <800 100>;
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reg = <0x800 0x100>;
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interrupts = <1 5 0 1 6 0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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gpio@b00 {
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compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
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reg = <b00 40>;
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reg = <0xb00 0x40>;
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interrupts = <1 7 0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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gpio@c00 {
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compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
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reg = <c00 40>;
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reg = <0xc00 0x40>;
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interrupts = <1 8 0 0 3 0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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spi@f00 {
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compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
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reg = <f00 20>;
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interrupts = <2 d 0 2 e 0>;
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reg = <0xf00 0x20>;
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interrupts = <2 13 0 2 14 0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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usb@1000 {
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compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
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reg = <1000 ff>;
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reg = <0x1000 0xff>;
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interrupts = <2 6 0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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dma-controller@1200 {
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compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
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reg = <1200 80>;
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reg = <0x1200 0x80>;
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interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
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3 4 0 3 5 0 3 6 0 3 7 0
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3 8 0 3 9 0 3 a 0 3 b 0
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3 c 0 3 d 0 3 e 0 3 f 0>;
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3 8 0 3 9 0 3 10 0 3 11 0
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3 12 0 3 13 0 3 14 0 3 15 0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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xlb@1f00 {
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compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
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reg = <1f00 100>;
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reg = <0x1f00 0x100>;
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};
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serial@2000 { // PSC1
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device_type = "serial";
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compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
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port-number = <0>; // Logical port assignment
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reg = <2000 100>;
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reg = <0x2000 0x100>;
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interrupts = <2 1 0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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@ -186,7 +182,7 @@
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device_type = "serial";
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compatible = "fsl,mpc5200-psc-uart";
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port-number = <1>; // Logical port assignment
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reg = <2200 100>;
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reg = <0x2200 0x100>;
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interrupts = <2 2 0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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@ -195,7 +191,7 @@
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device_type = "serial";
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compatible = "fsl,mpc5200-psc-uart";
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port-number = <2>; // Logical port assignment
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reg = <2400 100>;
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reg = <0x2400 0x100>;
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interrupts = <2 3 0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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@ -204,7 +200,7 @@
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device_type = "serial";
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compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
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port-number = <5>; // Logical port assignment
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reg = <2c00 100>;
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reg = <0x2c00 0x100>;
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interrupts = <2 4 0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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@ -212,7 +208,7 @@
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ethernet@3000 {
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device_type = "network";
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compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
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reg = <3000 400>;
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reg = <0x3000 0x400>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <2 5 0>;
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interrupt-parent = <&mpc5200_pic>;
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@ -223,7 +219,7 @@
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
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reg = <3000 400>; // fec range, since we need to setup fec interrupts
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reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
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interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
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interrupt-parent = <&mpc5200_pic>;
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@ -237,15 +233,15 @@
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
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reg = <3d40 40>;
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interrupts = <2 10 0>;
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reg = <0x3d40 0x40>;
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interrupts = <2 16 0>;
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interrupt-parent = <&mpc5200_pic>;
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fsl5200-clocking;
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};
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sram@8000 {
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compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
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reg = <8000 4000>;
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reg = <0x8000 0x4000>;
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};
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};
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@ -254,12 +250,12 @@
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compatible = "fsl,lpb";
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0 fc000000 2000000>;
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ranges = <0 0 0xfc000000 0x2000000>;
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// 16-bit flash device at LocalPlus Bus CS0
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flash@0,0 {
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compatible = "cfi-flash";
|
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reg = <0 0 2000000>;
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reg = <0 0 0x2000000>;
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bank-width = <2>;
|
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device-width = <2>;
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#size-cells = <1>;
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|
|
|
@ -10,6 +10,8 @@
|
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* option) any later version.
|
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*/
|
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/dts-v1/;
|
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|
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/ {
|
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model = "fsl,lite5200";
|
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compatible = "fsl,lite5200";
|
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|
@ -23,10 +25,10 @@
|
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PowerPC,5200@0 {
|
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device_type = "cpu";
|
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reg = <0>;
|
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d-cache-line-size = <20>;
|
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i-cache-line-size = <20>;
|
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d-cache-size = <4000>; // L1, 16K
|
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i-cache-size = <4000>; // L1, 16K
|
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d-cache-line-size = <32>;
|
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i-cache-line-size = <32>;
|
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d-cache-size = <0x4000>; // L1, 16K
|
||||
i-cache-size = <0x4000>; // L1, 16K
|
||||
timebase-frequency = <0>; // from bootloader
|
||||
bus-frequency = <0>; // from bootloader
|
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clock-frequency = <0>; // from bootloader
|
||||
|
@ -35,21 +37,21 @@
|
|||
|
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memory {
|
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device_type = "memory";
|
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reg = <00000000 04000000>; // 64MB
|
||||
reg = <0x00000000 0x04000000>; // 64MB
|
||||
};
|
||||
|
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soc5200@f0000000 {
|
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#address-cells = <1>;
|
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#size-cells = <1>;
|
||||
compatible = "fsl,mpc5200-immr";
|
||||
ranges = <0 f0000000 0000c000>;
|
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reg = <f0000000 00000100>;
|
||||
ranges = <0 0xf0000000 0x0000c000>;
|
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reg = <0xf0000000 0x00000100>;
|
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bus-frequency = <0>; // from bootloader
|
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system-frequency = <0>; // from bootloader
|
||||
|
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cdm@200 {
|
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compatible = "fsl,mpc5200-cdm";
|
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reg = <200 38>;
|
||||
reg = <0x200 0x38>;
|
||||
};
|
||||
|
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mpc5200_pic: interrupt-controller@500 {
|
||||
|
@ -58,13 +60,13 @@
|
|||
#interrupt-cells = <3>;
|
||||
device_type = "interrupt-controller";
|
||||
compatible = "fsl,mpc5200-pic";
|
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reg = <500 80>;
|
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reg = <0x500 0x80>;
|
||||
};
|
||||
|
||||
timer@600 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200-gpt";
|
||||
cell-index = <0>;
|
||||
reg = <600 10>;
|
||||
reg = <0x600 0x10>;
|
||||
interrupts = <1 9 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
fsl,has-wdt;
|
||||
|
@ -73,63 +75,63 @@
|
|||
timer@610 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200-gpt";
|
||||
cell-index = <1>;
|
||||
reg = <610 10>;
|
||||
interrupts = <1 a 0>;
|
||||
reg = <0x610 0x10>;
|
||||
interrupts = <1 10 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
timer@620 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200-gpt";
|
||||
cell-index = <2>;
|
||||
reg = <620 10>;
|
||||
interrupts = <1 b 0>;
|
||||
reg = <0x620 0x10>;
|
||||
interrupts = <1 11 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
timer@630 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200-gpt";
|
||||
cell-index = <3>;
|
||||
reg = <630 10>;
|
||||
interrupts = <1 c 0>;
|
||||
reg = <0x630 0x10>;
|
||||
interrupts = <1 12 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
timer@640 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200-gpt";
|
||||
cell-index = <4>;
|
||||
reg = <640 10>;
|
||||
interrupts = <1 d 0>;
|
||||
reg = <0x640 0x10>;
|
||||
interrupts = <1 13 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
timer@650 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200-gpt";
|
||||
cell-index = <5>;
|
||||
reg = <650 10>;
|
||||
interrupts = <1 e 0>;
|
||||
reg = <0x650 0x10>;
|
||||
interrupts = <1 14 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
timer@660 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200-gpt";
|
||||
cell-index = <6>;
|
||||
reg = <660 10>;
|
||||
interrupts = <1 f 0>;
|
||||
reg = <0x660 0x10>;
|
||||
interrupts = <1 15 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
timer@670 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200-gpt";
|
||||
cell-index = <7>;
|
||||
reg = <670 10>;
|
||||
interrupts = <1 10 0>;
|
||||
reg = <0x670 0x10>;
|
||||
interrupts = <1 16 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
rtc@800 { // Real time clock
|
||||
compatible = "fsl,mpc5200-rtc";
|
||||
device_type = "rtc";
|
||||
reg = <800 100>;
|
||||
reg = <0x800 0x100>;
|
||||
interrupts = <1 5 0 1 6 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
@ -137,43 +139,43 @@
|
|||
can@900 {
|
||||
compatible = "fsl,mpc5200-mscan";
|
||||
cell-index = <0>;
|
||||
interrupts = <2 11 0>;
|
||||
interrupts = <2 17 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
reg = <900 80>;
|
||||
reg = <0x900 0x80>;
|
||||
};
|
||||
|
||||
can@980 {
|
||||
compatible = "fsl,mpc5200-mscan";
|
||||
cell-index = <1>;
|
||||
interrupts = <2 12 0>;
|
||||
interrupts = <2 18 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
reg = <980 80>;
|
||||
reg = <0x980 0x80>;
|
||||
};
|
||||
|
||||
gpio@b00 {
|
||||
compatible = "fsl,mpc5200-gpio";
|
||||
reg = <b00 40>;
|
||||
reg = <0xb00 0x40>;
|
||||
interrupts = <1 7 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
gpio@c00 {
|
||||
compatible = "fsl,mpc5200-gpio-wkup";
|
||||
reg = <c00 40>;
|
||||
reg = <0xc00 0x40>;
|
||||
interrupts = <1 8 0 0 3 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
spi@f00 {
|
||||
compatible = "fsl,mpc5200-spi";
|
||||
reg = <f00 20>;
|
||||
interrupts = <2 d 0 2 e 0>;
|
||||
reg = <0xf00 0x20>;
|
||||
interrupts = <2 13 0 2 14 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
usb@1000 {
|
||||
compatible = "fsl,mpc5200-ohci","ohci-be";
|
||||
reg = <1000 ff>;
|
||||
reg = <0x1000 0xff>;
|
||||
interrupts = <2 6 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
@ -181,17 +183,17 @@
|
|||
dma-controller@1200 {
|
||||
device_type = "dma-controller";
|
||||
compatible = "fsl,mpc5200-bestcomm";
|
||||
reg = <1200 80>;
|
||||
reg = <0x1200 0x80>;
|
||||
interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
|
||||
3 4 0 3 5 0 3 6 0 3 7 0
|
||||
3 8 0 3 9 0 3 a 0 3 b 0
|
||||
3 c 0 3 d 0 3 e 0 3 f 0>;
|
||||
3 8 0 3 9 0 3 10 0 3 11 0
|
||||
3 12 0 3 13 0 3 14 0 3 15 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
xlb@1f00 {
|
||||
compatible = "fsl,mpc5200-xlb";
|
||||
reg = <1f00 100>;
|
||||
reg = <0x1f00 0x100>;
|
||||
};
|
||||
|
||||
serial@2000 { // PSC1
|
||||
|
@ -199,7 +201,7 @@
|
|||
compatible = "fsl,mpc5200-psc-uart";
|
||||
port-number = <0>; // Logical port assignment
|
||||
cell-index = <0>;
|
||||
reg = <2000 100>;
|
||||
reg = <0x2000 0x100>;
|
||||
interrupts = <2 1 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
@ -208,7 +210,7 @@
|
|||
//ac97@2200 { // PSC2
|
||||
// compatible = "fsl,mpc5200-psc-ac97";
|
||||
// cell-index = <1>;
|
||||
// reg = <2200 100>;
|
||||
// reg = <0x2200 0x100>;
|
||||
// interrupts = <2 2 0>;
|
||||
// interrupt-parent = <&mpc5200_pic>;
|
||||
//};
|
||||
|
@ -217,7 +219,7 @@
|
|||
//i2s@2400 { // PSC3
|
||||
// compatible = "fsl,mpc5200-psc-i2s";
|
||||
// cell-index = <2>;
|
||||
// reg = <2400 100>;
|
||||
// reg = <0x2400 0x100>;
|
||||
// interrupts = <2 3 0>;
|
||||
// interrupt-parent = <&mpc5200_pic>;
|
||||
//};
|
||||
|
@ -227,8 +229,8 @@
|
|||
// device_type = "serial";
|
||||
// compatible = "fsl,mpc5200-psc-uart";
|
||||
// cell-index = <3>;
|
||||
// reg = <2600 100>;
|
||||
// interrupts = <2 b 0>;
|
||||
// reg = <0x2600 0x100>;
|
||||
// interrupts = <2 11 0>;
|
||||
// interrupt-parent = <&mpc5200_pic>;
|
||||
//};
|
||||
|
||||
|
@ -237,8 +239,8 @@
|
|||
// device_type = "serial";
|
||||
// compatible = "fsl,mpc5200-psc-uart";
|
||||
// cell-index = <4>;
|
||||
// reg = <2800 100>;
|
||||
// interrupts = <2 c 0>;
|
||||
// reg = <0x2800 0x100>;
|
||||
// interrupts = <2 12 0>;
|
||||
// interrupt-parent = <&mpc5200_pic>;
|
||||
//};
|
||||
|
||||
|
@ -246,7 +248,7 @@
|
|||
//spi@2c00 { // PSC6
|
||||
// compatible = "fsl,mpc5200-psc-spi";
|
||||
// cell-index = <5>;
|
||||
// reg = <2c00 100>;
|
||||
// reg = <0x2c00 0x100>;
|
||||
// interrupts = <2 4 0>;
|
||||
// interrupt-parent = <&mpc5200_pic>;
|
||||
//};
|
||||
|
@ -254,7 +256,7 @@
|
|||
ethernet@3000 {
|
||||
device_type = "network";
|
||||
compatible = "fsl,mpc5200-fec";
|
||||
reg = <3000 800>;
|
||||
reg = <0x3000 0x400>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <2 5 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
|
@ -265,11 +267,11 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,mpc5200-mdio";
|
||||
reg = <3000 400>; // fec range, since we need to setup fec interrupts
|
||||
reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
|
||||
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
|
||||
phy0:ethernet-phy@1 {
|
||||
phy0: ethernet-phy@1 {
|
||||
device_type = "ethernet-phy";
|
||||
reg = <1>;
|
||||
};
|
||||
|
@ -278,7 +280,7 @@
|
|||
ata@3a00 {
|
||||
device_type = "ata";
|
||||
compatible = "fsl,mpc5200-ata";
|
||||
reg = <3a00 100>;
|
||||
reg = <0x3a00 0x100>;
|
||||
interrupts = <2 7 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
@ -288,8 +290,8 @@
|
|||
#size-cells = <0>;
|
||||
compatible = "fsl,mpc5200-i2c","fsl-i2c";
|
||||
cell-index = <0>;
|
||||
reg = <3d00 40>;
|
||||
interrupts = <2 f 0>;
|
||||
reg = <0x3d00 0x40>;
|
||||
interrupts = <2 15 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
fsl5200-clocking;
|
||||
};
|
||||
|
@ -299,14 +301,14 @@
|
|||
#size-cells = <0>;
|
||||
compatible = "fsl,mpc5200-i2c","fsl-i2c";
|
||||
cell-index = <1>;
|
||||
reg = <3d40 40>;
|
||||
interrupts = <2 10 0>;
|
||||
reg = <0x3d40 0x40>;
|
||||
interrupts = <2 16 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
fsl5200-clocking;
|
||||
};
|
||||
sram@8000 {
|
||||
compatible = "fsl,mpc5200-sram","sram";
|
||||
reg = <8000 4000>;
|
||||
reg = <0x8000 0x4000>;
|
||||
};
|
||||
};
|
||||
|
||||
|
@ -316,18 +318,18 @@
|
|||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
compatible = "fsl,mpc5200-pci";
|
||||
reg = <f0000d00 100>;
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3
|
||||
c000 0 0 2 &mpc5200_pic 0 0 3
|
||||
c000 0 0 3 &mpc5200_pic 0 0 3
|
||||
c000 0 0 4 &mpc5200_pic 0 0 3>;
|
||||
reg = <0xf0000d00 0x100>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3
|
||||
0xc000 0 0 2 &mpc5200_pic 0 0 3
|
||||
0xc000 0 0 3 &mpc5200_pic 0 0 3
|
||||
0xc000 0 0 4 &mpc5200_pic 0 0 3>;
|
||||
clock-frequency = <0>; // From boot loader
|
||||
interrupts = <2 8 0 2 9 0 2 a 0>;
|
||||
interrupts = <2 8 0 2 9 0 2 10 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <42000000 0 80000000 80000000 0 20000000
|
||||
02000000 0 a0000000 a0000000 0 10000000
|
||||
01000000 0 00000000 b0000000 0 01000000>;
|
||||
ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
|
||||
0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
|
||||
0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -10,11 +10,7 @@
|
|||
* option) any later version.
|
||||
*/
|
||||
|
||||
/*
|
||||
* WARNING: Do not depend on this tree layout remaining static just yet.
|
||||
* The MPC5200 device tree conventions are still in flux
|
||||
* Keep an eye on the linuxppc-dev mailing list for more details
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "fsl,lite5200b";
|
||||
|
@ -29,10 +25,10 @@
|
|||
PowerPC,5200@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <20>;
|
||||
i-cache-line-size = <20>;
|
||||
d-cache-size = <4000>; // L1, 16K
|
||||
i-cache-size = <4000>; // L1, 16K
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-size = <0x4000>; // L1, 16K
|
||||
i-cache-size = <0x4000>; // L1, 16K
|
||||
timebase-frequency = <0>; // from bootloader
|
||||
bus-frequency = <0>; // from bootloader
|
||||
clock-frequency = <0>; // from bootloader
|
||||
|
@ -41,21 +37,21 @@
|
|||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <00000000 10000000>; // 256MB
|
||||
reg = <0x00000000 0x10000000>; // 256MB
|
||||
};
|
||||
|
||||
soc5200@f0000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc5200b-immr";
|
||||
ranges = <0 f0000000 0000c000>;
|
||||
reg = <f0000000 00000100>;
|
||||
ranges = <0 0xf0000000 0x0000c000>;
|
||||
reg = <0xf0000000 0x00000100>;
|
||||
bus-frequency = <0>; // from bootloader
|
||||
system-frequency = <0>; // from bootloader
|
||||
|
||||
cdm@200 {
|
||||
compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
|
||||
reg = <200 38>;
|
||||
reg = <0x200 0x38>;
|
||||
};
|
||||
|
||||
mpc5200_pic: interrupt-controller@500 {
|
||||
|
@ -64,13 +60,13 @@
|
|||
#interrupt-cells = <3>;
|
||||
device_type = "interrupt-controller";
|
||||
compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
|
||||
reg = <500 80>;
|
||||
reg = <0x500 0x80>;
|
||||
};
|
||||
|
||||
timer@600 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
cell-index = <0>;
|
||||
reg = <600 10>;
|
||||
reg = <0x600 0x10>;
|
||||
interrupts = <1 9 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
fsl,has-wdt;
|
||||
|
@ -79,63 +75,63 @@
|
|||
timer@610 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
cell-index = <1>;
|
||||
reg = <610 10>;
|
||||
interrupts = <1 a 0>;
|
||||
reg = <0x610 0x10>;
|
||||
interrupts = <1 10 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
timer@620 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
cell-index = <2>;
|
||||
reg = <620 10>;
|
||||
interrupts = <1 b 0>;
|
||||
reg = <0x620 0x10>;
|
||||
interrupts = <1 11 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
timer@630 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
cell-index = <3>;
|
||||
reg = <630 10>;
|
||||
interrupts = <1 c 0>;
|
||||
reg = <0x630 0x10>;
|
||||
interrupts = <1 12 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
timer@640 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
cell-index = <4>;
|
||||
reg = <640 10>;
|
||||
interrupts = <1 d 0>;
|
||||
reg = <0x640 0x10>;
|
||||
interrupts = <1 13 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
timer@650 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
cell-index = <5>;
|
||||
reg = <650 10>;
|
||||
interrupts = <1 e 0>;
|
||||
reg = <0x650 0x10>;
|
||||
interrupts = <1 14 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
timer@660 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
cell-index = <6>;
|
||||
reg = <660 10>;
|
||||
interrupts = <1 f 0>;
|
||||
reg = <0x660 0x10>;
|
||||
interrupts = <1 15 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
timer@670 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
cell-index = <7>;
|
||||
reg = <670 10>;
|
||||
interrupts = <1 10 0>;
|
||||
reg = <0x670 0x10>;
|
||||
interrupts = <1 16 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
rtc@800 { // Real time clock
|
||||
compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
|
||||
device_type = "rtc";
|
||||
reg = <800 100>;
|
||||
reg = <0x800 0x100>;
|
||||
interrupts = <1 5 0 1 6 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
@ -143,43 +139,43 @@
|
|||
can@900 {
|
||||
compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
|
||||
cell-index = <0>;
|
||||
interrupts = <2 11 0>;
|
||||
interrupts = <2 17 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
reg = <900 80>;
|
||||
reg = <0x900 0x80>;
|
||||
};
|
||||
|
||||
can@980 {
|
||||
compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
|
||||
cell-index = <1>;
|
||||
interrupts = <2 12 0>;
|
||||
interrupts = <2 18 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
reg = <980 80>;
|
||||
reg = <0x980 0x80>;
|
||||
};
|
||||
|
||||
gpio@b00 {
|
||||
compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
|
||||
reg = <b00 40>;
|
||||
reg = <0xb00 0x40>;
|
||||
interrupts = <1 7 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
gpio@c00 {
|
||||
compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
|
||||
reg = <c00 40>;
|
||||
reg = <0xc00 0x40>;
|
||||
interrupts = <1 8 0 0 3 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
spi@f00 {
|
||||
compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
|
||||
reg = <f00 20>;
|
||||
interrupts = <2 d 0 2 e 0>;
|
||||
reg = <0xf00 0x20>;
|
||||
interrupts = <2 13 0 2 14 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
usb@1000 {
|
||||
compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
|
||||
reg = <1000 ff>;
|
||||
reg = <0x1000 0xff>;
|
||||
interrupts = <2 6 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
@ -187,17 +183,17 @@
|
|||
dma-controller@1200 {
|
||||
device_type = "dma-controller";
|
||||
compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
|
||||
reg = <1200 80>;
|
||||
reg = <0x1200 0x80>;
|
||||
interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
|
||||
3 4 0 3 5 0 3 6 0 3 7 0
|
||||
3 8 0 3 9 0 3 a 0 3 b 0
|
||||
3 c 0 3 d 0 3 e 0 3 f 0>;
|
||||
3 8 0 3 9 0 3 10 0 3 11 0
|
||||
3 12 0 3 13 0 3 14 0 3 15 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
xlb@1f00 {
|
||||
compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
|
||||
reg = <1f00 100>;
|
||||
reg = <0x1f00 0x100>;
|
||||
};
|
||||
|
||||
serial@2000 { // PSC1
|
||||
|
@ -205,7 +201,7 @@
|
|||
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||
port-number = <0>; // Logical port assignment
|
||||
cell-index = <0>;
|
||||
reg = <2000 100>;
|
||||
reg = <0x2000 0x100>;
|
||||
interrupts = <2 1 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
@ -214,7 +210,7 @@
|
|||
//ac97@2200 { // PSC2
|
||||
// compatible = "fsl,mpc5200b-psc-ac97","fsl,mpc5200-psc-ac97";
|
||||
// cell-index = <1>;
|
||||
// reg = <2200 100>;
|
||||
// reg = <0x2200 0x100>;
|
||||
// interrupts = <2 2 0>;
|
||||
// interrupt-parent = <&mpc5200_pic>;
|
||||
//};
|
||||
|
@ -223,7 +219,7 @@
|
|||
//i2s@2400 { // PSC3
|
||||
// compatible = "fsl,mpc5200b-psc-i2s"; //not 5200 compatible
|
||||
// cell-index = <2>;
|
||||
// reg = <2400 100>;
|
||||
// reg = <0x2400 0x100>;
|
||||
// interrupts = <2 3 0>;
|
||||
// interrupt-parent = <&mpc5200_pic>;
|
||||
//};
|
||||
|
@ -233,8 +229,8 @@
|
|||
// device_type = "serial";
|
||||
// compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||
// cell-index = <3>;
|
||||
// reg = <2600 100>;
|
||||
// interrupts = <2 b 0>;
|
||||
// reg = <0x2600 0x100>;
|
||||
// interrupts = <2 11 0>;
|
||||
// interrupt-parent = <&mpc5200_pic>;
|
||||
//};
|
||||
|
||||
|
@ -243,8 +239,8 @@
|
|||
// device_type = "serial";
|
||||
// compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||
// cell-index = <4>;
|
||||
// reg = <2800 100>;
|
||||
// interrupts = <2 c 0>;
|
||||
// reg = <0x2800 0x100>;
|
||||
// interrupts = <2 12 0>;
|
||||
// interrupt-parent = <&mpc5200_pic>;
|
||||
//};
|
||||
|
||||
|
@ -252,7 +248,7 @@
|
|||
//spi@2c00 { // PSC6
|
||||
// compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi";
|
||||
// cell-index = <5>;
|
||||
// reg = <2c00 100>;
|
||||
// reg = <0x2c00 0x100>;
|
||||
// interrupts = <2 4 0>;
|
||||
// interrupt-parent = <&mpc5200_pic>;
|
||||
//};
|
||||
|
@ -260,7 +256,7 @@
|
|||
ethernet@3000 {
|
||||
device_type = "network";
|
||||
compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
|
||||
reg = <3000 400>;
|
||||
reg = <0x3000 0x400>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <2 5 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
|
@ -271,11 +267,11 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,mpc5200b-mdio", "fsl,mpc5200-mdio";
|
||||
reg = <3000 400>; // fec range, since we need to setup fec interrupts
|
||||
reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
|
||||
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
|
||||
phy0:ethernet-phy@0 {
|
||||
phy0: ethernet-phy@0 {
|
||||
device_type = "ethernet-phy";
|
||||
reg = <0>;
|
||||
};
|
||||
|
@ -284,7 +280,7 @@
|
|||
ata@3a00 {
|
||||
device_type = "ata";
|
||||
compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
|
||||
reg = <3a00 100>;
|
||||
reg = <0x3a00 0x100>;
|
||||
interrupts = <2 7 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
@ -294,8 +290,8 @@
|
|||
#size-cells = <0>;
|
||||
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
|
||||
cell-index = <0>;
|
||||
reg = <3d00 40>;
|
||||
interrupts = <2 f 0>;
|
||||
reg = <0x3d00 0x40>;
|
||||
interrupts = <2 15 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
fsl5200-clocking;
|
||||
};
|
||||
|
@ -305,14 +301,14 @@
|
|||
#size-cells = <0>;
|
||||
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
|
||||
cell-index = <1>;
|
||||
reg = <3d40 40>;
|
||||
interrupts = <2 10 0>;
|
||||
reg = <0x3d40 0x40>;
|
||||
interrupts = <2 16 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
fsl5200-clocking;
|
||||
};
|
||||
sram@8000 {
|
||||
compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram","sram";
|
||||
reg = <8000 4000>;
|
||||
reg = <0x8000 0x4000>;
|
||||
};
|
||||
};
|
||||
|
||||
|
@ -322,23 +318,23 @@
|
|||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
|
||||
reg = <f0000d00 100>;
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
|
||||
c000 0 0 2 &mpc5200_pic 1 1 3
|
||||
c000 0 0 3 &mpc5200_pic 1 2 3
|
||||
c000 0 0 4 &mpc5200_pic 1 3 3
|
||||
reg = <0xf0000d00 0x100>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
|
||||
0xc000 0 0 2 &mpc5200_pic 1 1 3
|
||||
0xc000 0 0 3 &mpc5200_pic 1 2 3
|
||||
0xc000 0 0 4 &mpc5200_pic 1 3 3
|
||||
|
||||
c800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot
|
||||
c800 0 0 2 &mpc5200_pic 1 2 3
|
||||
c800 0 0 3 &mpc5200_pic 1 3 3
|
||||
c800 0 0 4 &mpc5200_pic 0 0 3>;
|
||||
0xc800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot
|
||||
0xc800 0 0 2 &mpc5200_pic 1 2 3
|
||||
0xc800 0 0 3 &mpc5200_pic 1 3 3
|
||||
0xc800 0 0 4 &mpc5200_pic 0 0 3>;
|
||||
clock-frequency = <0>; // From boot loader
|
||||
interrupts = <2 8 0 2 9 0 2 a 0>;
|
||||
interrupts = <2 8 0 2 9 0 2 10 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <42000000 0 80000000 80000000 0 20000000
|
||||
02000000 0 a0000000 a0000000 0 10000000
|
||||
01000000 0 00000000 b0000000 0 01000000>;
|
||||
ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
|
||||
0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
|
||||
0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -10,6 +10,8 @@
|
|||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "promess,motionpro";
|
||||
compatible = "promess,motionpro";
|
||||
|
@ -23,10 +25,10 @@
|
|||
PowerPC,5200@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <20>;
|
||||
i-cache-line-size = <20>;
|
||||
d-cache-size = <4000>; // L1, 16K
|
||||
i-cache-size = <4000>; // L1, 16K
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-size = <0x4000>; // L1, 16K
|
||||
i-cache-size = <0x4000>; // L1, 16K
|
||||
timebase-frequency = <0>; // from bootloader
|
||||
bus-frequency = <0>; // from bootloader
|
||||
clock-frequency = <0>; // from bootloader
|
||||
|
@ -35,21 +37,21 @@
|
|||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <00000000 04000000>; // 64MB
|
||||
reg = <0x00000000 0x04000000>; // 64MB
|
||||
};
|
||||
|
||||
soc5200@f0000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc5200b-immr";
|
||||
ranges = <0 f0000000 0000c000>;
|
||||
reg = <f0000000 00000100>;
|
||||
ranges = <0 0xf0000000 0x0000c000>;
|
||||
reg = <0xf0000000 0x00000100>;
|
||||
bus-frequency = <0>; // from bootloader
|
||||
system-frequency = <0>; // from bootloader
|
||||
|
||||
cdm@200 {
|
||||
compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
|
||||
reg = <200 38>;
|
||||
reg = <0x200 0x38>;
|
||||
};
|
||||
|
||||
mpc5200_pic: interrupt-controller@500 {
|
||||
|
@ -57,12 +59,12 @@
|
|||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
|
||||
reg = <500 80>;
|
||||
reg = <0x500 0x80>;
|
||||
};
|
||||
|
||||
timer@600 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
reg = <600 10>;
|
||||
reg = <0x600 0x10>;
|
||||
interrupts = <1 9 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
fsl,has-wdt;
|
||||
|
@ -70,118 +72,118 @@
|
|||
|
||||
timer@610 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
reg = <610 10>;
|
||||
interrupts = <1 a 0>;
|
||||
reg = <0x610 0x10>;
|
||||
interrupts = <1 10 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
timer@620 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
reg = <620 10>;
|
||||
interrupts = <1 b 0>;
|
||||
reg = <0x620 0x10>;
|
||||
interrupts = <1 11 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
timer@630 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
reg = <630 10>;
|
||||
interrupts = <1 c 0>;
|
||||
reg = <0x630 0x10>;
|
||||
interrupts = <1 12 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
timer@640 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
reg = <640 10>;
|
||||
interrupts = <1 d 0>;
|
||||
reg = <0x640 0x10>;
|
||||
interrupts = <1 13 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
timer@650 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
reg = <650 10>;
|
||||
interrupts = <1 e 0>;
|
||||
reg = <0x650 0x10>;
|
||||
interrupts = <1 14 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
motionpro-led@660 { // Motion-PRO status LED
|
||||
compatible = "promess,motionpro-led";
|
||||
label = "motionpro-statusled";
|
||||
reg = <660 10>;
|
||||
interrupts = <1 f 0>;
|
||||
reg = <0x660 0x10>;
|
||||
interrupts = <1 15 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
blink-delay = <64>; // 100 msec
|
||||
blink-delay = <100>; // 100 msec
|
||||
};
|
||||
|
||||
motionpro-led@670 { // Motion-PRO ready LED
|
||||
compatible = "promess,motionpro-led";
|
||||
label = "motionpro-readyled";
|
||||
reg = <670 10>;
|
||||
interrupts = <1 10 0>;
|
||||
reg = <0x670 0x10>;
|
||||
interrupts = <1 16 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
rtc@800 { // Real time clock
|
||||
compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
|
||||
reg = <800 100>;
|
||||
reg = <0x800 0x100>;
|
||||
interrupts = <1 5 0 1 6 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
mscan@980 {
|
||||
can@980 {
|
||||
compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
|
||||
interrupts = <2 12 0>;
|
||||
interrupts = <2 18 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
reg = <980 80>;
|
||||
reg = <0x980 0x80>;
|
||||
};
|
||||
|
||||
gpio@b00 {
|
||||
compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
|
||||
reg = <b00 40>;
|
||||
reg = <0xb00 0x40>;
|
||||
interrupts = <1 7 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
gpio@c00 {
|
||||
compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
|
||||
reg = <c00 40>;
|
||||
reg = <0xc00 0x40>;
|
||||
interrupts = <1 8 0 0 3 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
spi@f00 {
|
||||
compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
|
||||
reg = <f00 20>;
|
||||
interrupts = <2 d 0 2 e 0>;
|
||||
reg = <0xf00 0x20>;
|
||||
interrupts = <2 13 0 2 14 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
usb@1000 {
|
||||
compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
|
||||
reg = <1000 ff>;
|
||||
reg = <0x1000 0xff>;
|
||||
interrupts = <2 6 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
dma-controller@1200 {
|
||||
compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
|
||||
reg = <1200 80>;
|
||||
reg = <0x1200 0x80>;
|
||||
interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
|
||||
3 4 0 3 5 0 3 6 0 3 7 0
|
||||
3 8 0 3 9 0 3 a 0 3 b 0
|
||||
3 c 0 3 d 0 3 e 0 3 f 0>;
|
||||
3 8 0 3 9 0 3 10 0 3 11 0
|
||||
3 12 0 3 13 0 3 14 0 3 15 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
xlb@1f00 {
|
||||
compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
|
||||
reg = <1f00 100>;
|
||||
reg = <0x1f00 0x100>;
|
||||
};
|
||||
|
||||
serial@2000 { // PSC1
|
||||
device_type = "serial";
|
||||
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||
port-number = <0>; // Logical port assignment
|
||||
reg = <2000 100>;
|
||||
reg = <0x2000 0x100>;
|
||||
interrupts = <2 1 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
@ -190,7 +192,7 @@
|
|||
spi@2200 { // PSC2
|
||||
compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi";
|
||||
cell-index = <1>;
|
||||
reg = <2200 100>;
|
||||
reg = <0x2200 0x100>;
|
||||
interrupts = <2 2 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
@ -200,15 +202,15 @@
|
|||
device_type = "serial";
|
||||
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||
port-number = <4>; // Logical port assignment
|
||||
reg = <2800 100>;
|
||||
interrupts = <2 c 0>;
|
||||
reg = <0x2800 0x100>;
|
||||
interrupts = <2 12 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
ethernet@3000 {
|
||||
device_type = "network";
|
||||
compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
|
||||
reg = <3000 400>;
|
||||
reg = <0x3000 0x400>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <2 5 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
|
@ -219,7 +221,7 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
|
||||
reg = <3000 400>; // fec range, since we need to setup fec interrupts
|
||||
reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
|
||||
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
|
||||
|
@ -231,7 +233,7 @@
|
|||
|
||||
ata@3a00 {
|
||||
compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
|
||||
reg = <3a00 100>;
|
||||
reg = <0x3a00 0x100>;
|
||||
interrupts = <2 7 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
@ -240,21 +242,21 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
|
||||
reg = <3d40 40>;
|
||||
interrupts = <2 10 0>;
|
||||
reg = <0x3d40 0x40>;
|
||||
interrupts = <2 16 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
fsl5200-clocking;
|
||||
|
||||
rtc@68 {
|
||||
device_type = "rtc";
|
||||
compatible = "dallas,ds1339";
|
||||
reg = <68>;
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
sram@8000 {
|
||||
compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
|
||||
reg = <8000 4000>;
|
||||
reg = <0x8000 0x4000>;
|
||||
};
|
||||
};
|
||||
|
||||
|
@ -262,15 +264,15 @@
|
|||
compatible = "fsl,lpb";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 ff000000 01000000
|
||||
1 0 50000000 00010000
|
||||
2 0 50010000 00010000
|
||||
3 0 50020000 00010000>;
|
||||
ranges = <0 0 0xff000000 0x01000000
|
||||
1 0 0x50000000 0x00010000
|
||||
2 0 0x50010000 0x00010000
|
||||
3 0 0x50020000 0x00010000>;
|
||||
|
||||
// 8-bit DualPort SRAM on LocalPlus Bus CS1
|
||||
kollmorgen@1,0 {
|
||||
compatible = "promess,motionpro-kollmorgen";
|
||||
reg = <1 0 10000>;
|
||||
reg = <1 0 0x10000>;
|
||||
interrupts = <1 1 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
@ -278,13 +280,13 @@
|
|||
// 8-bit board CPLD on LocalPlus Bus CS2
|
||||
cpld@2,0 {
|
||||
compatible = "promess,motionpro-cpld";
|
||||
reg = <2 0 10000>;
|
||||
reg = <2 0 0x10000>;
|
||||
};
|
||||
|
||||
// 8-bit custom Anybus Module on LocalPlus Bus CS3
|
||||
anybus@3,0 {
|
||||
compatible = "promess,motionpro-anybus";
|
||||
reg = <3 0 10000>;
|
||||
reg = <3 0 0x10000>;
|
||||
};
|
||||
pro_module_general@3,0 {
|
||||
compatible = "promess,pro_module_general";
|
||||
|
@ -292,13 +294,13 @@
|
|||
};
|
||||
pro_module_dio@3,800 {
|
||||
compatible = "promess,pro_module_dio";
|
||||
reg = <3 800 2>;
|
||||
reg = <3 0x800 2>;
|
||||
};
|
||||
|
||||
// 16-bit flash device at LocalPlus Bus CS0
|
||||
flash@0,0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0 01000000>;
|
||||
reg = <0 0 0x01000000>;
|
||||
bank-width = <2>;
|
||||
device-width = <2>;
|
||||
#size-cells = <1>;
|
||||
|
|
|
@ -0,0 +1,363 @@
|
|||
/*
|
||||
* phyCORE-MPC5200B-tiny (pcm030) board Device Tree Source
|
||||
*
|
||||
* Copyright 2006 Pengutronix
|
||||
* Sascha Hauer <s.hauer@pengutronix.de>
|
||||
* Copyright 2007 Pengutronix
|
||||
* Juergen Beisert <j.beisert@pengutronix.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "phytec,pcm030";
|
||||
compatible = "phytec,pcm030";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,5200@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-size = <0x4000>; /* L1, 16K */
|
||||
i-cache-size = <0x4000>; /* L1, 16K */
|
||||
timebase-frequency = <0>; /* From Bootloader */
|
||||
bus-frequency = <0>; /* From Bootloader */
|
||||
clock-frequency = <0>; /* From Bootloader */
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x04000000>; /* 64MB */
|
||||
};
|
||||
|
||||
soc5200@f0000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc5200b-immr";
|
||||
ranges = <0x0 0xf0000000 0x0000c000>;
|
||||
bus-frequency = <0>; /* From bootloader */
|
||||
system-frequency = <0>; /* From bootloader */
|
||||
|
||||
cdm@200 {
|
||||
compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
|
||||
reg = <0x200 0x38>;
|
||||
};
|
||||
|
||||
mpc5200_pic: interrupt-controller@500 {
|
||||
/* 5200 interrupts are encoded into two levels; */
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
device_type = "interrupt-controller";
|
||||
compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
|
||||
reg = <0x500 0x80>;
|
||||
};
|
||||
|
||||
timer@600 { /* General Purpose Timer */
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
cell-index = <0>;
|
||||
reg = <0x600 0x10>;
|
||||
interrupts = <0x1 0x9 0x0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
fsl,has-wdt;
|
||||
};
|
||||
|
||||
timer@610 { /* General Purpose Timer */
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
cell-index = <1>;
|
||||
reg = <0x610 0x10>;
|
||||
interrupts = <0x1 0xa 0x0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
gpt2: timer@620 { /* General Purpose Timer in GPIO mode */
|
||||
compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
|
||||
cell-index = <2>;
|
||||
reg = <0x620 0x10>;
|
||||
interrupts = <0x1 0xb 0x0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpt3: timer@630 { /* General Purpose Timer in GPIO mode */
|
||||
compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
|
||||
cell-index = <3>;
|
||||
reg = <0x630 0x10>;
|
||||
interrupts = <0x1 0xc 0x0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpt4: timer@640 { /* General Purpose Timer in GPIO mode */
|
||||
compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
|
||||
cell-index = <4>;
|
||||
reg = <0x640 0x10>;
|
||||
interrupts = <0x1 0xd 0x0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpt5: timer@650 { /* General Purpose Timer in GPIO mode */
|
||||
compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
|
||||
cell-index = <5>;
|
||||
reg = <0x650 0x10>;
|
||||
interrupts = <0x1 0xe 0x0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpt6: timer@660 { /* General Purpose Timer in GPIO mode */
|
||||
compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
|
||||
cell-index = <6>;
|
||||
reg = <0x660 0x10>;
|
||||
interrupts = <0x1 0xf 0x0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpt7: timer@670 { /* General Purpose Timer in GPIO mode */
|
||||
compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
|
||||
cell-index = <7>;
|
||||
reg = <0x670 0x10>;
|
||||
interrupts = <0x1 0x10 0x0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
rtc@800 { // Real time clock
|
||||
compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
|
||||
device_type = "rtc";
|
||||
reg = <0x800 0x100>;
|
||||
interrupts = <0x1 0x5 0x0 0x1 0x6 0x0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
can@900 {
|
||||
compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
|
||||
cell-index = <0>;
|
||||
interrupts = <0x2 0x11 0x0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
reg = <0x900 0x80>;
|
||||
};
|
||||
|
||||
can@980 {
|
||||
compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
|
||||
cell-index = <1>;
|
||||
interrupts = <0x2 0x12 0x0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
reg = <0x980 0x80>;
|
||||
};
|
||||
|
||||
gpio_simple: gpio@b00 {
|
||||
compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
|
||||
reg = <0xb00 0x40>;
|
||||
interrupts = <0x1 0x7 0x0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpio_wkup: gpio-wkup@c00 {
|
||||
compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
|
||||
reg = <0xc00 0x40>;
|
||||
interrupts = <0x1 0x8 0x0 0x0 0x3 0x0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
spi@f00 {
|
||||
compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
|
||||
reg = <0xf00 0x20>;
|
||||
interrupts = <0x2 0xd 0x0 0x2 0xe 0x0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
usb@1000 {
|
||||
compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
|
||||
reg = <0x1000 0xff>;
|
||||
interrupts = <0x2 0x6 0x0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
dma-controller@1200 {
|
||||
device_type = "dma-controller";
|
||||
compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
|
||||
reg = <0x1200 0x80>;
|
||||
interrupts = <0x3 0x0 0x0 0x3 0x1 0x0 0x3 0x2 0x0 0x3 0x3 0x0
|
||||
0x3 0x4 0x0 0x3 0x5 0x0 0x3 0x6 0x0 0x3 0x7 0x0
|
||||
0x3 0x8 0x0 0x3 0x9 0x0 0x3 0xa 0x0 0x3 0xb 0x0
|
||||
0x3 0xc 0x0 0x3 0xd 0x0 0x3 0xe 0x0 0x3 0xf 0x0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
xlb@1f00 {
|
||||
compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
|
||||
reg = <0x1f00 0x100>;
|
||||
};
|
||||
|
||||
ac97@2000 { /* PSC1 in ac97 mode */
|
||||
device_type = "sound";
|
||||
compatible = "mpc5200b-psc-ac97","fsl,mpc5200b-psc-ac97";
|
||||
cell-index = <0>;
|
||||
reg = <0x2000 0x100>;
|
||||
interrupts = <0x2 0x2 0x0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
/* PSC2 port is used by CAN1/2 */
|
||||
|
||||
serial@2400 { /* PSC3 in UART mode */
|
||||
device_type = "serial";
|
||||
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||
port-number = <0>;
|
||||
cell-index = <2>;
|
||||
reg = <0x2400 0x100>;
|
||||
interrupts = <0x2 0x3 0x0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
/* PSC4 is ??? */
|
||||
|
||||
/* PSC5 is ??? */
|
||||
|
||||
serial@2c00 { /* PSC6 in UART mode */
|
||||
device_type = "serial";
|
||||
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||
port-number = <1>;
|
||||
cell-index = <5>;
|
||||
reg = <0x2c00 0x100>;
|
||||
interrupts = <0x2 0x4 0x0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
ethernet@3000 {
|
||||
device_type = "network";
|
||||
compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
|
||||
reg = <0x3000 0x400>;
|
||||
local-mac-address = [00 00 00 00 00 00];
|
||||
interrupts = <0x2 0x5 0x0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
phy-handle = <&phy0>;
|
||||
};
|
||||
|
||||
mdio@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,mpc5200b-mdio", "fsl,mpc5200-mdio";
|
||||
reg = <0x3000 0x400>; /* fec range, since we need to setup fec interrupts */
|
||||
interrupts = <0x2 0x5 0x0>; /* these are for "mii command finished", not link changes & co. */
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
|
||||
phy0:ethernet-phy@0 {
|
||||
device_type = "ethernet-phy";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
ata@3a00 {
|
||||
device_type = "ata";
|
||||
compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
|
||||
reg = <0x3a00 0x100>;
|
||||
interrupts = <0x2 0x7 0x0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
i2c@3d00 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
|
||||
cell-index = <0>;
|
||||
reg = <0x3d00 0x40>;
|
||||
interrupts = <0x2 0xf 0x0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
fsl5200-clocking;
|
||||
};
|
||||
|
||||
i2c@3d40 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
|
||||
cell-index = <1>;
|
||||
reg = <0x3d40 0x40>;
|
||||
interrupts = <0x2 0x10 0x0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
fsl5200-clocking;
|
||||
rtc@51 {
|
||||
device_type = "rtc";
|
||||
compatible = "nxp,pcf8563";
|
||||
reg = <0x51>;
|
||||
};
|
||||
/* FIXME: EEPROM */
|
||||
};
|
||||
|
||||
sram@8000 {
|
||||
compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram","sram";
|
||||
reg = <0x8000 0x4000>;
|
||||
};
|
||||
|
||||
/* This is only an example device to show the usage of gpios. It maps all available
|
||||
* gpios to the "gpio-provider" device.
|
||||
*/
|
||||
gpio {
|
||||
compatible = "gpio-provider";
|
||||
|
||||
/* mpc52xx exp.con patchfield */
|
||||
gpios = <&gpio_wkup 0 0 /* GPIO_WKUP_7 11d jp13-3 */
|
||||
&gpio_wkup 1 0 /* GPIO_WKUP_6 14c */
|
||||
&gpio_wkup 6 0 /* PSC2_4 43c x5-11 */
|
||||
&gpio_simple 2 0 /* IRDA_1 24c x7-6 set GPS_PORT_CONFIG[IRDA] = 0 */
|
||||
&gpio_simple 3 0 /* IRDA_0 x8-5 set GPS_PORT_CONFIG[IRDA] = 0 */
|
||||
&gpt2 0 0 /* timer2 12d x4-4 */
|
||||
&gpt3 0 0 /* timer3 13d x6-4 */
|
||||
&gpt4 0 0 /* timer4 61c x2-16 */
|
||||
&gpt5 0 0 /* timer5 44c x7-11 */
|
||||
&gpt6 0 0 /* timer6 60c x8-15 */
|
||||
&gpt7 0 0 /* timer7 36a x17-9 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
pci@f0000d00 {
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
|
||||
reg = <0xf0000d00 0x100>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <0xc000 0x0 0x0 0x1 &mpc5200_pic 0x0 0x0 0x3 /* 1st slot */
|
||||
0xc000 0x0 0x0 0x2 &mpc5200_pic 0x1 0x1 0x3
|
||||
0xc000 0x0 0x0 0x3 &mpc5200_pic 0x1 0x2 0x3
|
||||
0xc000 0x0 0x0 0x4 &mpc5200_pic 0x1 0x3 0x3
|
||||
|
||||
0xc800 0x0 0x0 0x1 &mpc5200_pic 0x1 0x1 0x3 /* 2nd slot */
|
||||
0xc800 0x0 0x0 0x2 &mpc5200_pic 0x1 0x2 0x3
|
||||
0xc800 0x0 0x0 0x3 &mpc5200_pic 0x1 0x3 0x3
|
||||
0xc800 0x0 0x0 0x4 &mpc5200_pic 0x0 0x0 0x3>;
|
||||
clock-frequency = <0>; // From boot loader
|
||||
interrupts = <0x2 0x8 0x0 0x2 0x9 0x0 0x2 0xa 0x0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x20000000
|
||||
0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
|
||||
0x01000000 0x0 0x00000000 0xb0000000 0x0 0x01000000>;
|
||||
};
|
||||
};
|
|
@ -10,6 +10,8 @@
|
|||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "tqc,tqm5200";
|
||||
compatible = "tqc,tqm5200";
|
||||
|
@ -23,10 +25,10 @@
|
|||
PowerPC,5200@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <20>;
|
||||
i-cache-line-size = <20>;
|
||||
d-cache-size = <4000>; // L1, 16K
|
||||
i-cache-size = <4000>; // L1, 16K
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-size = <0x4000>; // L1, 16K
|
||||
i-cache-size = <0x4000>; // L1, 16K
|
||||
timebase-frequency = <0>; // from bootloader
|
||||
bus-frequency = <0>; // from bootloader
|
||||
clock-frequency = <0>; // from bootloader
|
||||
|
@ -35,21 +37,21 @@
|
|||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <00000000 04000000>; // 64MB
|
||||
reg = <0x00000000 0x04000000>; // 64MB
|
||||
};
|
||||
|
||||
soc5200@f0000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc5200-immr";
|
||||
ranges = <0 f0000000 0000c000>;
|
||||
reg = <f0000000 00000100>;
|
||||
ranges = <0 0xf0000000 0x0000c000>;
|
||||
reg = <0xf0000000 0x00000100>;
|
||||
bus-frequency = <0>; // from bootloader
|
||||
system-frequency = <0>; // from bootloader
|
||||
|
||||
cdm@200 {
|
||||
compatible = "fsl,mpc5200-cdm";
|
||||
reg = <200 38>;
|
||||
reg = <0x200 0x38>;
|
||||
};
|
||||
|
||||
mpc5200_pic: interrupt-controller@500 {
|
||||
|
@ -57,12 +59,12 @@
|
|||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
compatible = "fsl,mpc5200-pic";
|
||||
reg = <500 80>;
|
||||
reg = <0x500 0x80>;
|
||||
};
|
||||
|
||||
timer@600 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200-gpt";
|
||||
reg = <600 10>;
|
||||
reg = <0x600 0x10>;
|
||||
interrupts = <1 9 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
fsl,has-wdt;
|
||||
|
@ -70,38 +72,38 @@
|
|||
|
||||
gpio@b00 {
|
||||
compatible = "fsl,mpc5200-gpio";
|
||||
reg = <b00 40>;
|
||||
reg = <0xb00 0x40>;
|
||||
interrupts = <1 7 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
usb@1000 {
|
||||
compatible = "fsl,mpc5200-ohci","ohci-be";
|
||||
reg = <1000 ff>;
|
||||
reg = <0x1000 0xff>;
|
||||
interrupts = <2 6 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
dma-controller@1200 {
|
||||
compatible = "fsl,mpc5200-bestcomm";
|
||||
reg = <1200 80>;
|
||||
reg = <0x1200 0x80>;
|
||||
interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
|
||||
3 4 0 3 5 0 3 6 0 3 7 0
|
||||
3 8 0 3 9 0 3 a 0 3 b 0
|
||||
3 c 0 3 d 0 3 e 0 3 f 0>;
|
||||
3 8 0 3 9 0 3 10 0 3 11 0
|
||||
3 12 0 3 13 0 3 14 0 3 15 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
xlb@1f00 {
|
||||
compatible = "fsl,mpc5200-xlb";
|
||||
reg = <1f00 100>;
|
||||
reg = <0x1f00 0x100>;
|
||||
};
|
||||
|
||||
serial@2000 { // PSC1
|
||||
device_type = "serial";
|
||||
compatible = "fsl,mpc5200-psc-uart";
|
||||
port-number = <0>; // Logical port assignment
|
||||
reg = <2000 100>;
|
||||
reg = <0x2000 0x100>;
|
||||
interrupts = <2 1 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
@ -110,7 +112,7 @@
|
|||
device_type = "serial";
|
||||
compatible = "fsl,mpc5200-psc-uart";
|
||||
port-number = <1>; // Logical port assignment
|
||||
reg = <2200 100>;
|
||||
reg = <0x2200 0x100>;
|
||||
interrupts = <2 2 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
@ -119,7 +121,7 @@
|
|||
device_type = "serial";
|
||||
compatible = "fsl,mpc5200-psc-uart";
|
||||
port-number = <2>; // Logical port assignment
|
||||
reg = <2400 100>;
|
||||
reg = <0x2400 0x100>;
|
||||
interrupts = <2 3 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
@ -127,7 +129,7 @@
|
|||
ethernet@3000 {
|
||||
device_type = "network";
|
||||
compatible = "fsl,mpc5200-fec";
|
||||
reg = <3000 400>;
|
||||
reg = <0x3000 0x400>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <2 5 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
|
@ -137,8 +139,8 @@
|
|||
mdio@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
|
||||
reg = <3000 400>; // fec range, since we need to setup fec interrupts
|
||||
compatible = "fsl,mpc5200-mdio";
|
||||
reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
|
||||
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
|
||||
|
@ -150,7 +152,7 @@
|
|||
|
||||
ata@3a00 {
|
||||
compatible = "fsl,mpc5200-ata";
|
||||
reg = <3a00 100>;
|
||||
reg = <0x3a00 0x100>;
|
||||
interrupts = <2 7 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
@ -159,21 +161,21 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,mpc5200-i2c","fsl-i2c";
|
||||
reg = <3d40 40>;
|
||||
interrupts = <2 10 0>;
|
||||
reg = <0x3d40 0x40>;
|
||||
interrupts = <2 16 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
fsl5200-clocking;
|
||||
|
||||
rtc@68 {
|
||||
device_type = "rtc";
|
||||
compatible = "dallas,ds1307";
|
||||
reg = <68>;
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
sram@8000 {
|
||||
compatible = "fsl,mpc5200-sram";
|
||||
reg = <8000 4000>;
|
||||
reg = <0x8000 0x4000>;
|
||||
};
|
||||
};
|
||||
|
||||
|
@ -182,11 +184,11 @@
|
|||
compatible = "fsl,lpb";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 fc000000 02000000>;
|
||||
ranges = <0 0 0xfc000000 0x02000000>;
|
||||
|
||||
flash@0,0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0 02000000>;
|
||||
reg = <0 0 0x02000000>;
|
||||
bank-width = <4>;
|
||||
device-width = <2>;
|
||||
#size-cells = <1>;
|
||||
|
@ -200,18 +202,18 @@
|
|||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
compatible = "fsl,mpc5200-pci";
|
||||
reg = <f0000d00 100>;
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3
|
||||
c000 0 0 2 &mpc5200_pic 0 0 3
|
||||
c000 0 0 3 &mpc5200_pic 0 0 3
|
||||
c000 0 0 4 &mpc5200_pic 0 0 3>;
|
||||
reg = <0xf0000d00 0x100>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3
|
||||
0xc000 0 0 2 &mpc5200_pic 0 0 3
|
||||
0xc000 0 0 3 &mpc5200_pic 0 0 3
|
||||
0xc000 0 0 4 &mpc5200_pic 0 0 3>;
|
||||
clock-frequency = <0>; // From boot loader
|
||||
interrupts = <2 8 0 2 9 0 2 a 0>;
|
||||
interrupts = <2 8 0 2 9 0 2 10 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <42000000 0 80000000 80000000 0 10000000
|
||||
02000000 0 90000000 90000000 0 10000000
|
||||
01000000 0 00000000 a0000000 0 01000000>;
|
||||
ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000
|
||||
0x02000000 0 0x90000000 0x90000000 0 0x10000000
|
||||
0x01000000 0 0x00000000 0xa0000000 0 0x01000000>;
|
||||
};
|
||||
};
|
||||
|
|
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
@ -74,20 +74,20 @@ void __init reserve_crashkernel(void)
|
|||
ret = parse_crashkernel(boot_command_line, lmb_phys_mem_size(),
|
||||
&crash_size, &crash_base);
|
||||
if (ret == 0 && crash_size > 0) {
|
||||
if (crash_base == 0)
|
||||
crash_base = KDUMP_KERNELBASE;
|
||||
crashk_res.start = crash_base;
|
||||
} else {
|
||||
/* handle the device tree */
|
||||
crash_size = crashk_res.end - crashk_res.start + 1;
|
||||
crashk_res.end = crash_base + crash_size - 1;
|
||||
}
|
||||
|
||||
if (crash_size == 0)
|
||||
if (crashk_res.end == crashk_res.start) {
|
||||
crashk_res.start = crashk_res.end = 0;
|
||||
return;
|
||||
}
|
||||
|
||||
/* We might have got these values via the command line or the
|
||||
* device tree, either way sanitise them now. */
|
||||
|
||||
crash_size = crashk_res.end - crashk_res.start + 1;
|
||||
|
||||
if (crashk_res.start != KDUMP_KERNELBASE)
|
||||
printk("Crash kernel location must be 0x%x\n",
|
||||
KDUMP_KERNELBASE);
|
||||
|
|
|
@ -487,9 +487,12 @@ static void __init emergency_stack_init(void)
|
|||
*/
|
||||
limit = min(0x10000000UL, lmb.rmo_size);
|
||||
|
||||
for_each_possible_cpu(i)
|
||||
paca[i].emergency_sp =
|
||||
__va(lmb_alloc_base(HW_PAGE_SIZE, 128, limit)) + HW_PAGE_SIZE;
|
||||
for_each_possible_cpu(i) {
|
||||
unsigned long sp;
|
||||
sp = lmb_alloc_base(THREAD_SIZE, THREAD_SIZE, limit);
|
||||
sp += THREAD_SIZE;
|
||||
paca[i].emergency_sp = __va(sp);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
@ -44,3 +44,9 @@ config PPC_MPC5200_BUGFIX
|
|||
|
||||
It is safe to say 'Y' here
|
||||
|
||||
config PPC_MPC5200_GPIO
|
||||
bool "MPC5200 GPIO support"
|
||||
depends on PPC_MPC52xx
|
||||
select HAVE_GPIO_LIB
|
||||
help
|
||||
Enable gpiolib support for mpc5200 based boards
|
||||
|
|
|
@ -14,3 +14,5 @@ obj-$(CONFIG_PM) += mpc52xx_sleep.o mpc52xx_pm.o
|
|||
ifeq ($(CONFIG_PPC_LITE5200),y)
|
||||
obj-$(CONFIG_PM) += lite5200_sleep.o lite5200_pm.o
|
||||
endif
|
||||
|
||||
obj-$(CONFIG_PPC_MPC5200_GPIO) += mpc52xx_gpio.o
|
|
@ -51,6 +51,7 @@ static void __init mpc5200_simple_setup_arch(void)
|
|||
/* list of the supported boards */
|
||||
static char *board[] __initdata = {
|
||||
"promess,motionpro",
|
||||
"phytec,pcm030",
|
||||
"schindler,cm5200",
|
||||
"tqc,tqm5200",
|
||||
NULL
|
||||
|
|
|
@ -0,0 +1,465 @@
|
|||
/*
|
||||
* MPC52xx gpio driver
|
||||
*
|
||||
* Copyright (c) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2
|
||||
* as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <linux/of.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/of_gpio.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/of_platform.h>
|
||||
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/mpc52xx.h>
|
||||
#include <sysdev/fsl_soc.h>
|
||||
|
||||
static DEFINE_SPINLOCK(gpio_lock);
|
||||
|
||||
struct mpc52xx_gpiochip {
|
||||
struct of_mm_gpio_chip mmchip;
|
||||
unsigned int shadow_dvo;
|
||||
unsigned int shadow_gpioe;
|
||||
unsigned int shadow_ddr;
|
||||
};
|
||||
|
||||
/*
|
||||
* GPIO LIB API implementation for wakeup GPIOs.
|
||||
*
|
||||
* There's a maximum of 8 wakeup GPIOs. Which of these are available
|
||||
* for use depends on your board setup.
|
||||
*
|
||||
* 0 -> GPIO_WKUP_7
|
||||
* 1 -> GPIO_WKUP_6
|
||||
* 2 -> PSC6_1
|
||||
* 3 -> PSC6_0
|
||||
* 4 -> ETH_17
|
||||
* 5 -> PSC3_9
|
||||
* 6 -> PSC2_4
|
||||
* 7 -> PSC1_4
|
||||
*
|
||||
*/
|
||||
static int mpc52xx_wkup_gpio_get(struct gpio_chip *gc, unsigned int gpio)
|
||||
{
|
||||
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
|
||||
struct mpc52xx_gpio_wkup __iomem *regs = mm_gc->regs;
|
||||
unsigned int ret;
|
||||
|
||||
ret = (in_8(®s->wkup_ival) >> (7 - gpio)) & 1;
|
||||
|
||||
pr_debug("%s: gpio: %d ret: %d\n", __func__, gpio, ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static inline void
|
||||
__mpc52xx_wkup_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
|
||||
{
|
||||
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
|
||||
struct mpc52xx_gpiochip *chip = container_of(mm_gc,
|
||||
struct mpc52xx_gpiochip, mmchip);
|
||||
struct mpc52xx_gpio_wkup __iomem *regs = mm_gc->regs;
|
||||
|
||||
if (val)
|
||||
chip->shadow_dvo |= 1 << (7 - gpio);
|
||||
else
|
||||
chip->shadow_dvo &= ~(1 << (7 - gpio));
|
||||
|
||||
out_8(®s->wkup_dvo, chip->shadow_dvo);
|
||||
}
|
||||
|
||||
static void
|
||||
mpc52xx_wkup_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&gpio_lock, flags);
|
||||
|
||||
__mpc52xx_wkup_gpio_set(gc, gpio, val);
|
||||
|
||||
spin_unlock_irqrestore(&gpio_lock, flags);
|
||||
|
||||
pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val);
|
||||
}
|
||||
|
||||
static int mpc52xx_wkup_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
|
||||
{
|
||||
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
|
||||
struct mpc52xx_gpiochip *chip = container_of(mm_gc,
|
||||
struct mpc52xx_gpiochip, mmchip);
|
||||
struct mpc52xx_gpio_wkup *regs = mm_gc->regs;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&gpio_lock, flags);
|
||||
|
||||
/* set the direction */
|
||||
chip->shadow_ddr &= ~(1 << (7 - gpio));
|
||||
out_8(®s->wkup_ddr, chip->shadow_ddr);
|
||||
|
||||
/* and enable the pin */
|
||||
chip->shadow_gpioe |= 1 << (7 - gpio);
|
||||
out_8(®s->wkup_gpioe, chip->shadow_gpioe);
|
||||
|
||||
spin_unlock_irqrestore(&gpio_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
mpc52xx_wkup_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
|
||||
{
|
||||
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
|
||||
struct mpc52xx_gpio_wkup *regs = mm_gc->regs;
|
||||
struct mpc52xx_gpiochip *chip = container_of(mm_gc,
|
||||
struct mpc52xx_gpiochip, mmchip);
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&gpio_lock, flags);
|
||||
|
||||
__mpc52xx_wkup_gpio_set(gc, gpio, val);
|
||||
|
||||
/* Then set direction */
|
||||
chip->shadow_ddr |= 1 << (7 - gpio);
|
||||
out_8(®s->wkup_ddr, chip->shadow_ddr);
|
||||
|
||||
/* Finally enable the pin */
|
||||
chip->shadow_gpioe |= 1 << (7 - gpio);
|
||||
out_8(®s->wkup_gpioe, chip->shadow_gpioe);
|
||||
|
||||
spin_unlock_irqrestore(&gpio_lock, flags);
|
||||
|
||||
pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __devinit mpc52xx_wkup_gpiochip_probe(struct of_device *ofdev,
|
||||
const struct of_device_id *match)
|
||||
{
|
||||
struct mpc52xx_gpiochip *chip;
|
||||
struct mpc52xx_gpio_wkup *regs;
|
||||
struct of_gpio_chip *ofchip;
|
||||
int ret;
|
||||
|
||||
chip = kzalloc(sizeof(*chip), GFP_KERNEL);
|
||||
if (!chip)
|
||||
return -ENOMEM;
|
||||
|
||||
ofchip = &chip->mmchip.of_gc;
|
||||
|
||||
ofchip->gpio_cells = 2;
|
||||
ofchip->gc.ngpio = 8;
|
||||
ofchip->gc.direction_input = mpc52xx_wkup_gpio_dir_in;
|
||||
ofchip->gc.direction_output = mpc52xx_wkup_gpio_dir_out;
|
||||
ofchip->gc.get = mpc52xx_wkup_gpio_get;
|
||||
ofchip->gc.set = mpc52xx_wkup_gpio_set;
|
||||
|
||||
ret = of_mm_gpiochip_add(ofdev->node, &chip->mmchip);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
regs = chip->mmchip.regs;
|
||||
chip->shadow_gpioe = in_8(®s->wkup_gpioe);
|
||||
chip->shadow_ddr = in_8(®s->wkup_ddr);
|
||||
chip->shadow_dvo = in_8(®s->wkup_dvo);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mpc52xx_gpiochip_remove(struct of_device *ofdev)
|
||||
{
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
static const struct of_device_id mpc52xx_wkup_gpiochip_match[] = {
|
||||
{
|
||||
.compatible = "fsl,mpc5200-gpio-wkup",
|
||||
},
|
||||
{}
|
||||
};
|
||||
|
||||
static struct of_platform_driver mpc52xx_wkup_gpiochip_driver = {
|
||||
.name = "gpio_wkup",
|
||||
.match_table = mpc52xx_wkup_gpiochip_match,
|
||||
.probe = mpc52xx_wkup_gpiochip_probe,
|
||||
.remove = mpc52xx_gpiochip_remove,
|
||||
};
|
||||
|
||||
/*
|
||||
* GPIO LIB API implementation for simple GPIOs
|
||||
*
|
||||
* There's a maximum of 32 simple GPIOs. Which of these are available
|
||||
* for use depends on your board setup.
|
||||
* The numbering reflects the bit numbering in the port registers:
|
||||
*
|
||||
* 0..1 > reserved
|
||||
* 2..3 > IRDA
|
||||
* 4..7 > ETHR
|
||||
* 8..11 > reserved
|
||||
* 12..15 > USB
|
||||
* 16..17 > reserved
|
||||
* 18..23 > PSC3
|
||||
* 24..27 > PSC2
|
||||
* 28..31 > PSC1
|
||||
*/
|
||||
static int mpc52xx_simple_gpio_get(struct gpio_chip *gc, unsigned int gpio)
|
||||
{
|
||||
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
|
||||
struct mpc52xx_gpio __iomem *regs = mm_gc->regs;
|
||||
unsigned int ret;
|
||||
|
||||
ret = (in_be32(®s->simple_ival) >> (31 - gpio)) & 1;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static inline void
|
||||
__mpc52xx_simple_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
|
||||
{
|
||||
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
|
||||
struct mpc52xx_gpiochip *chip = container_of(mm_gc,
|
||||
struct mpc52xx_gpiochip, mmchip);
|
||||
struct mpc52xx_gpio __iomem *regs = mm_gc->regs;
|
||||
|
||||
if (val)
|
||||
chip->shadow_dvo |= 1 << (31 - gpio);
|
||||
else
|
||||
chip->shadow_dvo &= ~(1 << (31 - gpio));
|
||||
out_be32(®s->simple_dvo, chip->shadow_dvo);
|
||||
}
|
||||
|
||||
static void
|
||||
mpc52xx_simple_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&gpio_lock, flags);
|
||||
|
||||
__mpc52xx_simple_gpio_set(gc, gpio, val);
|
||||
|
||||
spin_unlock_irqrestore(&gpio_lock, flags);
|
||||
|
||||
pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val);
|
||||
}
|
||||
|
||||
static int mpc52xx_simple_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
|
||||
{
|
||||
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
|
||||
struct mpc52xx_gpiochip *chip = container_of(mm_gc,
|
||||
struct mpc52xx_gpiochip, mmchip);
|
||||
struct mpc52xx_gpio *regs = mm_gc->regs;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&gpio_lock, flags);
|
||||
|
||||
/* set the direction */
|
||||
chip->shadow_ddr &= ~(1 << (31 - gpio));
|
||||
out_be32(®s->simple_ddr, chip->shadow_ddr);
|
||||
|
||||
/* and enable the pin */
|
||||
chip->shadow_gpioe |= 1 << (31 - gpio);
|
||||
out_be32(®s->simple_gpioe, chip->shadow_gpioe);
|
||||
|
||||
spin_unlock_irqrestore(&gpio_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
mpc52xx_simple_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
|
||||
{
|
||||
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
|
||||
struct mpc52xx_gpiochip *chip = container_of(mm_gc,
|
||||
struct mpc52xx_gpiochip, mmchip);
|
||||
struct mpc52xx_gpio *regs = mm_gc->regs;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&gpio_lock, flags);
|
||||
|
||||
/* First set initial value */
|
||||
__mpc52xx_simple_gpio_set(gc, gpio, val);
|
||||
|
||||
/* Then set direction */
|
||||
chip->shadow_ddr |= 1 << (31 - gpio);
|
||||
out_be32(®s->simple_ddr, chip->shadow_ddr);
|
||||
|
||||
/* Finally enable the pin */
|
||||
chip->shadow_gpioe |= 1 << (31 - gpio);
|
||||
out_be32(®s->simple_gpioe, chip->shadow_gpioe);
|
||||
|
||||
spin_unlock_irqrestore(&gpio_lock, flags);
|
||||
|
||||
pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __devinit mpc52xx_simple_gpiochip_probe(struct of_device *ofdev,
|
||||
const struct of_device_id *match)
|
||||
{
|
||||
struct mpc52xx_gpiochip *chip;
|
||||
struct of_gpio_chip *ofchip;
|
||||
struct mpc52xx_gpio *regs;
|
||||
int ret;
|
||||
|
||||
chip = kzalloc(sizeof(*chip), GFP_KERNEL);
|
||||
if (!chip)
|
||||
return -ENOMEM;
|
||||
|
||||
ofchip = &chip->mmchip.of_gc;
|
||||
|
||||
ofchip->gpio_cells = 2;
|
||||
ofchip->gc.ngpio = 32;
|
||||
ofchip->gc.direction_input = mpc52xx_simple_gpio_dir_in;
|
||||
ofchip->gc.direction_output = mpc52xx_simple_gpio_dir_out;
|
||||
ofchip->gc.get = mpc52xx_simple_gpio_get;
|
||||
ofchip->gc.set = mpc52xx_simple_gpio_set;
|
||||
|
||||
ret = of_mm_gpiochip_add(ofdev->node, &chip->mmchip);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
regs = chip->mmchip.regs;
|
||||
chip->shadow_gpioe = in_be32(®s->simple_gpioe);
|
||||
chip->shadow_ddr = in_be32(®s->simple_ddr);
|
||||
chip->shadow_dvo = in_be32(®s->simple_dvo);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id mpc52xx_simple_gpiochip_match[] = {
|
||||
{
|
||||
.compatible = "fsl,mpc5200-gpio",
|
||||
},
|
||||
{}
|
||||
};
|
||||
|
||||
static struct of_platform_driver mpc52xx_simple_gpiochip_driver = {
|
||||
.name = "gpio",
|
||||
.match_table = mpc52xx_simple_gpiochip_match,
|
||||
.probe = mpc52xx_simple_gpiochip_probe,
|
||||
.remove = mpc52xx_gpiochip_remove,
|
||||
};
|
||||
|
||||
/*
|
||||
* GPIO LIB API implementation for gpt GPIOs.
|
||||
*
|
||||
* Each gpt only has a single GPIO.
|
||||
*/
|
||||
static int mpc52xx_gpt_gpio_get(struct gpio_chip *gc, unsigned int gpio)
|
||||
{
|
||||
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
|
||||
struct mpc52xx_gpt __iomem *regs = mm_gc->regs;
|
||||
unsigned int ret;
|
||||
|
||||
return (in_be32(®s->status) & (1 << (31 - 23))) ? 1 : 0;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void
|
||||
mpc52xx_gpt_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
|
||||
{
|
||||
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
|
||||
struct mpc52xx_gpt __iomem *regs = mm_gc->regs;
|
||||
|
||||
if (val)
|
||||
out_be32(®s->mode, 0x34);
|
||||
else
|
||||
out_be32(®s->mode, 0x24);
|
||||
|
||||
pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val);
|
||||
}
|
||||
|
||||
static int mpc52xx_gpt_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
|
||||
{
|
||||
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
|
||||
struct mpc52xx_gpt *regs = mm_gc->regs;
|
||||
|
||||
out_be32(®s->mode, 0x04);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
mpc52xx_gpt_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
|
||||
{
|
||||
mpc52xx_gpt_gpio_set(gc, gpio, val);
|
||||
pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __devinit mpc52xx_gpt_gpiochip_probe(struct of_device *ofdev,
|
||||
const struct of_device_id *match)
|
||||
{
|
||||
struct of_mm_gpio_chip *mmchip;
|
||||
struct of_gpio_chip *chip;
|
||||
|
||||
mmchip = kzalloc(sizeof(*mmchip), GFP_KERNEL);
|
||||
if (!mmchip)
|
||||
return -ENOMEM;
|
||||
|
||||
chip = &mmchip->of_gc;
|
||||
|
||||
chip->gpio_cells = 2;
|
||||
chip->gc.ngpio = 1;
|
||||
chip->gc.direction_input = mpc52xx_gpt_gpio_dir_in;
|
||||
chip->gc.direction_output = mpc52xx_gpt_gpio_dir_out;
|
||||
chip->gc.get = mpc52xx_gpt_gpio_get;
|
||||
chip->gc.set = mpc52xx_gpt_gpio_set;
|
||||
|
||||
return of_mm_gpiochip_add(ofdev->node, mmchip);
|
||||
}
|
||||
|
||||
static const struct of_device_id mpc52xx_gpt_gpiochip_match[] = {
|
||||
{
|
||||
.compatible = "fsl,mpc5200-gpt-gpio",
|
||||
},
|
||||
{}
|
||||
};
|
||||
|
||||
static struct of_platform_driver mpc52xx_gpt_gpiochip_driver = {
|
||||
.name = "gpio_gpt",
|
||||
.match_table = mpc52xx_gpt_gpiochip_match,
|
||||
.probe = mpc52xx_gpt_gpiochip_probe,
|
||||
.remove = mpc52xx_gpiochip_remove,
|
||||
};
|
||||
|
||||
static int __init mpc52xx_gpio_init(void)
|
||||
{
|
||||
if (of_register_platform_driver(&mpc52xx_wkup_gpiochip_driver))
|
||||
printk(KERN_ERR "Unable to register wakeup GPIO driver\n");
|
||||
|
||||
if (of_register_platform_driver(&mpc52xx_simple_gpiochip_driver))
|
||||
printk(KERN_ERR "Unable to register simple GPIO driver\n");
|
||||
|
||||
if (of_register_platform_driver(&mpc52xx_gpt_gpiochip_driver))
|
||||
printk(KERN_ERR "Unable to register gpt GPIO driver\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/* Make sure we get initialised before anyone else tries to use us */
|
||||
subsys_initcall(mpc52xx_gpio_init);
|
||||
|
||||
/* No exit call at the moment as we cannot unregister of gpio chips */
|
||||
|
||||
MODULE_DESCRIPTION("Freescale MPC52xx gpio driver");
|
||||
MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
@ -18,6 +18,7 @@
|
|||
|
||||
#undef DEBUG
|
||||
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/of.h>
|
||||
#include <asm/io.h>
|
||||
|
@ -109,11 +110,48 @@ static void mpc52xx_extirq_ack(unsigned int virq)
|
|||
io_be_setbit(&intr->ctrl, 27-l2irq);
|
||||
}
|
||||
|
||||
static int mpc52xx_extirq_set_type(unsigned int virq, unsigned int flow_type)
|
||||
{
|
||||
u32 ctrl_reg, type;
|
||||
int irq;
|
||||
int l2irq;
|
||||
|
||||
irq = irq_map[virq].hwirq;
|
||||
l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
|
||||
|
||||
pr_debug("%s: irq=%x. l2=%d flow_type=%d\n", __func__, irq, l2irq, flow_type);
|
||||
|
||||
switch (flow_type) {
|
||||
case IRQF_TRIGGER_HIGH:
|
||||
type = 0;
|
||||
break;
|
||||
case IRQF_TRIGGER_RISING:
|
||||
type = 1;
|
||||
break;
|
||||
case IRQF_TRIGGER_FALLING:
|
||||
type = 2;
|
||||
break;
|
||||
case IRQF_TRIGGER_LOW:
|
||||
type = 3;
|
||||
break;
|
||||
default:
|
||||
type = 0;
|
||||
}
|
||||
|
||||
ctrl_reg = in_be32(&intr->ctrl);
|
||||
ctrl_reg &= ~(0x3 << (22 - (l2irq * 2)));
|
||||
ctrl_reg |= (type << (22 - (l2irq * 2)));
|
||||
out_be32(&intr->ctrl, ctrl_reg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct irq_chip mpc52xx_extirq_irqchip = {
|
||||
.typename = " MPC52xx IRQ[0-3] ",
|
||||
.mask = mpc52xx_extirq_mask,
|
||||
.unmask = mpc52xx_extirq_unmask,
|
||||
.ack = mpc52xx_extirq_ack,
|
||||
.set_type = mpc52xx_extirq_set_type,
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
|
@ -0,0 +1,2 @@
|
|||
spu_save_dump.h
|
||||
spu_restore_dump.h
|
|
@ -78,6 +78,7 @@ void destroy_spu_context(struct kref *kref)
|
|||
{
|
||||
struct spu_context *ctx;
|
||||
ctx = container_of(kref, struct spu_context, kref);
|
||||
spu_context_nospu_trace(destroy_spu_context__enter, ctx);
|
||||
mutex_lock(&ctx->state_mutex);
|
||||
spu_deactivate(ctx);
|
||||
mutex_unlock(&ctx->state_mutex);
|
||||
|
@ -88,6 +89,7 @@ void destroy_spu_context(struct kref *kref)
|
|||
kref_put(ctx->prof_priv_kref, ctx->prof_priv_release);
|
||||
BUG_ON(!list_empty(&ctx->rq));
|
||||
atomic_dec(&nr_spu_contexts);
|
||||
kfree(ctx->switch_log);
|
||||
kfree(ctx);
|
||||
}
|
||||
|
||||
|
@ -150,6 +152,8 @@ int spu_acquire_saved(struct spu_context *ctx)
|
|||
{
|
||||
int ret;
|
||||
|
||||
spu_context_nospu_trace(spu_acquire_saved__enter, ctx);
|
||||
|
||||
ret = spu_acquire(ctx);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
|
|
@ -2386,6 +2386,171 @@ static const struct file_operations spufs_stat_fops = {
|
|||
.release = single_release,
|
||||
};
|
||||
|
||||
static inline int spufs_switch_log_used(struct spu_context *ctx)
|
||||
{
|
||||
return (ctx->switch_log->head - ctx->switch_log->tail) %
|
||||
SWITCH_LOG_BUFSIZE;
|
||||
}
|
||||
|
||||
static inline int spufs_switch_log_avail(struct spu_context *ctx)
|
||||
{
|
||||
return SWITCH_LOG_BUFSIZE - spufs_switch_log_used(ctx);
|
||||
}
|
||||
|
||||
static int spufs_switch_log_open(struct inode *inode, struct file *file)
|
||||
{
|
||||
struct spu_context *ctx = SPUFS_I(inode)->i_ctx;
|
||||
|
||||
/*
|
||||
* We (ab-)use the mapping_lock here because it serves the similar
|
||||
* purpose for synchronizing open/close elsewhere. Maybe it should
|
||||
* be renamed eventually.
|
||||
*/
|
||||
mutex_lock(&ctx->mapping_lock);
|
||||
if (ctx->switch_log) {
|
||||
spin_lock(&ctx->switch_log->lock);
|
||||
ctx->switch_log->head = 0;
|
||||
ctx->switch_log->tail = 0;
|
||||
spin_unlock(&ctx->switch_log->lock);
|
||||
} else {
|
||||
/*
|
||||
* We allocate the switch log data structures on first open.
|
||||
* They will never be free because we assume a context will
|
||||
* be traced until it goes away.
|
||||
*/
|
||||
ctx->switch_log = kzalloc(sizeof(struct switch_log) +
|
||||
SWITCH_LOG_BUFSIZE * sizeof(struct switch_log_entry),
|
||||
GFP_KERNEL);
|
||||
if (!ctx->switch_log)
|
||||
goto out;
|
||||
spin_lock_init(&ctx->switch_log->lock);
|
||||
init_waitqueue_head(&ctx->switch_log->wait);
|
||||
}
|
||||
mutex_unlock(&ctx->mapping_lock);
|
||||
|
||||
return 0;
|
||||
out:
|
||||
mutex_unlock(&ctx->mapping_lock);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
static int switch_log_sprint(struct spu_context *ctx, char *tbuf, int n)
|
||||
{
|
||||
struct switch_log_entry *p;
|
||||
|
||||
p = ctx->switch_log->log + ctx->switch_log->tail % SWITCH_LOG_BUFSIZE;
|
||||
|
||||
return snprintf(tbuf, n, "%u.%09u %d %u %u %llu\n",
|
||||
(unsigned int) p->tstamp.tv_sec,
|
||||
(unsigned int) p->tstamp.tv_nsec,
|
||||
p->spu_id,
|
||||
(unsigned int) p->type,
|
||||
(unsigned int) p->val,
|
||||
(unsigned long long) p->timebase);
|
||||
}
|
||||
|
||||
static ssize_t spufs_switch_log_read(struct file *file, char __user *buf,
|
||||
size_t len, loff_t *ppos)
|
||||
{
|
||||
struct inode *inode = file->f_path.dentry->d_inode;
|
||||
struct spu_context *ctx = SPUFS_I(inode)->i_ctx;
|
||||
int error = 0, cnt = 0;
|
||||
|
||||
if (!buf || len < 0)
|
||||
return -EINVAL;
|
||||
|
||||
while (cnt < len) {
|
||||
char tbuf[128];
|
||||
int width;
|
||||
|
||||
if (file->f_flags & O_NONBLOCK) {
|
||||
if (spufs_switch_log_used(ctx) <= 0)
|
||||
return cnt ? cnt : -EAGAIN;
|
||||
} else {
|
||||
/* Wait for data in buffer */
|
||||
error = wait_event_interruptible(ctx->switch_log->wait,
|
||||
spufs_switch_log_used(ctx) > 0);
|
||||
if (error)
|
||||
break;
|
||||
}
|
||||
|
||||
spin_lock(&ctx->switch_log->lock);
|
||||
if (ctx->switch_log->head == ctx->switch_log->tail) {
|
||||
/* multiple readers race? */
|
||||
spin_unlock(&ctx->switch_log->lock);
|
||||
continue;
|
||||
}
|
||||
|
||||
width = switch_log_sprint(ctx, tbuf, sizeof(tbuf));
|
||||
if (width < len) {
|
||||
ctx->switch_log->tail =
|
||||
(ctx->switch_log->tail + 1) %
|
||||
SWITCH_LOG_BUFSIZE;
|
||||
}
|
||||
|
||||
spin_unlock(&ctx->switch_log->lock);
|
||||
|
||||
/*
|
||||
* If the record is greater than space available return
|
||||
* partial buffer (so far)
|
||||
*/
|
||||
if (width >= len)
|
||||
break;
|
||||
|
||||
error = copy_to_user(buf + cnt, tbuf, width);
|
||||
if (error)
|
||||
break;
|
||||
cnt += width;
|
||||
}
|
||||
|
||||
return cnt == 0 ? error : cnt;
|
||||
}
|
||||
|
||||
static unsigned int spufs_switch_log_poll(struct file *file, poll_table *wait)
|
||||
{
|
||||
struct inode *inode = file->f_path.dentry->d_inode;
|
||||
struct spu_context *ctx = SPUFS_I(inode)->i_ctx;
|
||||
unsigned int mask = 0;
|
||||
|
||||
poll_wait(file, &ctx->switch_log->wait, wait);
|
||||
|
||||
if (spufs_switch_log_used(ctx) > 0)
|
||||
mask |= POLLIN;
|
||||
|
||||
return mask;
|
||||
}
|
||||
|
||||
static const struct file_operations spufs_switch_log_fops = {
|
||||
.owner = THIS_MODULE,
|
||||
.open = spufs_switch_log_open,
|
||||
.read = spufs_switch_log_read,
|
||||
.poll = spufs_switch_log_poll,
|
||||
};
|
||||
|
||||
void spu_switch_log_notify(struct spu *spu, struct spu_context *ctx,
|
||||
u32 type, u32 val)
|
||||
{
|
||||
if (!ctx->switch_log)
|
||||
return;
|
||||
|
||||
spin_lock(&ctx->switch_log->lock);
|
||||
if (spufs_switch_log_avail(ctx) > 1) {
|
||||
struct switch_log_entry *p;
|
||||
|
||||
p = ctx->switch_log->log + ctx->switch_log->head;
|
||||
ktime_get_ts(&p->tstamp);
|
||||
p->timebase = get_tb();
|
||||
p->spu_id = spu ? spu->number : -1;
|
||||
p->type = type;
|
||||
p->val = val;
|
||||
|
||||
ctx->switch_log->head =
|
||||
(ctx->switch_log->head + 1) % SWITCH_LOG_BUFSIZE;
|
||||
}
|
||||
spin_unlock(&ctx->switch_log->lock);
|
||||
|
||||
wake_up(&ctx->switch_log->wait);
|
||||
}
|
||||
|
||||
struct tree_descr spufs_dir_contents[] = {
|
||||
{ "capabilities", &spufs_caps_fops, 0444, },
|
||||
|
@ -2422,6 +2587,7 @@ struct tree_descr spufs_dir_contents[] = {
|
|||
{ "proxydma_info", &spufs_proxydma_info_fops, 0444, },
|
||||
{ "tid", &spufs_tid_fops, 0444, },
|
||||
{ "stat", &spufs_stat_fops, 0444, },
|
||||
{ "switch_log", &spufs_switch_log_fops, 0444 },
|
||||
{},
|
||||
};
|
||||
|
||||
|
|
|
@ -405,6 +405,8 @@ long spufs_run_spu(struct spu_context *ctx, u32 *npc, u32 *event)
|
|||
ret = spu_run_fini(ctx, npc, &status);
|
||||
spu_yield(ctx);
|
||||
|
||||
spu_switch_log_notify(NULL, ctx, SWITCH_LOG_EXIT, status);
|
||||
|
||||
if ((status & SPU_STATUS_STOPPED_BY_STOP) &&
|
||||
(((status >> SPU_STOP_STATUS_SHIFT) & 0x3f00) == 0x2100))
|
||||
ctx->stats.libassist++;
|
||||
|
|
|
@ -240,6 +240,7 @@ static void spu_bind_context(struct spu *spu, struct spu_context *ctx)
|
|||
spu->mfc_callback = spufs_mfc_callback;
|
||||
mb();
|
||||
spu_unmap_mappings(ctx);
|
||||
spu_switch_log_notify(spu, ctx, SWITCH_LOG_START, 0);
|
||||
spu_restore(&ctx->csa, spu);
|
||||
spu->timestamp = jiffies;
|
||||
spu_cpu_affinity_set(spu, raw_smp_processor_id());
|
||||
|
@ -419,6 +420,7 @@ static void spu_unbind_context(struct spu *spu, struct spu_context *ctx)
|
|||
spu_switch_notify(spu, NULL);
|
||||
spu_unmap_mappings(ctx);
|
||||
spu_save(&ctx->csa, spu);
|
||||
spu_switch_log_notify(spu, ctx, SWITCH_LOG_STOP, 0);
|
||||
spu->timestamp = jiffies;
|
||||
ctx->state = SPU_STATE_SAVED;
|
||||
spu->ibox_callback = NULL;
|
||||
|
@ -591,7 +593,7 @@ static struct spu *find_victim(struct spu_context *ctx)
|
|||
struct spu *spu;
|
||||
int node, n;
|
||||
|
||||
spu_context_nospu_trace(spu_find_vitim__enter, ctx);
|
||||
spu_context_nospu_trace(spu_find_victim__enter, ctx);
|
||||
|
||||
/*
|
||||
* Look for a possible preemption candidate on the local node first.
|
||||
|
|
|
@ -47,6 +47,30 @@ enum {
|
|||
SPU_SCHED_SPU_RUN, /* context is within spu_run */
|
||||
};
|
||||
|
||||
enum {
|
||||
SWITCH_LOG_BUFSIZE = 4096,
|
||||
};
|
||||
|
||||
enum {
|
||||
SWITCH_LOG_START,
|
||||
SWITCH_LOG_STOP,
|
||||
SWITCH_LOG_EXIT,
|
||||
};
|
||||
|
||||
struct switch_log {
|
||||
spinlock_t lock;
|
||||
wait_queue_head_t wait;
|
||||
unsigned long head;
|
||||
unsigned long tail;
|
||||
struct switch_log_entry {
|
||||
struct timespec tstamp;
|
||||
s32 spu_id;
|
||||
u32 type;
|
||||
u32 val;
|
||||
u64 timebase;
|
||||
} log[];
|
||||
};
|
||||
|
||||
struct spu_context {
|
||||
struct spu *spu; /* pointer to a physical SPU */
|
||||
struct spu_state csa; /* SPU context save area. */
|
||||
|
@ -116,6 +140,9 @@ struct spu_context {
|
|||
unsigned long long libassist;
|
||||
} stats;
|
||||
|
||||
/* context switch log */
|
||||
struct switch_log *switch_log;
|
||||
|
||||
struct list_head aff_list;
|
||||
int aff_head;
|
||||
int aff_offset;
|
||||
|
@ -256,6 +283,8 @@ int spu_activate(struct spu_context *ctx, unsigned long flags);
|
|||
void spu_deactivate(struct spu_context *ctx);
|
||||
void spu_yield(struct spu_context *ctx);
|
||||
void spu_switch_notify(struct spu *spu, struct spu_context *ctx);
|
||||
void spu_switch_log_notify(struct spu *spu, struct spu_context *ctx,
|
||||
u32 type, u32 val);
|
||||
void spu_set_timeslice(struct spu_context *ctx);
|
||||
void spu_update_sched_info(struct spu_context *ctx);
|
||||
void __spu_update_sched_info(struct spu_context *ctx);
|
||||
|
@ -330,8 +359,8 @@ extern void spuctx_switch_state(struct spu_context *ctx,
|
|||
enum spu_utilization_state new_state);
|
||||
|
||||
#define spu_context_trace(name, ctx, spu) \
|
||||
trace_mark(name, "%p %p", ctx, spu);
|
||||
trace_mark(name, "ctx %p spu %p", ctx, spu);
|
||||
#define spu_context_nospu_trace(name, ctx) \
|
||||
trace_mark(name, "%p", ctx);
|
||||
trace_mark(name, "ctx %p", ctx);
|
||||
|
||||
#endif
|
||||
|
|
|
@ -171,24 +171,24 @@ static void spu_context_nospu_event(void *probe_private, void *call_data,
|
|||
}
|
||||
|
||||
struct spu_probe spu_probes[] = {
|
||||
{ "spu_bind_context__enter", "%p %p", spu_context_event },
|
||||
{ "spu_unbind_context__enter", "%p %p", spu_context_event },
|
||||
{ "spu_get_idle__enter", "%p", spu_context_nospu_event },
|
||||
{ "spu_get_idle__found", "%p %p", spu_context_event },
|
||||
{ "spu_get_idle__not_found", "%p", spu_context_nospu_event },
|
||||
{ "spu_find_victim__enter", "%p", spu_context_nospu_event },
|
||||
{ "spusched_tick__preempt", "%p %p", spu_context_event },
|
||||
{ "spusched_tick__newslice", "%p", spu_context_nospu_event },
|
||||
{ "spu_yield__enter", "%p", spu_context_nospu_event },
|
||||
{ "spu_deactivate__enter", "%p", spu_context_nospu_event },
|
||||
{ "__spu_deactivate__unload", "%p %p", spu_context_event },
|
||||
{ "spufs_ps_nopfn__enter", "%p", spu_context_nospu_event },
|
||||
{ "spufs_ps_nopfn__sleep", "%p", spu_context_nospu_event },
|
||||
{ "spufs_ps_nopfn__wake", "%p %p", spu_context_event },
|
||||
{ "spufs_ps_nopfn__insert", "%p %p", spu_context_event },
|
||||
{ "spu_acquire_saved__enter", "%p", spu_context_nospu_event },
|
||||
{ "destroy_spu_context__enter", "%p", spu_context_nospu_event },
|
||||
{ "spufs_stop_callback__enter", "%p %p", spu_context_event },
|
||||
{ "spu_bind_context__enter", "ctx %p spu %p", spu_context_event },
|
||||
{ "spu_unbind_context__enter", "ctx %p spu %p", spu_context_event },
|
||||
{ "spu_get_idle__enter", "ctx %p", spu_context_nospu_event },
|
||||
{ "spu_get_idle__found", "ctx %p spu %p", spu_context_event },
|
||||
{ "spu_get_idle__not_found", "ctx %p", spu_context_nospu_event },
|
||||
{ "spu_find_victim__enter", "ctx %p", spu_context_nospu_event },
|
||||
{ "spusched_tick__preempt", "ctx %p spu %p", spu_context_event },
|
||||
{ "spusched_tick__newslice", "ctx %p", spu_context_nospu_event },
|
||||
{ "spu_yield__enter", "ctx %p", spu_context_nospu_event },
|
||||
{ "spu_deactivate__enter", "ctx %p", spu_context_nospu_event },
|
||||
{ "__spu_deactivate__unload", "ctx %p spu %p", spu_context_event },
|
||||
{ "spufs_ps_nopfn__enter", "ctx %p", spu_context_nospu_event },
|
||||
{ "spufs_ps_nopfn__sleep", "ctx %p", spu_context_nospu_event },
|
||||
{ "spufs_ps_nopfn__wake", "ctx %p spu %p", spu_context_event },
|
||||
{ "spufs_ps_nopfn__insert", "ctx %p spu %p", spu_context_event },
|
||||
{ "spu_acquire_saved__enter", "ctx %p", spu_context_nospu_event },
|
||||
{ "destroy_spu_context__enter", "ctx %p", spu_context_nospu_event },
|
||||
{ "spufs_stop_callback__enter", "ctx %p spu %p", spu_context_event },
|
||||
};
|
||||
|
||||
static int __init sputrace_init(void)
|
||||
|
|
|
@ -491,20 +491,23 @@ static irqreturn_t mpc52xx_fec_interrupt(int irq, void *dev_id)
|
|||
|
||||
out_be32(&fec->ievent, ievent); /* clear pending events */
|
||||
|
||||
if (ievent & ~(FEC_IEVENT_RFIFO_ERROR | FEC_IEVENT_XFIFO_ERROR)) {
|
||||
if (ievent & ~FEC_IEVENT_TFINT)
|
||||
dev_dbg(&dev->dev, "ievent: %08x\n", ievent);
|
||||
/* on fifo error, soft-reset fec */
|
||||
if (ievent & (FEC_IEVENT_RFIFO_ERROR | FEC_IEVENT_XFIFO_ERROR)) {
|
||||
|
||||
if (net_ratelimit() && (ievent & FEC_IEVENT_RFIFO_ERROR))
|
||||
dev_warn(&dev->dev, "FEC_IEVENT_RFIFO_ERROR\n");
|
||||
if (net_ratelimit() && (ievent & FEC_IEVENT_XFIFO_ERROR))
|
||||
dev_warn(&dev->dev, "FEC_IEVENT_XFIFO_ERROR\n");
|
||||
|
||||
mpc52xx_fec_reset(dev);
|
||||
|
||||
netif_wake_queue(dev);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
if (net_ratelimit() && (ievent & FEC_IEVENT_RFIFO_ERROR))
|
||||
dev_warn(&dev->dev, "FEC_IEVENT_RFIFO_ERROR\n");
|
||||
if (net_ratelimit() && (ievent & FEC_IEVENT_XFIFO_ERROR))
|
||||
dev_warn(&dev->dev, "FEC_IEVENT_XFIFO_ERROR\n");
|
||||
if (ievent & ~FEC_IEVENT_TFINT)
|
||||
dev_dbg(&dev->dev, "ievent: %08x\n", ievent);
|
||||
|
||||
mpc52xx_fec_reset(dev);
|
||||
|
||||
netif_wake_queue(dev);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
|
|
|
@ -1221,8 +1221,8 @@ static struct of_device_id mpc52xx_uart_of_match[] = {
|
|||
#endif
|
||||
#ifdef CONFIG_PPC_MPC512x
|
||||
{ .compatible = "fsl,mpc5121-psc-uart", .data = &mpc512x_psc_ops, },
|
||||
{},
|
||||
#endif
|
||||
{},
|
||||
};
|
||||
|
||||
static int __devinit
|
||||
|
|
Загрузка…
Ссылка в новой задаче