IPoIB/cm: Fix performance regression on Mellanox
commit 518b1646
("IPoIB/cm: Fix SRQ WR leak") introduced a severe
performance regression on Mellanox cards, because keeping a QP in the
error state for extended periods of time moves hardware to the slow
path (until the QP is destroyed). For example, MPI latency goes from
~3 usecs to ~7 usecs.
Fix this by posting a send WR on one of the QPs that are being
flushed, instead of using a separate drain QP that is kept in the
error state.
This fixes bug <https://bugs.openfabrics.org/show_bug.cgi?id=636>,
reported and bisected by Scott Weitzenkamp at Cisco and debugged by
Sasha Mikheev at Voltaire.
Signed-off-by: Michael S. Tsirkin <mst@dev.mellanox.co.il>
Signed-off-by: Roland Dreier <rolandd@cisco.com>
This commit is contained in:
Родитель
8b7e15772a
Коммит
ec56dc0b7f
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@ -156,7 +156,7 @@ struct ipoib_cm_data {
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* - and then invoke a Destroy QP or Reset QP.
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*
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* We use the second option and wait for a completion on the
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* rx_drain_qp before destroying QPs attached to our SRQ.
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* same CQ before destroying QPs attached to our SRQ.
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*/
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enum ipoib_cm_state {
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@ -199,7 +199,6 @@ struct ipoib_cm_dev_priv {
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struct ib_srq *srq;
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struct ipoib_cm_rx_buf *srq_ring;
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struct ib_cm_id *id;
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struct ib_qp *rx_drain_qp; /* generates WR described in 10.3.1 */
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struct list_head passive_ids; /* state: LIVE */
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struct list_head rx_error_list; /* state: ERROR */
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struct list_head rx_flush_list; /* state: FLUSH, drain not started */
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@ -69,8 +69,9 @@ static struct ib_qp_attr ipoib_cm_err_attr = {
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#define IPOIB_CM_RX_DRAIN_WRID 0x7fffffff
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static struct ib_recv_wr ipoib_cm_rx_drain_wr = {
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.wr_id = IPOIB_CM_RX_DRAIN_WRID
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static struct ib_send_wr ipoib_cm_rx_drain_wr = {
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.wr_id = IPOIB_CM_RX_DRAIN_WRID,
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.opcode = IB_WR_SEND,
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};
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static int ipoib_cm_tx_handler(struct ib_cm_id *cm_id,
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@ -163,16 +164,22 @@ partial_error:
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static void ipoib_cm_start_rx_drain(struct ipoib_dev_priv* priv)
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{
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struct ib_recv_wr *bad_wr;
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struct ib_send_wr *bad_wr;
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struct ipoib_cm_rx *p;
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/* rx_drain_qp send queue depth is 1, so
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/* We only reserved 1 extra slot in CQ for drain WRs, so
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* make sure we have at most 1 outstanding WR. */
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if (list_empty(&priv->cm.rx_flush_list) ||
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!list_empty(&priv->cm.rx_drain_list))
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return;
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if (ib_post_recv(priv->cm.rx_drain_qp, &ipoib_cm_rx_drain_wr, &bad_wr))
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ipoib_warn(priv, "failed to post rx_drain wr\n");
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/*
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* QPs on flush list are error state. This way, a "flush
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* error" WC will be immediately generated for each WR we post.
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*/
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p = list_entry(priv->cm.rx_flush_list.next, typeof(*p), list);
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if (ib_post_send(p->qp, &ipoib_cm_rx_drain_wr, &bad_wr))
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ipoib_warn(priv, "failed to post drain wr\n");
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list_splice_init(&priv->cm.rx_flush_list, &priv->cm.rx_drain_list);
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}
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@ -199,10 +206,10 @@ static struct ib_qp *ipoib_cm_create_rx_qp(struct net_device *dev,
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struct ipoib_dev_priv *priv = netdev_priv(dev);
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struct ib_qp_init_attr attr = {
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.event_handler = ipoib_cm_rx_event_handler,
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.send_cq = priv->cq, /* does not matter, we never send anything */
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.send_cq = priv->cq, /* For drain WR */
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.recv_cq = priv->cq,
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.srq = priv->cm.srq,
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.cap.max_send_wr = 1, /* FIXME: 0 Seems not to work */
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.cap.max_send_wr = 1, /* For drain WR */
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.cap.max_send_sge = 1, /* FIXME: 0 Seems not to work */
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.sq_sig_type = IB_SIGNAL_ALL_WR,
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.qp_type = IB_QPT_RC,
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@ -242,6 +249,27 @@ static int ipoib_cm_modify_rx_qp(struct net_device *dev,
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ipoib_warn(priv, "failed to modify QP to RTR: %d\n", ret);
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return ret;
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}
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/*
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* Current Mellanox HCA firmware won't generate completions
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* with error for drain WRs unless the QP has been moved to
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* RTS first. This work-around leaves a window where a QP has
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* moved to error asynchronously, but this will eventually get
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* fixed in firmware, so let's not error out if modify QP
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* fails.
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*/
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qp_attr.qp_state = IB_QPS_RTS;
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ret = ib_cm_init_qp_attr(cm_id, &qp_attr, &qp_attr_mask);
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if (ret) {
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ipoib_warn(priv, "failed to init QP attr for RTS: %d\n", ret);
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return 0;
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}
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ret = ib_modify_qp(qp, &qp_attr, qp_attr_mask);
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if (ret) {
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ipoib_warn(priv, "failed to modify QP to RTS: %d\n", ret);
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return 0;
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}
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return 0;
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}
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@ -623,38 +651,11 @@ static void ipoib_cm_tx_completion(struct ib_cq *cq, void *tx_ptr)
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int ipoib_cm_dev_open(struct net_device *dev)
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{
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struct ipoib_dev_priv *priv = netdev_priv(dev);
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struct ib_qp_init_attr qp_init_attr = {
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.send_cq = priv->cq, /* does not matter, we never send anything */
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.recv_cq = priv->cq,
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.cap.max_send_wr = 1, /* FIXME: 0 Seems not to work */
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.cap.max_send_sge = 1, /* FIXME: 0 Seems not to work */
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.cap.max_recv_wr = 1,
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.cap.max_recv_sge = 1, /* FIXME: 0 Seems not to work */
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.sq_sig_type = IB_SIGNAL_ALL_WR,
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.qp_type = IB_QPT_UC,
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};
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int ret;
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if (!IPOIB_CM_SUPPORTED(dev->dev_addr))
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return 0;
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priv->cm.rx_drain_qp = ib_create_qp(priv->pd, &qp_init_attr);
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if (IS_ERR(priv->cm.rx_drain_qp)) {
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printk(KERN_WARNING "%s: failed to create CM ID\n", priv->ca->name);
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ret = PTR_ERR(priv->cm.rx_drain_qp);
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return ret;
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}
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/*
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* We put the QP in error state directly. This way, a "flush
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* error" WC will be immediately generated for each WR we post.
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*/
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ret = ib_modify_qp(priv->cm.rx_drain_qp, &ipoib_cm_err_attr, IB_QP_STATE);
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if (ret) {
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ipoib_warn(priv, "failed to modify drain QP to error: %d\n", ret);
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goto err_qp;
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}
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priv->cm.id = ib_create_cm_id(priv->ca, ipoib_cm_rx_handler, dev);
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if (IS_ERR(priv->cm.id)) {
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printk(KERN_WARNING "%s: failed to create CM ID\n", priv->ca->name);
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@ -676,8 +677,6 @@ err_listen:
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ib_destroy_cm_id(priv->cm.id);
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err_cm:
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priv->cm.id = NULL;
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err_qp:
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ib_destroy_qp(priv->cm.rx_drain_qp);
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return ret;
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}
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@ -740,7 +739,6 @@ void ipoib_cm_dev_stop(struct net_device *dev)
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kfree(p);
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}
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ib_destroy_qp(priv->cm.rx_drain_qp);
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cancel_delayed_work(&priv->cm.stale_task);
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}
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