mtd: nand: pxa3xx: Remove unneeded internal cmdset
Use the defined macros for NAND command instead of using a constant internal structure. This commit is only a cleanup, there's no functionality modification. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by: Daniel Mack <zonque@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This commit is contained in:
Ezequiel Garcia
David Woodhouse
Родитель
f455578dd9
Коммит
ec82135a01
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@ -131,7 +131,6 @@ enum pxa3xx_nand_variant {
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struct pxa3xx_nand_host {
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struct nand_chip chip;
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struct pxa3xx_nand_cmdset *cmdset;
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struct mtd_info *mtd;
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void *info_data;
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@ -205,23 +204,6 @@ static bool use_dma = 1;
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module_param(use_dma, bool, 0444);
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MODULE_PARM_DESC(use_dma, "enable DMA for data transferring to/from NAND HW");
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/*
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* Default NAND flash controller configuration setup by the
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* bootloader. This configuration is used only when pdata->keep_config is set
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*/
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static struct pxa3xx_nand_cmdset default_cmdset = {
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.read1 = 0x3000,
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.read2 = 0x0050,
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.program = 0x1080,
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.read_status = 0x0070,
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.read_id = 0x0090,
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.erase = 0xD060,
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.reset = 0x00FF,
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.lock = 0x002A,
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.unlock = 0x2423,
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.lock_status = 0x007A,
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};
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static struct pxa3xx_nand_timing timing[] = {
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{ 40, 80, 60, 100, 80, 100, 90000, 400, 40, },
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{ 10, 0, 20, 40, 30, 40, 11123, 110, 10, },
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@ -530,7 +512,6 @@ static inline int is_buf_blank(uint8_t *buf, size_t len)
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static int prepare_command_pool(struct pxa3xx_nand_info *info, int command,
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uint16_t column, int page_addr)
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{
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uint16_t cmd;
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int addr_cycle, exec_cmd;
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struct pxa3xx_nand_host *host;
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struct mtd_info *mtd;
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@ -580,21 +561,17 @@ static int prepare_command_pool(struct pxa3xx_nand_info *info, int command,
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switch (command) {
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case NAND_CMD_READOOB:
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case NAND_CMD_READ0:
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cmd = host->cmdset->read1;
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if (command == NAND_CMD_READOOB)
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info->buf_start = mtd->writesize + column;
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else
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info->buf_start = column;
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info->buf_start = column;
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info->ndcb0 |= NDCB0_CMD_TYPE(0)
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| addr_cycle
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| NAND_CMD_READ0;
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if (unlikely(host->page_size < PAGE_CHUNK_SIZE))
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info->ndcb0 |= NDCB0_CMD_TYPE(0)
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| addr_cycle
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| (cmd & NDCB0_CMD1_MASK);
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else
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info->ndcb0 |= NDCB0_CMD_TYPE(0)
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| NDCB0_DBC
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| addr_cycle
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| cmd;
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if (command == NAND_CMD_READOOB)
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info->buf_start += mtd->writesize;
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/* Second command setting for large pages */
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if (host->page_size >= PAGE_CHUNK_SIZE)
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info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8);
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case NAND_CMD_SEQIN:
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/* small page addr setting */
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@ -625,62 +602,58 @@ static int prepare_command_pool(struct pxa3xx_nand_info *info, int command,
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break;
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}
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cmd = host->cmdset->program;
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info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
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| NDCB0_AUTO_RS
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| NDCB0_ST_ROW_EN
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| NDCB0_DBC
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| cmd
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| (NAND_CMD_PAGEPROG << 8)
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| NAND_CMD_SEQIN
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| addr_cycle;
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break;
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case NAND_CMD_PARAM:
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cmd = NAND_CMD_PARAM;
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info->buf_count = 256;
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info->ndcb0 |= NDCB0_CMD_TYPE(0)
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| NDCB0_ADDR_CYC(1)
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| NDCB0_LEN_OVRD
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| cmd;
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| command;
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info->ndcb1 = (column & 0xFF);
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info->ndcb3 = 256;
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info->data_size = 256;
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break;
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case NAND_CMD_READID:
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cmd = host->cmdset->read_id;
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info->buf_count = host->read_id_bytes;
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info->ndcb0 |= NDCB0_CMD_TYPE(3)
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| NDCB0_ADDR_CYC(1)
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| cmd;
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| command;
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info->ndcb1 = (column & 0xFF);
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info->data_size = 8;
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break;
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case NAND_CMD_STATUS:
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cmd = host->cmdset->read_status;
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info->buf_count = 1;
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info->ndcb0 |= NDCB0_CMD_TYPE(4)
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| NDCB0_ADDR_CYC(1)
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| cmd;
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| command;
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info->data_size = 8;
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break;
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case NAND_CMD_ERASE1:
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cmd = host->cmdset->erase;
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info->ndcb0 |= NDCB0_CMD_TYPE(2)
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| NDCB0_AUTO_RS
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| NDCB0_ADDR_CYC(3)
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| NDCB0_DBC
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| cmd;
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| (NAND_CMD_ERASE2 << 8)
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| NAND_CMD_ERASE1;
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info->ndcb1 = page_addr;
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info->ndcb2 = 0;
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break;
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case NAND_CMD_RESET:
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cmd = host->cmdset->reset;
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info->ndcb0 |= NDCB0_CMD_TYPE(5)
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| cmd;
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| command;
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break;
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@ -876,7 +849,6 @@ static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info,
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}
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/* calculate flash information */
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host->cmdset = &default_cmdset;
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host->page_size = f->page_size;
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host->read_id_bytes = (f->page_size == 2048) ? 4 : 2;
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@ -922,7 +894,6 @@ static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
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}
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host->reg_ndcr = ndcr & ~NDCR_INT_MASK;
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host->cmdset = &default_cmdset;
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host->ndtr0cs0 = nand_readl(info, NDTR0CS0);
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host->ndtr1cs0 = nand_readl(info, NDTR1CS0);
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@ -16,19 +16,6 @@ struct pxa3xx_nand_timing {
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unsigned int tAR; /* ND_ALE low to ND_nRE low delay */
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};
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struct pxa3xx_nand_cmdset {
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uint16_t read1;
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uint16_t read2;
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uint16_t program;
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uint16_t read_status;
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uint16_t read_id;
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uint16_t erase;
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uint16_t reset;
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uint16_t lock;
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uint16_t unlock;
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uint16_t lock_status;
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};
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struct pxa3xx_nand_flash {
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char *name;
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uint32_t chip_id;
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