ASoC: max98090: Correct pclk divisor settings
The Baytrail-based chromebooks have a 20MHz mclk, the code was setting the divisor incorrectly in this case. According to the 98090 datasheet, the divisor should be set to DIV1 for 10 <= mclk <= 20. Correct this and the surrounding clock ranges as well to match the datasheet. Signed-off-by: Dylan Reid <dgreid@chromium.org> Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -1941,13 +1941,13 @@ static int max98090_dai_set_sysclk(struct snd_soc_dai *dai,
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* 0x02 (when master clk is 20MHz to 40MHz)..
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* 0x03 (when master clk is 40MHz to 60MHz)..
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*/
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if ((freq >= 10000000) && (freq < 20000000)) {
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if ((freq >= 10000000) && (freq <= 20000000)) {
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snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK,
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M98090_PSCLK_DIV1);
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} else if ((freq >= 20000000) && (freq < 40000000)) {
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} else if ((freq > 20000000) && (freq <= 40000000)) {
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snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK,
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M98090_PSCLK_DIV2);
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} else if ((freq >= 40000000) && (freq < 60000000)) {
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} else if ((freq > 40000000) && (freq <= 60000000)) {
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snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK,
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M98090_PSCLK_DIV4);
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} else {
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