From 8703612b0abb33e6daacc0f6b709a006ac85b285 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 30 Mar 2012 15:50:44 -0600 Subject: [PATCH 01/29] ARM: tegra: provide clock aliases for AHUB configlink The Tegra30 AHUB driver must call tegra_periph_reset_deassert() for all devices on the AHUB's configlink bus. The AHUB driver must be able to call clk_get_sys() to retrieve the clock parameter for this function. Add the necessary clock aliases to allow this. Signed-off-by: Stephen Warren Acked-by: Olof Johansson --- arch/arm/mach-tegra/tegra30_clocks.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/mach-tegra/tegra30_clocks.c b/arch/arm/mach-tegra/tegra30_clocks.c index 6d08b53f92d2..e33fe4b14a2a 100644 --- a/arch/arm/mach-tegra/tegra30_clocks.c +++ b/arch/arm/mach-tegra/tegra30_clocks.c @@ -3015,6 +3015,15 @@ struct clk_duplicate tegra_clk_duplicates[] = { CLK_DUPLICATE("sbc6", "spi_slave_tegra.5", NULL), CLK_DUPLICATE("twd", "smp_twd", NULL), CLK_DUPLICATE("vcp", "nvavp", "vcp"), + CLK_DUPLICATE("i2s0", NULL, "i2s0"), + CLK_DUPLICATE("i2s1", NULL, "i2s1"), + CLK_DUPLICATE("i2s2", NULL, "i2s2"), + CLK_DUPLICATE("i2s3", NULL, "i2s3"), + CLK_DUPLICATE("i2s4", NULL, "i2s4"), + CLK_DUPLICATE("dam0", NULL, "dam0"), + CLK_DUPLICATE("dam1", NULL, "dam1"), + CLK_DUPLICATE("dam2", NULL, "dam2"), + CLK_DUPLICATE("spdif_in", NULL, "spdif_in"), }; struct clk *tegra_ptr_clks[] = { From 6437626928467e81aa4a3087d88cd3f443b3e9ec Mon Sep 17 00:00:00 2001 From: Peter De Schrijver Date: Mon, 23 Apr 2012 01:31:49 -0700 Subject: [PATCH 02/29] ARM: tegra: Initialize pll_p_out1 pll_a uses pll_p_out1 as its parent. Therefore this clock needs to be initialized to make sure pll_a has a known input clock. Failure to do so will cause the system to crash early in the bootup. Signed-off-by: Peter De Schrijver Signed-off-by: Stephen Warren --- arch/arm/mach-tegra/common.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index 22df10fb9972..1f762333937e 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -93,6 +93,17 @@ static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = { }; #endif +#ifdef CONFIG_ARCH_TEGRA_3x_SOC +static __initdata struct tegra_clk_init_table tegra30_clk_init_table[] = { + /* name parent rate enabled */ + { "clk_m", NULL, 0, true }, + { "pll_p", "clk_m", 408000000, true }, + { "pll_p_out1", "pll_p", 9600000, true }, + { NULL, NULL, 0, 0}, +}; +#endif + + static void __init tegra_init_cache(u32 tag_latency, u32 data_latency) { #ifdef CONFIG_CACHE_L2X0 @@ -127,6 +138,7 @@ void __init tegra30_init_early(void) { tegra_init_fuse(); tegra30_init_clocks(); + tegra_clk_init_from_table(tegra30_clk_init_table); tegra_init_cache(0x441, 0x551); tegra_pmc_init(); tegra_powergate_init(); From 18b81fb733356025a6ad48b85092a0456e348ff0 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 26 Mar 2012 16:49:39 -0600 Subject: [PATCH 03/29] ARM: tegra: set up audio clocks for tegra30 dt Set up the audio clock tree for Tegra30 in an equivalent fashion to the existing setup for Tegra20. Signed-off-by: Stephen Warren Acked-by: Olof Johansson --- arch/arm/mach-tegra/board-dt-tegra30.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c b/arch/arm/mach-tegra/board-dt-tegra30.c index 5f7c03e972f3..3de21c0b5461 100644 --- a/arch/arm/mach-tegra/board-dt-tegra30.c +++ b/arch/arm/mach-tegra/board-dt-tegra30.c @@ -57,6 +57,15 @@ struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = { static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = { /* name parent rate enabled */ { "uarta", "pll_p", 408000000, true }, + { "pll_a", "pll_p_out1", 564480000, true }, + { "pll_a_out0", "pll_a", 11289600, true }, + { "extern1", "pll_a_out0", 0, true }, + { "clk_out_1", "extern1", 0, true }, + { "i2s0", "pll_a_out0", 11289600, false}, + { "i2s1", "pll_a_out0", 11289600, false}, + { "i2s2", "pll_a_out0", 11289600, false}, + { "i2s3", "pll_a_out0", 11289600, false}, + { "i2s4", "pll_a_out0", 11289600, false}, { NULL, NULL, 0, 0}, }; From 5657d98deadb5e245bf5608cfb06e86898032125 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 27 Mar 2012 11:37:47 -0600 Subject: [PATCH 04/29] ARM: tegra: add AUXDATA required for audio Both the Tegra30 I2S and AHUB modules used clocks, and hence currently require AUXDATA in order to get specific device names so that clock lookups work. Signed-off-by: Stephen Warren Acked-by: Olof Johansson --- arch/arm/mach-tegra/board-dt-tegra30.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c b/arch/arm/mach-tegra/board-dt-tegra30.c index 3de21c0b5461..d96dae0b4aa7 100644 --- a/arch/arm/mach-tegra/board-dt-tegra30.c +++ b/arch/arm/mach-tegra/board-dt-tegra30.c @@ -51,6 +51,7 @@ struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = { OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C500, "tegra-i2c.2", NULL), OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C700, "tegra-i2c.3", NULL), OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000D000, "tegra-i2c.4", NULL), + OF_DEV_AUXDATA("nvidia,tegra30-ahub", 0x70080000, "tegra30-ahub", NULL), {} }; From 9ee6a5c4f4cd2b0a732502c5f11b3ee8f13fac76 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 27 Mar 2012 12:40:53 -0600 Subject: [PATCH 05/29] ARM: dt: tegra30.dtsi: Add audio-related nodes Add nodes for the Tegra30 AHUB and I2S controllers. Signed-off-by: Stephen Warren Acked-by: Olof Johansson --- arch/arm/boot/dts/tegra30.dtsi | 41 ++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 62a7b39f1c9a..15200a949a81 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -183,4 +183,45 @@ reg = < 0x70000868 0xd0 /* Pad control registers */ 0x70003000 0x3e0 >; /* Mux registers */ }; + + ahub { + compatible = "nvidia,tegra30-ahub"; + reg = <0x70080000 0x200 0x70080200 0x100>; + interrupts = < 0 103 0x04 >; + nvidia,dma-request-selector = <&apbdma 1>; + + ranges; + #address-cells = <1>; + #size-cells = <1>; + + tegra_i2s0: i2s@70080300 { + compatible = "nvidia,tegra30-i2s"; + reg = <0x70080300 0x100>; + nvidia,ahub-cif-ids = <4 4>; + }; + + tegra_i2s1: i2s@70080400 { + compatible = "nvidia,tegra30-i2s"; + reg = <0x70080400 0x100>; + nvidia,ahub-cif-ids = <5 5>; + }; + + tegra_i2s2: i2s@70080500 { + compatible = "nvidia,tegra30-i2s"; + reg = <0x70080500 0x100>; + nvidia,ahub-cif-ids = <6 6>; + }; + + tegra_i2s3: i2s@70080600 { + compatible = "nvidia,tegra30-i2s"; + reg = <0x70080600 0x100>; + nvidia,ahub-cif-ids = <7 7>; + }; + + tegra_i2s4: i2s@70080700 { + compatible = "nvidia,tegra30-i2s"; + reg = <0x70080700 0x100>; + nvidia,ahub-cif-ids = <8 8>; + }; + }; }; From 8c6a3852f639736ca7cb0f5e7b3fd0f314b0fc6a Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 27 Mar 2012 12:41:37 -0600 Subject: [PATCH 06/29] ARM: dt: tegra cardhu: basic audio support Add WM8903 codec nodes, and top-level sound complex node for basic analog audio over headset jack and internal speakers. Signed-off-by: Stephen Warren Acked-by: Olof Johansson --- arch/arm/boot/dts/tegra-cardhu.dts | 63 ++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/arch/arm/boot/dts/tegra-cardhu.dts b/arch/arm/boot/dts/tegra-cardhu.dts index 0a9f34a2c3aa..ab8d901b5ab6 100644 --- a/arch/arm/boot/dts/tegra-cardhu.dts +++ b/arch/arm/boot/dts/tegra-cardhu.dts @@ -51,6 +51,15 @@ nvidia,pull = <2>; nvidia,tristate = <0>; }; + dap2_fs_pa2 { + nvidia,pins = "dap2_fs_pa2", + "dap2_sclk_pa3", + "dap2_din_pa4", + "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + }; }; }; @@ -92,6 +101,20 @@ i2c@7000d000 { clock-frequency = <100000>; + + wm8903: wm8903@1a { + compatible = "wlf,wm8903"; + reg = <0x1a>; + interrupt-parent = <&gpio>; + interrupts = <179 0x04>; /* gpio PW3 */ + + gpio-controller; + #gpio-cells = <2>; + + micdet-cfg = <0>; + micdet-delay = <100>; + gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; + }; }; sdhci@78000000 { @@ -111,4 +134,44 @@ sdhci@78000400 { support-8bit; }; + + ahub@70080000 { + i2s@70080300 { + status = "disable"; + }; + + i2s@70080500 { + status = "disable"; + }; + + i2s@70080600 { + status = "disable"; + }; + + i2s@70080700 { + status = "disable"; + }; + }; + + sound { + compatible = "nvidia,tegra-audio-wm8903-cardhu", + "nvidia,tegra-audio-wm8903"; + nvidia,model = "NVIDIA Tegra Cardhu"; + + nvidia,audio-routing = + "Headphone Jack", "HPOUTR", + "Headphone Jack", "HPOUTL", + "Int Spk", "ROP", + "Int Spk", "RON", + "Int Spk", "LOP", + "Int Spk", "LON", + "Mic Jack", "MICBIAS", + "IN1L", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&wm8903>; + + nvidia,spkr-en-gpios = <&wm8903 2 0>; + nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ + }; }; From c8b62ab41f76218efca5e4baa5c22ef52a9fe3a5 Mon Sep 17 00:00:00 2001 From: Allen Martin Date: Fri, 10 Sep 2010 09:17:33 -0500 Subject: [PATCH 07/29] ARM: tegra: Add pllc clock init table pll_c will be used as a clock source. Fill in tegra_pll_c_freq_table[] so that it's possible to explicitly initialize the PLL. NVIDIA's downstream nv-3.1 kernel and the ChromeOS kernel have different pll_c tables. nv-3.1 contains entries for 522MHz and 598MHz output, whereas the ChromeOS kernel contains entries for 600MHz output. I chose to upstream the ChromeOS values for now, since the 600MHz rate appears to match the default rate of this PLL when the HW boots, and it's not clear to me why 522 or 598MHz are more useful. Signed-off-by: Allen Martin Signed-off-by: Olof Johansson Signed-off-by: Stephen Warren [swarren: wrote commit description] --- arch/arm/mach-tegra/tegra2_clocks.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c index 592a4eeb5328..a357ad2a8cf7 100644 --- a/arch/arm/mach-tegra/tegra2_clocks.c +++ b/arch/arm/mach-tegra/tegra2_clocks.c @@ -1486,6 +1486,10 @@ static struct clk tegra_clk_m = { }; static struct clk_pll_freq_table tegra_pll_c_freq_table[] = { + { 12000000, 600000000, 600, 12, 1, 8 }, + { 13000000, 600000000, 600, 13, 1, 8 }, + { 19200000, 600000000, 500, 16, 1, 6 }, + { 26000000, 600000000, 600, 26, 1, 8 }, { 0, 0, 0, 0, 0, 0 }, }; From 60f975b98cf41476ba0e156f7523b197b046cf2b Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 12 Apr 2012 14:09:39 -0600 Subject: [PATCH 08/29] ARM: tegra: reparent sclk to pll_c_out1 pll_p_out4 needs to be used for other purposes. Reparent sclk so that it runs from pll_c. Change sclk's rate to 120MHz from 108MHz since this is the lowest precise rate that can be achieved by dividing the pll_c rate without reducing the sclk rate. (600/5=120, 600/5.5=109.0909..., 600/6=100). Signed-off-by: Stephen Warren --- arch/arm/mach-tegra/common.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index 22df10fb9972..e96900418682 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -83,8 +83,10 @@ static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = { { "pll_p_out2", "pll_p", 48000000, true }, { "pll_p_out3", "pll_p", 72000000, true }, { "pll_p_out4", "pll_p", 108000000, true }, - { "sclk", "pll_p_out4", 108000000, true }, - { "hclk", "sclk", 108000000, true }, + { "pll_c", "clk_m", 600000000, true }, + { "pll_c_out1", "pll_c", 120000000, true }, + { "sclk", "pll_c_out1", 120000000, true }, + { "hclk", "sclk", 120000000, true }, { "pclk", "hclk", 54000000, true }, { "csite", NULL, 0, true }, { "emc", NULL, 0, true }, From 7ff4db0967bd7d617c77dc5a66c0d95166277817 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 20 Apr 2012 16:58:18 -0600 Subject: [PATCH 09/29] ARM: tegra: fix pclk rate Commit 40f9cf0 "ARM: tegra: reparent sclk to pll_c_out1" changed the rate of hclk. Since pclk is derived from that, and only has integer dividers, the pclk rate needs to change in the same fashion, from 54MHz to 60MHz. Signed-off-by: Stephen Warren --- arch/arm/mach-tegra/common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index e96900418682..a4fba8835136 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -87,7 +87,7 @@ static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = { { "pll_c_out1", "pll_c", 120000000, true }, { "sclk", "pll_c_out1", 120000000, true }, { "hclk", "sclk", 120000000, true }, - { "pclk", "hclk", 54000000, true }, + { "pclk", "hclk", 60000000, true }, { "csite", NULL, 0, true }, { "emc", NULL, 0, true }, { "cpu", NULL, 0, true }, From 9abafa021e223f04d6589ee2b977bbaf2e1f1367 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 12 Apr 2012 14:13:05 -0600 Subject: [PATCH 10/29] ARM: tegra: change pll_p_out4's rate to 24MHz pll_p_out4 is used on all/most Tegra boards to drive the cdev2 output pin to provide a reference clock to a ULPI USB PHY. This reference clock must run at 24MHz, and the cdev2 output has no additional dividers. Remove board-paz00.c's now-duplicate initialization of this clock. Reported-by: Marc Dietrich Signed-off-by: Stephen Warren --- arch/arm/mach-tegra/board-paz00.c | 1 - arch/arm/mach-tegra/common.c | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c index 330afdfa2475..aebfa4003813 100644 --- a/arch/arm/mach-tegra/board-paz00.c +++ b/arch/arm/mach-tegra/board-paz00.c @@ -176,7 +176,6 @@ static __initdata struct tegra_clk_init_table paz00_clk_init_table[] = { { "uarta", "pll_p", 216000000, true }, { "uartc", "pll_p", 216000000, true }, - { "pll_p_out4", "pll_p", 24000000, true }, { "usbd", "clk_m", 12000000, false }, { "usb2", "clk_m", 12000000, false }, { "usb3", "clk_m", 12000000, false }, diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index a4fba8835136..f18f615aa93a 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -82,7 +82,7 @@ static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = { { "pll_p_out1", "pll_p", 28800000, true }, { "pll_p_out2", "pll_p", 48000000, true }, { "pll_p_out3", "pll_p", 72000000, true }, - { "pll_p_out4", "pll_p", 108000000, true }, + { "pll_p_out4", "pll_p", 24000000, true }, { "pll_c", "clk_m", 600000000, true }, { "pll_c_out1", "pll_c", 120000000, true }, { "sclk", "pll_c_out1", 120000000, true }, From 60d148b9f838b718e4808061ee6d5833de77fd9c Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 12 Apr 2012 15:03:52 -0600 Subject: [PATCH 11/29] ARM: tegra: don't hard-code USB ULPI PHY reset_gpio Not all boards use GPIO_PV0 as the ULPI PHY reset signal. Instead of hard-coding this GPIO into devices.c, make the board files set it explicitly. This will allow the PHY code to differentiate between set and unset values, and hence know when to read the value from device tree. Signed-off-by: Stephen Warren --- arch/arm/mach-tegra/board-paz00.c | 2 ++ arch/arm/mach-tegra/board-trimslice.c | 2 ++ arch/arm/mach-tegra/devices.c | 5 ++--- arch/arm/mach-tegra/devices.h | 4 ++++ 4 files changed, 10 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c index aebfa4003813..e31317deec21 100644 --- a/arch/arm/mach-tegra/board-paz00.c +++ b/arch/arm/mach-tegra/board-paz00.c @@ -159,6 +159,8 @@ static void paz00_i2c_init(void) static void paz00_usb_init(void) { + tegra_ehci2_ulpi_phy_config.reset_gpio = TEGRA_ULPI_RST; + platform_device_register(&tegra_ehci2_device); platform_device_register(&tegra_ehci3_device); } diff --git a/arch/arm/mach-tegra/board-trimslice.c b/arch/arm/mach-tegra/board-trimslice.c index f6f5b6a11325..24f1678098dd 100644 --- a/arch/arm/mach-tegra/board-trimslice.c +++ b/arch/arm/mach-tegra/board-trimslice.c @@ -117,6 +117,8 @@ static void trimslice_usb_init(void) pdata = tegra_ehci1_device.dev.platform_data; pdata->vbus_gpio = TRIMSLICE_GPIO_USB1_MODE; + tegra_ehci2_ulpi_phy_config.reset_gpio = TEGRA_GPIO_PV0; + platform_device_register(&tegra_ehci3_device); platform_device_register(&tegra_ehci2_device); platform_device_register(&tegra_ehci1_device); diff --git a/arch/arm/mach-tegra/devices.c b/arch/arm/mach-tegra/devices.c index bd3035e0cea1..9fcb9a522276 100644 --- a/arch/arm/mach-tegra/devices.c +++ b/arch/arm/mach-tegra/devices.c @@ -439,9 +439,8 @@ static struct resource tegra_usb3_resources[] = { }, }; -static struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = { - /* All existing boards use GPIO PV0 for phy reset */ - .reset_gpio = TEGRA_GPIO_PV0, +struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = { + .reset_gpio = -1, .clk = "cdev2", }; diff --git a/arch/arm/mach-tegra/devices.h b/arch/arm/mach-tegra/devices.h index ec455679b219..4290ea0063ac 100644 --- a/arch/arm/mach-tegra/devices.h +++ b/arch/arm/mach-tegra/devices.h @@ -22,6 +22,10 @@ #include #include +#include + +extern struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config; + extern struct tegra_ehci_platform_data tegra_ehci1_pdata; extern struct tegra_ehci_platform_data tegra_ehci2_pdata; extern struct tegra_ehci_platform_data tegra_ehci3_pdata; From aa607ebf93a5fc26275a575781399df971dd1b91 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 12 Apr 2012 15:46:49 -0600 Subject: [PATCH 12/29] ARM: tegra: add USB ULPI PHY reset GPIO to device tree ULPI PHYs have a reset signal, and different boards use a different GPIO for this task. Add a property to device tree to represent this. I'm not sure if adding this property to the EHCI controller node is entirely correct; perhaps eventually we should have explicit separate nodes for the various PHYs. However, we don't have that right now, so this binding seems like a reasonable choice. Cc: Cc: Greg Kroah-Hartman Cc: Signed-off-by: Stephen Warren --- .../devicetree/bindings/usb/tegra-usb.txt | 3 +++ arch/arm/boot/dts/tegra-harmony.dts | 4 ++++ arch/arm/boot/dts/tegra-paz00.dts | 4 ++++ arch/arm/boot/dts/tegra-seaboard.dts | 4 ++++ arch/arm/boot/dts/tegra-trimslice.dts | 4 ++++ arch/arm/boot/dts/tegra-ventana.dts | 4 ++++ arch/arm/mach-tegra/include/mach/usb_phy.h | 4 ++-- arch/arm/mach-tegra/usb_phy.c | 15 +++++++++++++-- drivers/usb/host/ehci-tegra.c | 5 +++-- 9 files changed, 41 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/usb/tegra-usb.txt b/Documentation/devicetree/bindings/usb/tegra-usb.txt index 007005ddbe12..e9b005dc7625 100644 --- a/Documentation/devicetree/bindings/usb/tegra-usb.txt +++ b/Documentation/devicetree/bindings/usb/tegra-usb.txt @@ -12,6 +12,9 @@ Required properties : - nvidia,vbus-gpio : If present, specifies a gpio that needs to be activated for the bus to be powered. +Required properties for phy_type == ulpi: + - nvidia,phy-reset-gpio : The GPIO used to reset the PHY. + Optional properties: - dr_mode : dual role mode. Indicates the working mode for nvidia,tegra20-ehci compatible controllers. Can be "host", "peripheral", diff --git a/arch/arm/boot/dts/tegra-harmony.dts b/arch/arm/boot/dts/tegra-harmony.dts index 1a0b1f182944..59bf1cf6a65c 100644 --- a/arch/arm/boot/dts/tegra-harmony.dts +++ b/arch/arm/boot/dts/tegra-harmony.dts @@ -336,4 +336,8 @@ power-gpios = <&gpio 70 0>; /* gpio PI6 */ support-8bit; }; + + usb@c5004000 { + nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ + }; }; diff --git a/arch/arm/boot/dts/tegra-paz00.dts b/arch/arm/boot/dts/tegra-paz00.dts index 10943fb2561c..fad92f2dbff0 100644 --- a/arch/arm/boot/dts/tegra-paz00.dts +++ b/arch/arm/boot/dts/tegra-paz00.dts @@ -351,4 +351,8 @@ linux,default-trigger = "rfkill0"; }; }; + + usb@c5004000 { + nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */ + }; }; diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra-seaboard.dts index ec33116f5df9..ed0a2f5bf918 100644 --- a/arch/arm/boot/dts/tegra-seaboard.dts +++ b/arch/arm/boot/dts/tegra-seaboard.dts @@ -415,4 +415,8 @@ 0x00000000 0x00000000 0x00000000 0x00000000 >; }; }; + + usb@c5004000 { + nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ + }; }; diff --git a/arch/arm/boot/dts/tegra-trimslice.dts b/arch/arm/boot/dts/tegra-trimslice.dts index 98efd5b0d7f9..71b73aab87ff 100644 --- a/arch/arm/boot/dts/tegra-trimslice.dts +++ b/arch/arm/boot/dts/tegra-trimslice.dts @@ -304,4 +304,8 @@ cd-gpios = <&gpio 121 0>; wp-gpios = <&gpio 122 0>; }; + + usb@c5004000 { + nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */ + }; }; diff --git a/arch/arm/boot/dts/tegra-ventana.dts b/arch/arm/boot/dts/tegra-ventana.dts index 71eb2e50a668..bd074cfb338f 100644 --- a/arch/arm/boot/dts/tegra-ventana.dts +++ b/arch/arm/boot/dts/tegra-ventana.dts @@ -335,4 +335,8 @@ sdhci@c8000600 { support-8bit; }; + + usb@c5004000 { + nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ + }; }; diff --git a/arch/arm/mach-tegra/include/mach/usb_phy.h b/arch/arm/mach-tegra/include/mach/usb_phy.h index de1a0f602b28..935ce9f65590 100644 --- a/arch/arm/mach-tegra/include/mach/usb_phy.h +++ b/arch/arm/mach-tegra/include/mach/usb_phy.h @@ -61,8 +61,8 @@ struct tegra_usb_phy { struct usb_phy *ulpi; }; -struct tegra_usb_phy *tegra_usb_phy_open(int instance, void __iomem *regs, - void *config, enum tegra_usb_phy_mode phy_mode); +struct tegra_usb_phy *tegra_usb_phy_open(struct device *dev, int instance, + void __iomem *regs, void *config, enum tegra_usb_phy_mode phy_mode); int tegra_usb_phy_power_on(struct tegra_usb_phy *phy); diff --git a/arch/arm/mach-tegra/usb_phy.c b/arch/arm/mach-tegra/usb_phy.c index d71d2fed6721..54e353c8e304 100644 --- a/arch/arm/mach-tegra/usb_phy.c +++ b/arch/arm/mach-tegra/usb_phy.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -654,8 +655,8 @@ static void ulpi_phy_power_off(struct tegra_usb_phy *phy) clk_disable(phy->clk); } -struct tegra_usb_phy *tegra_usb_phy_open(int instance, void __iomem *regs, - void *config, enum tegra_usb_phy_mode phy_mode) +struct tegra_usb_phy *tegra_usb_phy_open(struct device *dev, int instance, + void __iomem *regs, void *config, enum tegra_usb_phy_mode phy_mode) { struct tegra_usb_phy *phy; struct tegra_ulpi_config *ulpi_config; @@ -711,6 +712,16 @@ struct tegra_usb_phy *tegra_usb_phy_open(int instance, void __iomem *regs, err = -ENXIO; goto err1; } + if (!gpio_is_valid(ulpi_config->reset_gpio)) + ulpi_config->reset_gpio = + of_get_named_gpio(dev->of_node, + "nvidia,phy-reset-gpio", 0); + if (!gpio_is_valid(ulpi_config->reset_gpio)) { + pr_err("%s: invalid reset gpio: %d\n", __func__, + ulpi_config->reset_gpio); + err = -EINVAL; + goto err1; + } gpio_request(ulpi_config->reset_gpio, "ulpi_phy_reset_b"); gpio_direction_output(ulpi_config->reset_gpio, 0); phy->ulpi = otg_ulpi_create(&ulpi_viewport_access_ops, 0); diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c index 9692bef159f5..14532fe04f5e 100644 --- a/drivers/usb/host/ehci-tegra.c +++ b/drivers/usb/host/ehci-tegra.c @@ -708,8 +708,9 @@ static int tegra_ehci_probe(struct platform_device *pdev) } } - tegra->phy = tegra_usb_phy_open(instance, hcd->regs, pdata->phy_config, - TEGRA_USB_PHY_MODE_HOST); + tegra->phy = tegra_usb_phy_open(&pdev->dev, instance, hcd->regs, + pdata->phy_config, + TEGRA_USB_PHY_MODE_HOST); if (IS_ERR(tegra->phy)) { dev_err(&pdev->dev, "Failed to open USB phy\n"); err = -ENXIO; From 563da21b1d1878736905bbff0f096fcd960d57c5 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 13 Apr 2012 16:35:20 -0600 Subject: [PATCH 13/29] ARM: dt: tegra: pinmux changes for USB ULPI Ensure that the USB ULPI signals are not tri-stated, and have no pull- up or pull-down. Ensure that the pingroup hosting the USB ULPI reset signal (GPIO PV0 or PV1 depending on the board, so UAC) is not tri-stated, and has no pull- up or pull-down. This change appears larger than it is due to the grouping and sorting of the pin configuration data. Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra-harmony.dts | 20 ++++++++++---------- arch/arm/boot/dts/tegra-paz00.dts | 14 +++++--------- arch/arm/boot/dts/tegra-trimslice.dts | 18 +++++++++--------- 3 files changed, 24 insertions(+), 28 deletions(-) diff --git a/arch/arm/boot/dts/tegra-harmony.dts b/arch/arm/boot/dts/tegra-harmony.dts index 59bf1cf6a65c..6857cec8382d 100644 --- a/arch/arm/boot/dts/tegra-harmony.dts +++ b/arch/arm/boot/dts/tegra-harmony.dts @@ -167,28 +167,28 @@ }; conf_ata { nvidia,pins = "ata", "atb", "atc", "atd", "ate", - "cdev1", "dap1", "dtb", "gma", "gmb", - "gmc", "gmd", "gme", "gpu7", "gpv", - "i2cp", "pta", "rm", "slxa", "slxk", - "spia", "spib"; + "cdev1", "cdev2", "dap1", "dtb", "gma", + "gmb", "gmc", "gmd", "gme", "gpu7", + "gpv", "i2cp", "pta", "rm", "slxa", + "slxk", "spia", "spib", "uac"; nvidia,pull = <0>; nvidia,tristate = <0>; }; - conf_cdev2 { - nvidia,pins = "cdev2", "csus", "spid", "spif"; - nvidia,pull = <1>; - nvidia,tristate = <1>; - }; conf_ck32 { nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; nvidia,pull = <0>; }; + conf_csus { + nvidia,pins = "csus", "spid", "spif"; + nvidia,pull = <1>; + nvidia,tristate = <1>; + }; conf_crtp { nvidia,pins = "crtp", "dap2", "dap3", "dap4", "dtc", "dte", "dtf", "gpu", "sdio1", "slxc", "slxd", "spdi", "spdo", "spig", - "uac", "uda"; + "uda"; nvidia,pull = <0>; nvidia,tristate = <1>; }; diff --git a/arch/arm/boot/dts/tegra-paz00.dts b/arch/arm/boot/dts/tegra-paz00.dts index fad92f2dbff0..34a917710e09 100644 --- a/arch/arm/boot/dts/tegra-paz00.dts +++ b/arch/arm/boot/dts/tegra-paz00.dts @@ -159,18 +159,14 @@ }; conf_ata { nvidia,pins = "ata", "atb", "atc", "atd", "ate", - "cdev1", "dap1", "dap2", "dtf", "gma", - "gmb", "gmc", "gmd", "gme", "gpu", - "gpu7", "gpv", "i2cp", "pta", "rm", - "sdio1", "slxk", "spdo", "uac", "uda"; + "cdev1", "cdev2", "dap1", "dap2", "dtf", + "gma", "gmb", "gmc", "gmd", "gme", + "gpu", "gpu7", "gpv", "i2cp", "pta", + "rm", "sdio1", "slxk", "spdo", "uac", + "uda"; nvidia,pull = <0>; nvidia,tristate = <0>; }; - conf_cdev2 { - nvidia,pins = "cdev2"; - nvidia,pull = <1>; - nvidia,tristate = <0>; - }; conf_ck32 { nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; diff --git a/arch/arm/boot/dts/tegra-trimslice.dts b/arch/arm/boot/dts/tegra-trimslice.dts index 71b73aab87ff..e4fcf9a8178a 100644 --- a/arch/arm/boot/dts/tegra-trimslice.dts +++ b/arch/arm/boot/dts/tegra-trimslice.dts @@ -182,23 +182,23 @@ nvidia,tristate = <1>; }; conf_atb { - nvidia,pins = "atb", "cdev1", "dap1", "gma", - "gmc", "gmd", "gpu", "gpu7", "gpv", - "sdio1", "slxa", "slxk", "uac"; + nvidia,pins = "atb", "cdev1", "cdev2", "dap1", + "gma", "gmc", "gmd", "gpu", "gpu7", + "gpv", "sdio1", "slxa", "slxk", "uac"; nvidia,pull = <0>; nvidia,tristate = <0>; }; - conf_cdev2 { - nvidia,pins = "cdev2", "csus", "spia", "spib", - "spid", "spif"; - nvidia,pull = <1>; - nvidia,tristate = <1>; - }; conf_ck32 { nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; nvidia,pull = <0>; }; + conf_csus { + nvidia,pins = "csus", "spia", "spib", + "spid", "spif"; + nvidia,pull = <1>; + nvidia,tristate = <1>; + }; conf_ddc { nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd"; nvidia,pull = <2>; From 7868a9bcac7d98d7437e10eca649d787e2c80d2c Mon Sep 17 00:00:00 2001 From: Hiroshi DOYU Date: Mon, 7 May 2012 09:43:47 +0300 Subject: [PATCH 14/29] ARM: dt: tegra: Add device tree support for AHB Add AHB entry for tegra20/30. Signed-off-by: Hiroshi DOYU Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra20.dtsi | 5 +++++ arch/arm/boot/dts/tegra30.dtsi | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 108e894a8926..24129fb507a5 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -206,5 +206,10 @@ interrupts = < 0 97 0x04 >; phy_type = "utmi"; }; + + ahb: ahb@6000c004 { + compatible = "nvidia,tegra20-ahb"; + reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */ + }; }; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 15200a949a81..9d650fb07e45 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -224,4 +224,9 @@ nvidia,ahub-cif-ids = <8 8>; }; }; + + ahb: ahb@6000c004 { + compatible = "nvidia,tegra30-ahb"; + reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */ + }; }; From 4a82f2b38ee2d8b185a6d5ee2d5783e8a4c8c53d Mon Sep 17 00:00:00 2001 From: "hdoyu@nvidia.com" Date: Wed, 9 May 2012 21:42:31 +0000 Subject: [PATCH 15/29] ARM: dt: tegra20.dtsi: Add Memory Controller(MC) nodes Add Tegra MC(Memory Controller) nodes for tegra20.dtsi. Signed-off-by: Hiroshi DOYU Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra20.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 24129fb507a5..548b42eebd53 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -211,5 +211,12 @@ compatible = "nvidia,tegra20-ahb"; reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */ }; + + mc { + compatible = "nvidia,tegra20-mc"; + reg = <0x7000f000 0x024 + 0x7000f03c 0x3c4>; + interrupts = <0 77 0x04>; + }; }; From ecf43742735d7c1edfd03e8c3cc30f52268138fc Mon Sep 17 00:00:00 2001 From: "hdoyu@nvidia.com" Date: Wed, 9 May 2012 21:42:33 +0000 Subject: [PATCH 16/29] ARM: dt: tegra30.dtsi: Add Memory Controller(MC) nodes Add Tegra MC(Memory Controller) nodes for tegra30.dtsi. Signed-off-by: Hiroshi DOYU Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra30.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 9d650fb07e45..167ccbcd9b86 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -229,4 +229,13 @@ compatible = "nvidia,tegra30-ahb"; reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */ }; + + mc { + compatible = "nvidia,tegra30-mc"; + reg = <0x7000f000 0x010 + 0x7000f03c 0x1b4 + 0x7000f200 0x028 + 0x7000f284 0x17c>; + interrupts = <0 77 0x04>; + }; }; From 6a943e0e13900881ff6b980441233e10a6642904 Mon Sep 17 00:00:00 2001 From: "hdoyu@nvidia.com" Date: Wed, 9 May 2012 21:45:33 +0000 Subject: [PATCH 17/29] ARM: dt: tegra20.dtsi: Add GART node Add a node for the Tegra20 GART Signed-off-by: Hiroshi DOYU Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra20.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 548b42eebd53..a76c8a85020a 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -218,5 +218,11 @@ 0x7000f03c 0x3c4>; interrupts = <0 77 0x04>; }; + + gart { + compatible = "nvidia,tegra20-gart"; + reg = <0x7000f024 0x00000018 /* controller registers */ + 0x58000000 0x02000000>; /* GART aperture */ + }; }; From 54174a33da64536d6840ffa5ae9edc71cb9bf3a1 Mon Sep 17 00:00:00 2001 From: "hdoyu@nvidia.com" Date: Wed, 9 May 2012 21:50:21 +0000 Subject: [PATCH 18/29] ARM: dt: tegra30.dtsi: Add SMMU node Add a node for the Tegra30 SMMU Signed-off-by: Hiroshi DOYU Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra30.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 167ccbcd9b86..e9792ac03635 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -238,4 +238,14 @@ 0x7000f284 0x17c>; interrupts = <0 77 0x04>; }; + + smmu { + compatible = "nvidia,tegra30-smmu"; + reg = <0x7000f010 0x02c + 0x7000f1f0 0x010 + 0x7000f228 0x05c>; + nvidia,#asids = <4>; /* # of ASIDs */ + dma-window = <0 0x40000000>; /* IOVA start & length */ + nvidia,ahb = <&ahb>; + }; }; From 331da58ca179d036a4e03353067f782ae54879e7 Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Thu, 10 May 2012 20:38:45 +0000 Subject: [PATCH 19/29] ARM: dt: tegra: cardhu: register core regulator tps62361 Add device info for the core regulator tps62360 in tegra-cardhu dts file. Signed-off-by: Laxman Dewangan [swarren: fixed node name to reflect actual device type] Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra-cardhu.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/tegra-cardhu.dts b/arch/arm/boot/dts/tegra-cardhu.dts index facb950c4bec..c45775685f72 100644 --- a/arch/arm/boot/dts/tegra-cardhu.dts +++ b/arch/arm/boot/dts/tegra-cardhu.dts @@ -123,6 +123,19 @@ micdet-delay = <100>; gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; }; + + tps62361 { + compatible = "ti,tps62361"; + reg = <0x60>; + + regulator-name = "tps62361-vout"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + ti,vsel0-state-high; + ti,vsel1-state-high; + }; }; sdhci@78000000 { From 1dfebb426cfd16e2080f8c95e00ca2462f2325d4 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 11 May 2012 18:01:38 -0600 Subject: [PATCH 20/29] ARM: dt: tegra cardhu: fix typo in SDHCI node name Cardhu's eMMC controller is on sdhci@78000600, not sdhci@78000400. Fix the typo. This roughly doubles the IO performance, since the support-8bit property actually takes effect. Signed-off-by: Stephen Warren Cc: stable@kernel.org # v3.4 --- arch/arm/boot/dts/tegra-cardhu.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra-cardhu.dts b/arch/arm/boot/dts/tegra-cardhu.dts index c45775685f72..74d1ca4fc1b4 100644 --- a/arch/arm/boot/dts/tegra-cardhu.dts +++ b/arch/arm/boot/dts/tegra-cardhu.dts @@ -152,7 +152,7 @@ status = "disable"; }; - sdhci@78000400 { + sdhci@78000600 { support-8bit; }; From 95decf84742d712a5875bb655cd7440f6d7c1184 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 11 May 2012 16:11:38 -0600 Subject: [PATCH 21/29] ARM: dt: tegra: whitespace cleanup Consistently don't place a space after < or before >. Signed-off-by: Stephen Warren Acked-by: Olof Johansson --- arch/arm/boot/dts/tegra-cardhu.dts | 4 +- arch/arm/boot/dts/tegra-harmony.dts | 8 +- arch/arm/boot/dts/tegra-seaboard.dts | 26 +++--- arch/arm/boot/dts/tegra-trimslice.dts | 4 +- arch/arm/boot/dts/tegra-ventana.dts | 8 +- arch/arm/boot/dts/tegra20.dtsi | 101 +++++++++++----------- arch/arm/boot/dts/tegra30.dtsi | 120 +++++++++++++------------- 7 files changed, 135 insertions(+), 136 deletions(-) diff --git a/arch/arm/boot/dts/tegra-cardhu.dts b/arch/arm/boot/dts/tegra-cardhu.dts index 74d1ca4fc1b4..378b65e186e8 100644 --- a/arch/arm/boot/dts/tegra-cardhu.dts +++ b/arch/arm/boot/dts/tegra-cardhu.dts @@ -7,7 +7,7 @@ compatible = "nvidia,cardhu", "nvidia,tegra30"; memory { - reg = < 0x80000000 0x40000000 >; + reg = <0x80000000 0x40000000>; }; pinmux@70000000 { @@ -64,7 +64,7 @@ }; serial@70006000 { - clock-frequency = < 408000000 >; + clock-frequency = <408000000>; }; serial@70006040 { diff --git a/arch/arm/boot/dts/tegra-harmony.dts b/arch/arm/boot/dts/tegra-harmony.dts index 6857cec8382d..04647b3175db 100644 --- a/arch/arm/boot/dts/tegra-harmony.dts +++ b/arch/arm/boot/dts/tegra-harmony.dts @@ -7,7 +7,7 @@ compatible = "nvidia,harmony", "nvidia,tegra20"; memory@0 { - reg = < 0x00000000 0x40000000 >; + reg = <0x00000000 0x40000000>; }; pinmux@70000000 { @@ -245,14 +245,14 @@ compatible = "wlf,wm8903"; reg = <0x1a>; interrupt-parent = <&gpio>; - interrupts = < 187 0x04 >; + interrupts = <187 0x04>; gpio-controller; #gpio-cells = <2>; micdet-cfg = <0>; micdet-delay = <100>; - gpio-cfg = < 0xffffffff 0xffffffff 0 0xffffffff 0xffffffff >; + gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; }; }; @@ -309,7 +309,7 @@ }; serial@70006300 { - clock-frequency = < 216000000 >; + clock-frequency = <216000000>; }; serial@70006400 { diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra-seaboard.dts index c4d171ec9ee4..d4cbd8054c07 100644 --- a/arch/arm/boot/dts/tegra-seaboard.dts +++ b/arch/arm/boot/dts/tegra-seaboard.dts @@ -8,7 +8,7 @@ memory { device_type = "memory"; - reg = < 0x00000000 0x40000000 >; + reg = <0x00000000 0x40000000>; }; pinmux@70000000 { @@ -265,14 +265,14 @@ compatible = "wlf,wm8903"; reg = <0x1a>; interrupt-parent = <&gpio>; - interrupts = < 187 0x04 >; + interrupts = <187 0x04>; gpio-controller; #gpio-cells = <2>; micdet-cfg = <0>; micdet-delay = <100>; - gpio-cfg = < 0xffffffff 0xffffffff 0 0xffffffff 0xffffffff >; + gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; }; /* ALS and proximity sensor */ @@ -280,7 +280,7 @@ compatible = "isil,isl29018"; reg = <0x44>; interrupt-parent = <&gpio>; - interrupts = < 202 0x04 >; /* GPIO PZ2 */ + interrupts = <202 0x04>; /* GPIO PZ2 */ }; gyrometer@68 { @@ -361,7 +361,7 @@ }; serial@70006300 { - clock-frequency = < 216000000 >; + clock-frequency = <216000000>; }; serial@70006400 { @@ -413,10 +413,10 @@ emc@7000f400 { emc-table@190000 { - reg = < 190000 >; + reg = <190000>; compatible = "nvidia,tegra20-emc-table"; - clock-frequency = < 190000 >; - nvidia,emc-registers = < 0x0000000c 0x00000026 + clock-frequency = <190000>; + nvidia,emc-registers = <0x0000000c 0x00000026 0x00000009 0x00000003 0x00000004 0x00000004 0x00000002 0x0000000c 0x00000003 0x00000003 0x00000002 0x00000001 0x00000004 0x00000005 @@ -427,14 +427,14 @@ 0x00000002 0x00000000 0x00000000 0x00000002 0x00000000 0x00000000 0x00000083 0xa06204ae 0x007dc010 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 >; + 0x00000000 0x00000000 0x00000000 0x00000000>; }; emc-table@380000 { - reg = < 380000 >; + reg = <380000>; compatible = "nvidia,tegra20-emc-table"; - clock-frequency = < 380000 >; - nvidia,emc-registers = < 0x00000017 0x0000004b + clock-frequency = <380000>; + nvidia,emc-registers = <0x00000017 0x0000004b 0x00000012 0x00000006 0x00000004 0x00000005 0x00000003 0x0000000c 0x00000006 0x00000006 0x00000003 0x00000001 0x00000004 0x00000005 @@ -445,7 +445,7 @@ 0x00000002 0x00000000 0x00000000 0x00000002 0x00000000 0x00000000 0x00000083 0xe044048b 0x007d8010 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 >; + 0x00000000 0x00000000 0x00000000 0x00000000>; }; }; diff --git a/arch/arm/boot/dts/tegra-trimslice.dts b/arch/arm/boot/dts/tegra-trimslice.dts index ead93657dd06..7181a5e9e48b 100644 --- a/arch/arm/boot/dts/tegra-trimslice.dts +++ b/arch/arm/boot/dts/tegra-trimslice.dts @@ -7,7 +7,7 @@ compatible = "compulab,trimslice", "nvidia,tegra20"; memory@0 { - reg = < 0x00000000 0x40000000 >; + reg = <0x00000000 0x40000000>; }; pinmux@70000000 { @@ -277,7 +277,7 @@ }; serial@70006000 { - clock-frequency = < 216000000 >; + clock-frequency = <216000000>; }; serial@70006040 { diff --git a/arch/arm/boot/dts/tegra-ventana.dts b/arch/arm/boot/dts/tegra-ventana.dts index c20d5e93f9c9..9d2bc270b35b 100644 --- a/arch/arm/boot/dts/tegra-ventana.dts +++ b/arch/arm/boot/dts/tegra-ventana.dts @@ -7,7 +7,7 @@ compatible = "nvidia,ventana", "nvidia,tegra20"; memory { - reg = < 0x00000000 0x40000000 >; + reg = <0x00000000 0x40000000>; }; pinmux@70000000 { @@ -247,14 +247,14 @@ compatible = "wlf,wm8903"; reg = <0x1a>; interrupt-parent = <&gpio>; - interrupts = < 187 0x04 >; + interrupts = <187 0x04>; gpio-controller; #gpio-cells = <2>; micdet-cfg = <0>; micdet-delay = <100>; - gpio-cfg = < 0xffffffff 0xffffffff 0 0xffffffff 0xffffffff >; + gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; }; /* ALS and proximity sensor */ @@ -319,7 +319,7 @@ }; serial@70006300 { - clock-frequency = < 216000000 >; + clock-frequency = <216000000>; }; serial@70006400 { diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index a76c8a85020a..f98be33da708 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -13,8 +13,8 @@ compatible = "arm,cortex-a9-gic"; interrupt-controller; #interrupt-cells = <3>; - reg = < 0x50041000 0x1000 >, - < 0x50040100 0x0100 >; + reg = <0x50041000 0x1000>, + <0x50040100 0x0100>; }; pmu { @@ -26,22 +26,22 @@ apbdma: dma@6000a000 { compatible = "nvidia,tegra20-apbdma"; reg = <0x6000a000 0x1200>; - interrupts = < 0 104 0x04 - 0 105 0x04 - 0 106 0x04 - 0 107 0x04 - 0 108 0x04 - 0 109 0x04 - 0 110 0x04 - 0 111 0x04 - 0 112 0x04 - 0 113 0x04 - 0 114 0x04 - 0 115 0x04 - 0 116 0x04 - 0 117 0x04 - 0 118 0x04 - 0 119 0x04 >; + interrupts = <0 104 0x04 + 0 105 0x04 + 0 106 0x04 + 0 107 0x04 + 0 108 0x04 + 0 109 0x04 + 0 110 0x04 + 0 111 0x04 + 0 112 0x04 + 0 113 0x04 + 0 114 0x04 + 0 115 0x04 + 0 116 0x04 + 0 117 0x04 + 0 118 0x04 + 0 119 0x04>; }; i2c@7000c000 { @@ -49,7 +49,7 @@ #size-cells = <0>; compatible = "nvidia,tegra20-i2c"; reg = <0x7000C000 0x100>; - interrupts = < 0 38 0x04 >; + interrupts = <0 38 0x04>; }; i2c@7000c400 { @@ -57,7 +57,7 @@ #size-cells = <0>; compatible = "nvidia,tegra20-i2c"; reg = <0x7000C400 0x100>; - interrupts = < 0 84 0x04 >; + interrupts = <0 84 0x04>; }; i2c@7000c500 { @@ -65,7 +65,7 @@ #size-cells = <0>; compatible = "nvidia,tegra20-i2c"; reg = <0x7000C500 0x100>; - interrupts = < 0 92 0x04 >; + interrupts = <0 92 0x04>; }; i2c@7000d000 { @@ -73,21 +73,21 @@ #size-cells = <0>; compatible = "nvidia,tegra20-i2c-dvc"; reg = <0x7000D000 0x200>; - interrupts = < 0 53 0x04 >; + interrupts = <0 53 0x04>; }; tegra_i2s1: i2s@70002800 { compatible = "nvidia,tegra20-i2s"; reg = <0x70002800 0x200>; - interrupts = < 0 13 0x04 >; - nvidia,dma-request-selector = < &apbdma 2 >; + interrupts = <0 13 0x04>; + nvidia,dma-request-selector = <&apbdma 2>; }; tegra_i2s2: i2s@70002a00 { compatible = "nvidia,tegra20-i2s"; reg = <0x70002a00 0x200>; - interrupts = < 0 3 0x04 >; - nvidia,dma-request-selector = < &apbdma 1 >; + interrupts = <0 3 0x04>; + nvidia,dma-request-selector = <&apbdma 1>; }; das@70000c00 { @@ -97,14 +97,14 @@ gpio: gpio@6000d000 { compatible = "nvidia,tegra20-gpio"; - reg = < 0x6000d000 0x1000 >; - interrupts = < 0 32 0x04 - 0 33 0x04 - 0 34 0x04 - 0 35 0x04 - 0 55 0x04 - 0 87 0x04 - 0 89 0x04 >; + reg = <0x6000d000 0x1000>; + interrupts = <0 32 0x04 + 0 33 0x04 + 0 34 0x04 + 0 35 0x04 + 0 55 0x04 + 0 87 0x04 + 0 89 0x04>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; @@ -113,45 +113,45 @@ pinmux: pinmux@70000000 { compatible = "nvidia,tegra20-pinmux"; - reg = < 0x70000014 0x10 /* Tri-state registers */ - 0x70000080 0x20 /* Mux registers */ - 0x700000a0 0x14 /* Pull-up/down registers */ - 0x70000868 0xa8 >; /* Pad control registers */ + reg = <0x70000014 0x10 /* Tri-state registers */ + 0x70000080 0x20 /* Mux registers */ + 0x700000a0 0x14 /* Pull-up/down registers */ + 0x70000868 0xa8>; /* Pad control registers */ }; serial@70006000 { compatible = "nvidia,tegra20-uart"; reg = <0x70006000 0x40>; reg-shift = <2>; - interrupts = < 0 36 0x04 >; + interrupts = <0 36 0x04>; }; serial@70006040 { compatible = "nvidia,tegra20-uart"; reg = <0x70006040 0x40>; reg-shift = <2>; - interrupts = < 0 37 0x04 >; + interrupts = <0 37 0x04>; }; serial@70006200 { compatible = "nvidia,tegra20-uart"; reg = <0x70006200 0x100>; reg-shift = <2>; - interrupts = < 0 46 0x04 >; + interrupts = <0 46 0x04>; }; serial@70006300 { compatible = "nvidia,tegra20-uart"; reg = <0x70006300 0x100>; reg-shift = <2>; - interrupts = < 0 90 0x04 >; + interrupts = <0 90 0x04>; }; serial@70006400 { compatible = "nvidia,tegra20-uart"; reg = <0x70006400 0x100>; reg-shift = <2>; - interrupts = < 0 91 0x04 >; + interrupts = <0 91 0x04>; }; emc@7000f400 { @@ -164,31 +164,31 @@ sdhci@c8000000 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000000 0x200>; - interrupts = < 0 14 0x04 >; + interrupts = <0 14 0x04>; }; sdhci@c8000200 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000200 0x200>; - interrupts = < 0 15 0x04 >; + interrupts = <0 15 0x04>; }; sdhci@c8000400 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000400 0x200>; - interrupts = < 0 19 0x04 >; + interrupts = <0 19 0x04>; }; sdhci@c8000600 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000600 0x200>; - interrupts = < 0 31 0x04 >; + interrupts = <0 31 0x04>; }; usb@c5000000 { compatible = "nvidia,tegra20-ehci", "usb-ehci"; reg = <0xc5000000 0x4000>; - interrupts = < 0 20 0x04 >; + interrupts = <0 20 0x04>; phy_type = "utmi"; nvidia,has-legacy-mode; }; @@ -196,14 +196,14 @@ usb@c5004000 { compatible = "nvidia,tegra20-ehci", "usb-ehci"; reg = <0xc5004000 0x4000>; - interrupts = < 0 21 0x04 >; + interrupts = <0 21 0x04>; phy_type = "ulpi"; }; usb@c5008000 { compatible = "nvidia,tegra20-ehci", "usb-ehci"; reg = <0xc5008000 0x4000>; - interrupts = < 0 97 0x04 >; + interrupts = <0 97 0x04>; phy_type = "utmi"; }; @@ -225,4 +225,3 @@ 0x58000000 0x02000000>; /* GART aperture */ }; }; - diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index e9792ac03635..5dd6556fce01 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -13,8 +13,8 @@ compatible = "arm,cortex-a9-gic"; interrupt-controller; #interrupt-cells = <3>; - reg = < 0x50041000 0x1000 >, - < 0x50040100 0x0100 >; + reg = <0x50041000 0x1000>, + <0x50040100 0x0100>; }; pmu { @@ -28,38 +28,38 @@ apbdma: dma@6000a000 { compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; reg = <0x6000a000 0x1400>; - interrupts = < 0 104 0x04 - 0 105 0x04 - 0 106 0x04 - 0 107 0x04 - 0 108 0x04 - 0 109 0x04 - 0 110 0x04 - 0 111 0x04 - 0 112 0x04 - 0 113 0x04 - 0 114 0x04 - 0 115 0x04 - 0 116 0x04 - 0 117 0x04 - 0 118 0x04 - 0 119 0x04 - 0 128 0x04 - 0 129 0x04 - 0 130 0x04 - 0 131 0x04 - 0 132 0x04 - 0 133 0x04 - 0 134 0x04 - 0 135 0x04 - 0 136 0x04 - 0 137 0x04 - 0 138 0x04 - 0 139 0x04 - 0 140 0x04 - 0 141 0x04 - 0 142 0x04 - 0 143 0x04 >; + interrupts = <0 104 0x04 + 0 105 0x04 + 0 106 0x04 + 0 107 0x04 + 0 108 0x04 + 0 109 0x04 + 0 110 0x04 + 0 111 0x04 + 0 112 0x04 + 0 113 0x04 + 0 114 0x04 + 0 115 0x04 + 0 116 0x04 + 0 117 0x04 + 0 118 0x04 + 0 119 0x04 + 0 128 0x04 + 0 129 0x04 + 0 130 0x04 + 0 131 0x04 + 0 132 0x04 + 0 133 0x04 + 0 134 0x04 + 0 135 0x04 + 0 136 0x04 + 0 137 0x04 + 0 138 0x04 + 0 139 0x04 + 0 140 0x04 + 0 141 0x04 + 0 142 0x04 + 0 143 0x04>; }; i2c@7000c000 { @@ -67,7 +67,7 @@ #size-cells = <0>; compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; reg = <0x7000C000 0x100>; - interrupts = < 0 38 0x04 >; + interrupts = <0 38 0x04>; }; i2c@7000c400 { @@ -75,7 +75,7 @@ #size-cells = <0>; compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; reg = <0x7000C400 0x100>; - interrupts = < 0 84 0x04 >; + interrupts = <0 84 0x04>; }; i2c@7000c500 { @@ -83,7 +83,7 @@ #size-cells = <0>; compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; reg = <0x7000C500 0x100>; - interrupts = < 0 92 0x04 >; + interrupts = <0 92 0x04>; }; i2c@7000c700 { @@ -91,7 +91,7 @@ #size-cells = <0>; compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; reg = <0x7000c700 0x100>; - interrupts = < 0 120 0x04 >; + interrupts = <0 120 0x04>; }; i2c@7000d000 { @@ -99,20 +99,20 @@ #size-cells = <0>; compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; reg = <0x7000D000 0x100>; - interrupts = < 0 53 0x04 >; + interrupts = <0 53 0x04>; }; gpio: gpio@6000d000 { compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio"; - reg = < 0x6000d000 0x1000 >; - interrupts = < 0 32 0x04 - 0 33 0x04 - 0 34 0x04 - 0 35 0x04 - 0 55 0x04 - 0 87 0x04 - 0 89 0x04 - 0 125 0x04 >; + reg = <0x6000d000 0x1000>; + interrupts = <0 32 0x04 + 0 33 0x04 + 0 34 0x04 + 0 35 0x04 + 0 55 0x04 + 0 87 0x04 + 0 89 0x04 + 0 125 0x04>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; @@ -123,71 +123,71 @@ compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; reg = <0x70006000 0x40>; reg-shift = <2>; - interrupts = < 0 36 0x04 >; + interrupts = <0 36 0x04>; }; serial@70006040 { compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; reg = <0x70006040 0x40>; reg-shift = <2>; - interrupts = < 0 37 0x04 >; + interrupts = <0 37 0x04>; }; serial@70006200 { compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; reg = <0x70006200 0x100>; reg-shift = <2>; - interrupts = < 0 46 0x04 >; + interrupts = <0 46 0x04>; }; serial@70006300 { compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; reg = <0x70006300 0x100>; reg-shift = <2>; - interrupts = < 0 90 0x04 >; + interrupts = <0 90 0x04>; }; serial@70006400 { compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; reg = <0x70006400 0x100>; reg-shift = <2>; - interrupts = < 0 91 0x04 >; + interrupts = <0 91 0x04>; }; sdhci@78000000 { compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; reg = <0x78000000 0x200>; - interrupts = < 0 14 0x04 >; + interrupts = <0 14 0x04>; }; sdhci@78000200 { compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; reg = <0x78000200 0x200>; - interrupts = < 0 15 0x04 >; + interrupts = <0 15 0x04>; }; sdhci@78000400 { compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; reg = <0x78000400 0x200>; - interrupts = < 0 19 0x04 >; + interrupts = <0 19 0x04>; }; sdhci@78000600 { compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; reg = <0x78000600 0x200>; - interrupts = < 0 31 0x04 >; + interrupts = <0 31 0x04>; }; pinmux: pinmux@70000000 { compatible = "nvidia,tegra30-pinmux"; - reg = < 0x70000868 0xd0 /* Pad control registers */ - 0x70003000 0x3e0 >; /* Mux registers */ + reg = <0x70000868 0xd0 /* Pad control registers */ + 0x70003000 0x3e0>; /* Mux registers */ }; ahub { compatible = "nvidia,tegra30-ahub"; reg = <0x70080000 0x200 0x70080200 0x100>; - interrupts = < 0 103 0x04 >; + interrupts = <0 103 0x04>; nvidia,dma-request-selector = <&apbdma 1>; ranges; From f9eb26a4e11c63bba2fb71b58dff5ed6f33091f9 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 11 May 2012 16:17:47 -0600 Subject: [PATCH 22/29] ARM: dt: tegra: remove unnecessary unit addresses DT node names only need to include the unit address if it's required to make the node name unique. Remove the unnecessary unit addresses. Signed-off-by: Stephen Warren Acked-by: Olof Johansson --- arch/arm/boot/dts/tegra-cardhu.dts | 4 ++-- arch/arm/boot/dts/tegra-harmony.dts | 6 +++--- arch/arm/boot/dts/tegra-paz00.dts | 6 +++--- arch/arm/boot/dts/tegra-seaboard.dts | 4 ++-- arch/arm/boot/dts/tegra-trimslice.dts | 4 ++-- arch/arm/boot/dts/tegra-ventana.dts | 2 +- arch/arm/boot/dts/tegra20.dtsi | 16 ++++++++-------- arch/arm/boot/dts/tegra30.dtsi | 12 ++++++------ 8 files changed, 27 insertions(+), 27 deletions(-) diff --git a/arch/arm/boot/dts/tegra-cardhu.dts b/arch/arm/boot/dts/tegra-cardhu.dts index 378b65e186e8..653d62891791 100644 --- a/arch/arm/boot/dts/tegra-cardhu.dts +++ b/arch/arm/boot/dts/tegra-cardhu.dts @@ -10,7 +10,7 @@ reg = <0x80000000 0x40000000>; }; - pinmux@70000000 { + pinmux { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -156,7 +156,7 @@ support-8bit; }; - ahub@70080000 { + ahub { i2s@70080300 { status = "disable"; }; diff --git a/arch/arm/boot/dts/tegra-harmony.dts b/arch/arm/boot/dts/tegra-harmony.dts index 04647b3175db..759e289e7f87 100644 --- a/arch/arm/boot/dts/tegra-harmony.dts +++ b/arch/arm/boot/dts/tegra-harmony.dts @@ -6,11 +6,11 @@ model = "NVIDIA Tegra2 Harmony evaluation board"; compatible = "nvidia,harmony", "nvidia,tegra20"; - memory@0 { + memory { reg = <0x00000000 0x40000000>; }; - pinmux@70000000 { + pinmux { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -234,7 +234,7 @@ }; }; - pmc@7000f400 { + pmc { nvidia,invert-interrupt; }; diff --git a/arch/arm/boot/dts/tegra-paz00.dts b/arch/arm/boot/dts/tegra-paz00.dts index 34a917710e09..4983ef116831 100644 --- a/arch/arm/boot/dts/tegra-paz00.dts +++ b/arch/arm/boot/dts/tegra-paz00.dts @@ -6,11 +6,11 @@ model = "Toshiba AC100 / Dynabook AZ"; compatible = "compal,paz00", "nvidia,tegra20"; - memory@0 { + memory { reg = <0x00000000 0x20000000>; }; - pinmux@70000000 { + pinmux { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -245,7 +245,7 @@ status = "disable"; }; - nvec@7000c500 { + nvec { #address-cells = <1>; #size-cells = <0>; compatible = "nvidia,nvec"; diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra-seaboard.dts index d4cbd8054c07..ea93332ef9a0 100644 --- a/arch/arm/boot/dts/tegra-seaboard.dts +++ b/arch/arm/boot/dts/tegra-seaboard.dts @@ -11,7 +11,7 @@ reg = <0x00000000 0x40000000>; }; - pinmux@70000000 { + pinmux { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -411,7 +411,7 @@ }; }; - emc@7000f400 { + emc { emc-table@190000 { reg = <190000>; compatible = "nvidia,tegra20-emc-table"; diff --git a/arch/arm/boot/dts/tegra-trimslice.dts b/arch/arm/boot/dts/tegra-trimslice.dts index 7181a5e9e48b..4436b42be4a2 100644 --- a/arch/arm/boot/dts/tegra-trimslice.dts +++ b/arch/arm/boot/dts/tegra-trimslice.dts @@ -6,11 +6,11 @@ model = "Compulab TrimSlice board"; compatible = "compulab,trimslice", "nvidia,tegra20"; - memory@0 { + memory { reg = <0x00000000 0x40000000>; }; - pinmux@70000000 { + pinmux { pinctrl-names = "default"; pinctrl-0 = <&state_default>; diff --git a/arch/arm/boot/dts/tegra-ventana.dts b/arch/arm/boot/dts/tegra-ventana.dts index 9d2bc270b35b..0c8d30d9c2fa 100644 --- a/arch/arm/boot/dts/tegra-ventana.dts +++ b/arch/arm/boot/dts/tegra-ventana.dts @@ -10,7 +10,7 @@ reg = <0x00000000 0x40000000>; }; - pinmux@70000000 { + pinmux { pinctrl-names = "default"; pinctrl-0 = <&state_default>; diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index f98be33da708..a6b135164ae0 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -4,12 +4,12 @@ compatible = "nvidia,tegra20"; interrupt-parent = <&intc>; - pmc@7000f400 { + pmc { compatible = "nvidia,tegra20-pmc"; reg = <0x7000e400 0x400>; }; - intc: interrupt-controller@50041000 { + intc: interrupt-controller { compatible = "arm,cortex-a9-gic"; interrupt-controller; #interrupt-cells = <3>; @@ -23,7 +23,7 @@ 0 57 0x04>; }; - apbdma: dma@6000a000 { + apbdma: dma { compatible = "nvidia,tegra20-apbdma"; reg = <0x6000a000 0x1200>; interrupts = <0 104 0x04 @@ -90,12 +90,12 @@ nvidia,dma-request-selector = <&apbdma 1>; }; - das@70000c00 { + das { compatible = "nvidia,tegra20-das"; reg = <0x70000c00 0x80>; }; - gpio: gpio@6000d000 { + gpio: gpio { compatible = "nvidia,tegra20-gpio"; reg = <0x6000d000 0x1000>; interrupts = <0 32 0x04 @@ -111,7 +111,7 @@ interrupt-controller; }; - pinmux: pinmux@70000000 { + pinmux: pinmux { compatible = "nvidia,tegra20-pinmux"; reg = <0x70000014 0x10 /* Tri-state registers */ 0x70000080 0x20 /* Mux registers */ @@ -154,7 +154,7 @@ interrupts = <0 91 0x04>; }; - emc@7000f400 { + emc { #address-cells = <1>; #size-cells = <0>; compatible = "nvidia,tegra20-emc"; @@ -207,7 +207,7 @@ phy_type = "utmi"; }; - ahb: ahb@6000c004 { + ahb { compatible = "nvidia,tegra20-ahb"; reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */ }; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 5dd6556fce01..45547ad82972 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -4,12 +4,12 @@ compatible = "nvidia,tegra30"; interrupt-parent = <&intc>; - pmc@7000f400 { + pmc { compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc"; reg = <0x7000e400 0x400>; }; - intc: interrupt-controller@50041000 { + intc: interrupt-controller { compatible = "arm,cortex-a9-gic"; interrupt-controller; #interrupt-cells = <3>; @@ -25,7 +25,7 @@ 0 147 0x04>; }; - apbdma: dma@6000a000 { + apbdma: dma { compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; reg = <0x6000a000 0x1400>; interrupts = <0 104 0x04 @@ -102,7 +102,7 @@ interrupts = <0 53 0x04>; }; - gpio: gpio@6000d000 { + gpio: gpio { compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio"; reg = <0x6000d000 0x1000>; interrupts = <0 32 0x04 @@ -178,7 +178,7 @@ interrupts = <0 31 0x04>; }; - pinmux: pinmux@70000000 { + pinmux: pinmux { compatible = "nvidia,tegra30-pinmux"; reg = <0x70000868 0xd0 /* Pad control registers */ 0x70003000 0x3e0>; /* Mux registers */ @@ -225,7 +225,7 @@ }; }; - ahb: ahb@6000c004 { + ahb: ahb { compatible = "nvidia,tegra30-ahb"; reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */ }; From c44e438a7ff53b14d0fc433258b93948e1884f22 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 11 May 2012 16:21:10 -0600 Subject: [PATCH 23/29] ARM: dt: tegra: gpio comment cleanup Ensure that all Tegraa GPIO specifiers contain a comment indicating which GPIO name the number refers to. Signed-off-by: Stephen Warren Acked-by: Olof Johansson --- arch/arm/boot/dts/tegra-paz00.dts | 4 ++-- arch/arm/boot/dts/tegra-trimslice.dts | 4 ++-- arch/arm/boot/dts/tegra-ventana.dts | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/tegra-paz00.dts b/arch/arm/boot/dts/tegra-paz00.dts index 4983ef116831..03b2e65c4278 100644 --- a/arch/arm/boot/dts/tegra-paz00.dts +++ b/arch/arm/boot/dts/tegra-paz00.dts @@ -252,7 +252,7 @@ reg = <0x7000C500 0x100>; interrupts = <0 92 0x04>; clock-frequency = <80000>; - request-gpios = <&gpio 170 0>; + request-gpios = <&gpio 170 0>; /* gpio PV2 */ slave-addr = <138>; }; @@ -343,7 +343,7 @@ wifi { label = "wifi-led"; - gpios = <&gpio 24 0>; + gpios = <&gpio 24 0>; /* gpio PD0 */ linux,default-trigger = "rfkill0"; }; }; diff --git a/arch/arm/boot/dts/tegra-trimslice.dts b/arch/arm/boot/dts/tegra-trimslice.dts index 4436b42be4a2..eebcf504d12d 100644 --- a/arch/arm/boot/dts/tegra-trimslice.dts +++ b/arch/arm/boot/dts/tegra-trimslice.dts @@ -305,8 +305,8 @@ }; sdhci@c8000600 { - cd-gpios = <&gpio 121 0>; - wp-gpios = <&gpio 122 0>; + cd-gpios = <&gpio 121 0>; /* gpio PP1 */ + wp-gpios = <&gpio 122 0>; /* gpio PP2 */ }; usb@c5004000 { diff --git a/arch/arm/boot/dts/tegra-ventana.dts b/arch/arm/boot/dts/tegra-ventana.dts index 0c8d30d9c2fa..e64318d595d5 100644 --- a/arch/arm/boot/dts/tegra-ventana.dts +++ b/arch/arm/boot/dts/tegra-ventana.dts @@ -302,7 +302,7 @@ nvidia,spkr-en-gpios = <&wm8903 2 0>; nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ - nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */ + nvidia,int-mic-en-gpios = <&gpio 184 0>; /* gpio PX0 */ nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */ }; From 5ff488875b982f5a1acc02ba74b23d2802d2613a Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 11 May 2012 16:26:03 -0600 Subject: [PATCH 24/29] ARM: dt: tegra: format regs properties consistently Place each reg "entry" on its own line, and wrap the whole list in <> rather than each individual entry. The convention chosen here is slightly arbitrary, but is not consistent throughout all Tegra files. Signed-off-by: Stephen Warren Acked-by: Olof Johansson --- arch/arm/boot/dts/tegra20.dtsi | 4 ++-- arch/arm/boot/dts/tegra30.dtsi | 7 ++++--- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index a6b135164ae0..7f718bd03452 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -13,8 +13,8 @@ compatible = "arm,cortex-a9-gic"; interrupt-controller; #interrupt-cells = <3>; - reg = <0x50041000 0x1000>, - <0x50040100 0x0100>; + reg = <0x50041000 0x1000 + 0x50040100 0x0100>; }; pmu { diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 45547ad82972..b52378a06fb3 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -13,8 +13,8 @@ compatible = "arm,cortex-a9-gic"; interrupt-controller; #interrupt-cells = <3>; - reg = <0x50041000 0x1000>, - <0x50040100 0x0100>; + reg = <0x50041000 0x1000 + 0x50040100 0x0100>; }; pmu { @@ -186,7 +186,8 @@ ahub { compatible = "nvidia,tegra30-ahub"; - reg = <0x70080000 0x200 0x70080200 0x100>; + reg = <0x70080000 0x200 + 0x70080200 0x100>; interrupts = <0 103 0x04>; nvidia,dma-request-selector = <&apbdma 1>; From ba04c289bc9bae0f381797f58615c7b3989c5e8c Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 11 May 2012 16:28:59 -0600 Subject: [PATCH 25/29] ARM: dt: tegra: consistenly use lower-case for hex constants Signed-off-by: Stephen Warren Acked-by: Olof Johansson --- arch/arm/boot/dts/tegra-paz00.dts | 2 +- arch/arm/boot/dts/tegra20.dtsi | 8 ++++---- arch/arm/boot/dts/tegra30.dtsi | 8 ++++---- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/tegra-paz00.dts b/arch/arm/boot/dts/tegra-paz00.dts index 03b2e65c4278..d469322afbb8 100644 --- a/arch/arm/boot/dts/tegra-paz00.dts +++ b/arch/arm/boot/dts/tegra-paz00.dts @@ -249,7 +249,7 @@ #address-cells = <1>; #size-cells = <0>; compatible = "nvidia,nvec"; - reg = <0x7000C500 0x100>; + reg = <0x7000c500 0x100>; interrupts = <0 92 0x04>; clock-frequency = <80000>; request-gpios = <&gpio 170 0>; /* gpio PV2 */ diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 7f718bd03452..5f9110af43b1 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -48,7 +48,7 @@ #address-cells = <1>; #size-cells = <0>; compatible = "nvidia,tegra20-i2c"; - reg = <0x7000C000 0x100>; + reg = <0x7000c000 0x100>; interrupts = <0 38 0x04>; }; @@ -56,7 +56,7 @@ #address-cells = <1>; #size-cells = <0>; compatible = "nvidia,tegra20-i2c"; - reg = <0x7000C400 0x100>; + reg = <0x7000c400 0x100>; interrupts = <0 84 0x04>; }; @@ -64,7 +64,7 @@ #address-cells = <1>; #size-cells = <0>; compatible = "nvidia,tegra20-i2c"; - reg = <0x7000C500 0x100>; + reg = <0x7000c500 0x100>; interrupts = <0 92 0x04>; }; @@ -72,7 +72,7 @@ #address-cells = <1>; #size-cells = <0>; compatible = "nvidia,tegra20-i2c-dvc"; - reg = <0x7000D000 0x200>; + reg = <0x7000d000 0x200>; interrupts = <0 53 0x04>; }; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index b52378a06fb3..ea829f5bae01 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -66,7 +66,7 @@ #address-cells = <1>; #size-cells = <0>; compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; - reg = <0x7000C000 0x100>; + reg = <0x7000c000 0x100>; interrupts = <0 38 0x04>; }; @@ -74,7 +74,7 @@ #address-cells = <1>; #size-cells = <0>; compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; - reg = <0x7000C400 0x100>; + reg = <0x7000c400 0x100>; interrupts = <0 84 0x04>; }; @@ -82,7 +82,7 @@ #address-cells = <1>; #size-cells = <0>; compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; - reg = <0x7000C500 0x100>; + reg = <0x7000c500 0x100>; interrupts = <0 92 0x04>; }; @@ -98,7 +98,7 @@ #address-cells = <1>; #size-cells = <0>; compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; - reg = <0x7000D000 0x100>; + reg = <0x7000d000 0x100>; interrupts = <0 53 0x04>; }; From 2f32b1faa8c75e2e987c5b714ae25491d8477da5 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 11 May 2012 17:06:44 -0600 Subject: [PATCH 26/29] ARM: dt: tegra: remove duplicate device_type property It's already specified in skeleton.dtsi, included via tegra20.dtsi. Signed-off-by: Stephen Warren Acked-by: Olof Johansson --- arch/arm/boot/dts/tegra-seaboard.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra-seaboard.dts index ea93332ef9a0..c935a2871846 100644 --- a/arch/arm/boot/dts/tegra-seaboard.dts +++ b/arch/arm/boot/dts/tegra-seaboard.dts @@ -7,7 +7,6 @@ compatible = "nvidia,seaboard", "nvidia,tegra20"; memory { - device_type = "memory"; reg = <0x00000000 0x40000000>; }; From c04abb3a07b56db4756b6f970609e65a8624b0a3 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 11 May 2012 17:03:26 -0600 Subject: [PATCH 27/29] ARM: dt: tegra: sort nodes based on bus order Sort the nodes according to the following rules: * First, any overrides for properties or nodes created by included files, in the order they appeared in the include file. * Second, any nodes with a reg property, in numerical order. * Third, any nodes without a reg property, in alphabetical order of node name. The second sorting rule at least will probably help if/when we need to explicitly insert nodes for the various busses in Tegra; that will just be an indentation change rather than also a node re-ordering. Signed-off-by: Stephen Warren Acked-by: Olof Johansson --- arch/arm/boot/dts/tegra-cardhu.dts | 36 ++--- arch/arm/boot/dts/tegra-harmony.dts | 96 ++++++------ arch/arm/boot/dts/tegra-paz00.dts | 88 +++++------ arch/arm/boot/dts/tegra-seaboard.dts | 178 ++++++++++----------- arch/arm/boot/dts/tegra-trimslice.dts | 60 ++++---- arch/arm/boot/dts/tegra-ventana.dts | 86 +++++------ arch/arm/boot/dts/tegra20.dtsi | 196 +++++++++++------------ arch/arm/boot/dts/tegra30.dtsi | 214 +++++++++++++------------- 8 files changed, 477 insertions(+), 477 deletions(-) diff --git a/arch/arm/boot/dts/tegra-cardhu.dts b/arch/arm/boot/dts/tegra-cardhu.dts index 653d62891791..3b5cd7b07553 100644 --- a/arch/arm/boot/dts/tegra-cardhu.dts +++ b/arch/arm/boot/dts/tegra-cardhu.dts @@ -138,24 +138,6 @@ }; }; - sdhci@78000000 { - cd-gpios = <&gpio 69 0>; /* gpio PI5 */ - wp-gpios = <&gpio 155 0>; /* gpio PT3 */ - power-gpios = <&gpio 31 0>; /* gpio PD7 */ - }; - - sdhci@78000200 { - status = "disable"; - }; - - sdhci@78000400 { - status = "disable"; - }; - - sdhci@78000600 { - support-8bit; - }; - ahub { i2s@70080300 { status = "disable"; @@ -174,6 +156,24 @@ }; }; + sdhci@78000000 { + cd-gpios = <&gpio 69 0>; /* gpio PI5 */ + wp-gpios = <&gpio 155 0>; /* gpio PT3 */ + power-gpios = <&gpio 31 0>; /* gpio PD7 */ + }; + + sdhci@78000200 { + status = "disable"; + }; + + sdhci@78000400 { + status = "disable"; + }; + + sdhci@78000600 { + support-8bit; + }; + sound { compatible = "nvidia,tegra-audio-wm8903-cardhu", "nvidia,tegra-audio-wm8903"; diff --git a/arch/arm/boot/dts/tegra-harmony.dts b/arch/arm/boot/dts/tegra-harmony.dts index 759e289e7f87..f18385d36dde 100644 --- a/arch/arm/boot/dts/tegra-harmony.dts +++ b/arch/arm/boot/dts/tegra-harmony.dts @@ -234,8 +234,28 @@ }; }; - pmc { - nvidia,invert-interrupt; + i2s@70002a00 { + status = "disable"; + }; + + serial@70006000 { + status = "disable"; + }; + + serial@70006040 { + status = "disable"; + }; + + serial@70006200 { + status = "disable"; + }; + + serial@70006300 { + clock-frequency = <216000000>; + }; + + serial@70006400 { + status = "disable"; }; i2c@7000c000 { @@ -268,10 +288,35 @@ clock-frequency = <400000>; }; - i2s@70002a00 { + pmc { + nvidia,invert-interrupt; + }; + + usb@c5004000 { + nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ + }; + + sdhci@c8000000 { status = "disable"; }; + sdhci@c8000200 { + cd-gpios = <&gpio 69 0>; /* gpio PI5 */ + wp-gpios = <&gpio 57 0>; /* gpio PH1 */ + power-gpios = <&gpio 155 0>; /* gpio PT3 */ + }; + + sdhci@c8000400 { + status = "disable"; + }; + + sdhci@c8000600 { + cd-gpios = <&gpio 58 0>; /* gpio PH2 */ + wp-gpios = <&gpio 59 0>; /* gpio PH3 */ + power-gpios = <&gpio 70 0>; /* gpio PI6 */ + support-8bit; + }; + sound { compatible = "nvidia,tegra-audio-wm8903-harmony", "nvidia,tegra-audio-wm8903"; @@ -295,49 +340,4 @@ nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */ nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */ }; - - serial@70006000 { - status = "disable"; - }; - - serial@70006040 { - status = "disable"; - }; - - serial@70006200 { - status = "disable"; - }; - - serial@70006300 { - clock-frequency = <216000000>; - }; - - serial@70006400 { - status = "disable"; - }; - - sdhci@c8000000 { - status = "disable"; - }; - - sdhci@c8000200 { - cd-gpios = <&gpio 69 0>; /* gpio PI5 */ - wp-gpios = <&gpio 57 0>; /* gpio PH1 */ - power-gpios = <&gpio 155 0>; /* gpio PT3 */ - }; - - sdhci@c8000400 { - status = "disable"; - }; - - sdhci@c8000600 { - cd-gpios = <&gpio 58 0>; /* gpio PH2 */ - wp-gpios = <&gpio 59 0>; /* gpio PH3 */ - power-gpios = <&gpio 70 0>; /* gpio PI6 */ - support-8bit; - }; - - usb@c5004000 { - nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ - }; }; diff --git a/arch/arm/boot/dts/tegra-paz00.dts b/arch/arm/boot/dts/tegra-paz00.dts index d469322afbb8..b500212cc01c 100644 --- a/arch/arm/boot/dts/tegra-paz00.dts +++ b/arch/arm/boot/dts/tegra-paz00.dts @@ -226,6 +226,30 @@ }; }; + i2s@70002a00 { + status = "disable"; + }; + + serial@70006000 { + clock-frequency = <216000000>; + }; + + serial@70006040 { + status = "disable"; + }; + + serial@70006200 { + clock-frequency = <216000000>; + }; + + serial@70006300 { + status = "disable"; + }; + + serial@70006400 { + status = "disable"; + }; + i2c@7000c000 { clock-frequency = <400000>; @@ -265,48 +289,8 @@ }; }; - i2s@70002a00 { - status = "disable"; - }; - - sound { - compatible = "nvidia,tegra-audio-alc5632-paz00", - "nvidia,tegra-audio-alc5632"; - - nvidia,model = "Compal PAZ00"; - - nvidia,audio-routing = - "Int Spk", "SPKOUT", - "Int Spk", "SPKOUTN", - "Headset Mic", "MICBIAS1", - "MIC1", "Headset Mic", - "Headset Stereophone", "HPR", - "Headset Stereophone", "HPL", - "DMICDAT", "Digital Mic"; - - nvidia,audio-codec = <&alc5632>; - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ - }; - - serial@70006000 { - clock-frequency = <216000000>; - }; - - serial@70006040 { - status = "disable"; - }; - - serial@70006200 { - clock-frequency = <216000000>; - }; - - serial@70006300 { - status = "disable"; - }; - - serial@70006400 { - status = "disable"; + usb@c5004000 { + nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */ }; sdhci@c8000000 { @@ -348,7 +332,23 @@ }; }; - usb@c5004000 { - nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */ + sound { + compatible = "nvidia,tegra-audio-alc5632-paz00", + "nvidia,tegra-audio-alc5632"; + + nvidia,model = "Compal PAZ00"; + + nvidia,audio-routing = + "Int Spk", "SPKOUT", + "Int Spk", "SPKOUTN", + "Headset Mic", "MICBIAS1", + "MIC1", "Headset Mic", + "Headset Stereophone", "HPR", + "Headset Stereophone", "HPL", + "DMICDAT", "Digital Mic"; + + nvidia,audio-codec = <&alc5632>; + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ }; }; diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra-seaboard.dts index c935a2871846..88f3b8e0c8c0 100644 --- a/arch/arm/boot/dts/tegra-seaboard.dts +++ b/arch/arm/boot/dts/tegra-seaboard.dts @@ -257,6 +257,30 @@ }; }; + i2s@70002a00 { + status = "disable"; + }; + + serial@70006000 { + status = "disable"; + }; + + serial@70006040 { + status = "disable"; + }; + + serial@70006200 { + status = "disable"; + }; + + serial@70006300 { + clock-frequency = <216000000>; + }; + + serial@70006400 { + status = "disable"; + }; + i2c@7000c000 { clock-frequency = <400000>; @@ -321,95 +345,6 @@ }; }; - i2s@70002a00 { - status = "disable"; - }; - - sound { - compatible = "nvidia,tegra-audio-wm8903-seaboard", - "nvidia,tegra-audio-wm8903"; - nvidia,model = "NVIDIA Tegra Seaboard"; - - nvidia,audio-routing = - "Headphone Jack", "HPOUTR", - "Headphone Jack", "HPOUTL", - "Int Spk", "ROP", - "Int Spk", "RON", - "Int Spk", "LOP", - "Int Spk", "LON", - "Mic Jack", "MICBIAS", - "IN1R", "Mic Jack"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&wm8903>; - - nvidia,spkr-en-gpios = <&wm8903 2 0>; - nvidia,hp-det-gpios = <&gpio 185 0>; /* gpio PX1 */ - }; - - serial@70006000 { - status = "disable"; - }; - - serial@70006040 { - status = "disable"; - }; - - serial@70006200 { - status = "disable"; - }; - - serial@70006300 { - clock-frequency = <216000000>; - }; - - serial@70006400 { - status = "disable"; - }; - - sdhci@c8000000 { - status = "disable"; - }; - - sdhci@c8000200 { - status = "disable"; - }; - - sdhci@c8000400 { - cd-gpios = <&gpio 69 0>; /* gpio PI5 */ - wp-gpios = <&gpio 57 0>; /* gpio PH1 */ - power-gpios = <&gpio 70 0>; /* gpio PI6 */ - }; - - sdhci@c8000600 { - support-8bit; - }; - - usb@c5000000 { - nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */ - dr_mode = "otg"; - }; - - gpio-keys { - compatible = "gpio-keys"; - - power { - label = "Power"; - gpios = <&gpio 170 1>; /* gpio PV2, active low */ - linux,code = <116>; /* KEY_POWER */ - gpio-key,wakeup; - }; - - lid { - label = "Lid"; - gpios = <&gpio 23 0>; /* gpio PC7 */ - linux,input-type = <5>; /* EV_SW */ - linux,code = <0>; /* SW_LID */ - debounce-interval = <1>; - gpio-key,wakeup; - }; - }; - emc { emc-table@190000 { reg = <190000>; @@ -448,7 +383,72 @@ }; }; + usb@c5000000 { + nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */ + dr_mode = "otg"; + }; + usb@c5004000 { nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ }; + + sdhci@c8000000 { + status = "disable"; + }; + + sdhci@c8000200 { + status = "disable"; + }; + + sdhci@c8000400 { + cd-gpios = <&gpio 69 0>; /* gpio PI5 */ + wp-gpios = <&gpio 57 0>; /* gpio PH1 */ + power-gpios = <&gpio 70 0>; /* gpio PI6 */ + }; + + sdhci@c8000600 { + support-8bit; + }; + + gpio-keys { + compatible = "gpio-keys"; + + power { + label = "Power"; + gpios = <&gpio 170 1>; /* gpio PV2, active low */ + linux,code = <116>; /* KEY_POWER */ + gpio-key,wakeup; + }; + + lid { + label = "Lid"; + gpios = <&gpio 23 0>; /* gpio PC7 */ + linux,input-type = <5>; /* EV_SW */ + linux,code = <0>; /* SW_LID */ + debounce-interval = <1>; + gpio-key,wakeup; + }; + }; + + sound { + compatible = "nvidia,tegra-audio-wm8903-seaboard", + "nvidia,tegra-audio-wm8903"; + nvidia,model = "NVIDIA Tegra Seaboard"; + + nvidia,audio-routing = + "Headphone Jack", "HPOUTR", + "Headphone Jack", "HPOUTL", + "Int Spk", "ROP", + "Int Spk", "RON", + "Int Spk", "LOP", + "Int Spk", "LON", + "Mic Jack", "MICBIAS", + "IN1R", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&wm8903>; + + nvidia,spkr-en-gpios = <&wm8903 2 0>; + nvidia,hp-det-gpios = <&gpio 185 0>; /* gpio PX1 */ + }; }; diff --git a/arch/arm/boot/dts/tegra-trimslice.dts b/arch/arm/boot/dts/tegra-trimslice.dts index eebcf504d12d..1dea6cc68dde 100644 --- a/arch/arm/boot/dts/tegra-trimslice.dts +++ b/arch/arm/boot/dts/tegra-trimslice.dts @@ -240,6 +240,30 @@ }; }; + i2s@70002a00 { + status = "disable"; + }; + + serial@70006000 { + clock-frequency = <216000000>; + }; + + serial@70006040 { + status = "disable"; + }; + + serial@70006200 { + status = "disable"; + }; + + serial@70006300 { + status = "disable"; + }; + + serial@70006400 { + status = "disable"; + }; + i2c@7000c000 { clock-frequency = <400000>; }; @@ -266,34 +290,8 @@ status = "disable"; }; - i2s@70002a00 { - status = "disable"; - }; - - sound { - compatible = "nvidia,tegra-audio-trimslice"; - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&codec>; - }; - - serial@70006000 { - clock-frequency = <216000000>; - }; - - serial@70006040 { - status = "disable"; - }; - - serial@70006200 { - status = "disable"; - }; - - serial@70006300 { - status = "disable"; - }; - - serial@70006400 { - status = "disable"; + usb@c5004000 { + nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */ }; sdhci@c8000200 { @@ -309,7 +307,9 @@ wp-gpios = <&gpio 122 0>; /* gpio PP2 */ }; - usb@c5004000 { - nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */ + sound { + compatible = "nvidia,tegra-audio-trimslice"; + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&codec>; }; }; diff --git a/arch/arm/boot/dts/tegra-ventana.dts b/arch/arm/boot/dts/tegra-ventana.dts index e64318d595d5..6de4c106024f 100644 --- a/arch/arm/boot/dts/tegra-ventana.dts +++ b/arch/arm/boot/dts/tegra-ventana.dts @@ -240,6 +240,30 @@ }; }; + i2s@70002a00 { + status = "disable"; + }; + + serial@70006000 { + status = "disable"; + }; + + serial@70006040 { + status = "disable"; + }; + + serial@70006200 { + status = "disable"; + }; + + serial@70006300 { + clock-frequency = <216000000>; + }; + + serial@70006400 { + status = "disable"; + }; + i2c@7000c000 { clock-frequency = <400000>; @@ -278,10 +302,28 @@ clock-frequency = <400000>; }; - i2s@70002a00 { + usb@c5004000 { + nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ + }; + + sdhci@c8000000 { status = "disable"; }; + sdhci@c8000200 { + status = "disable"; + }; + + sdhci@c8000400 { + cd-gpios = <&gpio 69 0>; /* gpio PI5 */ + wp-gpios = <&gpio 57 0>; /* gpio PH1 */ + power-gpios = <&gpio 70 0>; /* gpio PI6 */ + }; + + sdhci@c8000600 { + support-8bit; + }; + sound { compatible = "nvidia,tegra-audio-wm8903-ventana", "nvidia,tegra-audio-wm8903"; @@ -305,46 +347,4 @@ nvidia,int-mic-en-gpios = <&gpio 184 0>; /* gpio PX0 */ nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */ }; - - serial@70006000 { - status = "disable"; - }; - - serial@70006040 { - status = "disable"; - }; - - serial@70006200 { - status = "disable"; - }; - - serial@70006300 { - clock-frequency = <216000000>; - }; - - serial@70006400 { - status = "disable"; - }; - - sdhci@c8000000 { - status = "disable"; - }; - - sdhci@c8000200 { - status = "disable"; - }; - - sdhci@c8000400 { - cd-gpios = <&gpio 69 0>; /* gpio PI5 */ - wp-gpios = <&gpio 57 0>; /* gpio PH1 */ - power-gpios = <&gpio 70 0>; /* gpio PI6 */ - }; - - sdhci@c8000600 { - support-8bit; - }; - - usb@c5004000 { - nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ - }; }; diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 5f9110af43b1..0e371f92d1d2 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -4,11 +4,6 @@ compatible = "nvidia,tegra20"; interrupt-parent = <&intc>; - pmc { - compatible = "nvidia,tegra20-pmc"; - reg = <0x7000e400 0x400>; - }; - intc: interrupt-controller { compatible = "arm,cortex-a9-gic"; interrupt-controller; @@ -17,12 +12,6 @@ 0x50040100 0x0100>; }; - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = <0 56 0x04 - 0 57 0x04>; - }; - apbdma: dma { compatible = "nvidia,tegra20-apbdma"; reg = <0x6000a000 0x1200>; @@ -44,55 +33,9 @@ 0 119 0x04>; }; - i2c@7000c000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "nvidia,tegra20-i2c"; - reg = <0x7000c000 0x100>; - interrupts = <0 38 0x04>; - }; - - i2c@7000c400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "nvidia,tegra20-i2c"; - reg = <0x7000c400 0x100>; - interrupts = <0 84 0x04>; - }; - - i2c@7000c500 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "nvidia,tegra20-i2c"; - reg = <0x7000c500 0x100>; - interrupts = <0 92 0x04>; - }; - - i2c@7000d000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "nvidia,tegra20-i2c-dvc"; - reg = <0x7000d000 0x200>; - interrupts = <0 53 0x04>; - }; - - tegra_i2s1: i2s@70002800 { - compatible = "nvidia,tegra20-i2s"; - reg = <0x70002800 0x200>; - interrupts = <0 13 0x04>; - nvidia,dma-request-selector = <&apbdma 2>; - }; - - tegra_i2s2: i2s@70002a00 { - compatible = "nvidia,tegra20-i2s"; - reg = <0x70002a00 0x200>; - interrupts = <0 3 0x04>; - nvidia,dma-request-selector = <&apbdma 1>; - }; - - das { - compatible = "nvidia,tegra20-das"; - reg = <0x70000c00 0x80>; + ahb { + compatible = "nvidia,tegra20-ahb"; + reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */ }; gpio: gpio { @@ -119,6 +62,25 @@ 0x70000868 0xa8>; /* Pad control registers */ }; + das { + compatible = "nvidia,tegra20-das"; + reg = <0x70000c00 0x80>; + }; + + tegra_i2s1: i2s@70002800 { + compatible = "nvidia,tegra20-i2s"; + reg = <0x70002800 0x200>; + interrupts = <0 13 0x04>; + nvidia,dma-request-selector = <&apbdma 2>; + }; + + tegra_i2s2: i2s@70002a00 { + compatible = "nvidia,tegra20-i2s"; + reg = <0x70002a00 0x200>; + interrupts = <0 3 0x04>; + nvidia,dma-request-selector = <&apbdma 1>; + }; + serial@70006000 { compatible = "nvidia,tegra20-uart"; reg = <0x70006000 0x40>; @@ -154,6 +116,56 @@ interrupts = <0 91 0x04>; }; + i2c@7000c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-i2c"; + reg = <0x7000c000 0x100>; + interrupts = <0 38 0x04>; + }; + + i2c@7000c400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-i2c"; + reg = <0x7000c400 0x100>; + interrupts = <0 84 0x04>; + }; + + i2c@7000c500 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-i2c"; + reg = <0x7000c500 0x100>; + interrupts = <0 92 0x04>; + }; + + i2c@7000d000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-i2c-dvc"; + reg = <0x7000d000 0x200>; + interrupts = <0 53 0x04>; + }; + + pmc { + compatible = "nvidia,tegra20-pmc"; + reg = <0x7000e400 0x400>; + }; + + mc { + compatible = "nvidia,tegra20-mc"; + reg = <0x7000f000 0x024 + 0x7000f03c 0x3c4>; + interrupts = <0 77 0x04>; + }; + + gart { + compatible = "nvidia,tegra20-gart"; + reg = <0x7000f024 0x00000018 /* controller registers */ + 0x58000000 0x02000000>; /* GART aperture */ + }; + emc { #address-cells = <1>; #size-cells = <0>; @@ -161,6 +173,28 @@ reg = <0x7000f400 0x200>; }; + usb@c5000000 { + compatible = "nvidia,tegra20-ehci", "usb-ehci"; + reg = <0xc5000000 0x4000>; + interrupts = <0 20 0x04>; + phy_type = "utmi"; + nvidia,has-legacy-mode; + }; + + usb@c5004000 { + compatible = "nvidia,tegra20-ehci", "usb-ehci"; + reg = <0xc5004000 0x4000>; + interrupts = <0 21 0x04>; + phy_type = "ulpi"; + }; + + usb@c5008000 { + compatible = "nvidia,tegra20-ehci", "usb-ehci"; + reg = <0xc5008000 0x4000>; + interrupts = <0 97 0x04>; + phy_type = "utmi"; + }; + sdhci@c8000000 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000000 0x200>; @@ -185,43 +219,9 @@ interrupts = <0 31 0x04>; }; - usb@c5000000 { - compatible = "nvidia,tegra20-ehci", "usb-ehci"; - reg = <0xc5000000 0x4000>; - interrupts = <0 20 0x04>; - phy_type = "utmi"; - nvidia,has-legacy-mode; - }; - - usb@c5004000 { - compatible = "nvidia,tegra20-ehci", "usb-ehci"; - reg = <0xc5004000 0x4000>; - interrupts = <0 21 0x04>; - phy_type = "ulpi"; - }; - - usb@c5008000 { - compatible = "nvidia,tegra20-ehci", "usb-ehci"; - reg = <0xc5008000 0x4000>; - interrupts = <0 97 0x04>; - phy_type = "utmi"; - }; - - ahb { - compatible = "nvidia,tegra20-ahb"; - reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */ - }; - - mc { - compatible = "nvidia,tegra20-mc"; - reg = <0x7000f000 0x024 - 0x7000f03c 0x3c4>; - interrupts = <0 77 0x04>; - }; - - gart { - compatible = "nvidia,tegra20-gart"; - reg = <0x7000f024 0x00000018 /* controller registers */ - 0x58000000 0x02000000>; /* GART aperture */ + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = <0 56 0x04 + 0 57 0x04>; }; }; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index ea829f5bae01..9fb47adc935d 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -4,11 +4,6 @@ compatible = "nvidia,tegra30"; interrupt-parent = <&intc>; - pmc { - compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc"; - reg = <0x7000e400 0x400>; - }; - intc: interrupt-controller { compatible = "arm,cortex-a9-gic"; interrupt-controller; @@ -17,14 +12,6 @@ 0x50040100 0x0100>; }; - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = <0 144 0x04 - 0 145 0x04 - 0 146 0x04 - 0 147 0x04>; - }; - apbdma: dma { compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; reg = <0x6000a000 0x1400>; @@ -62,6 +49,69 @@ 0 143 0x04>; }; + ahb: ahb { + compatible = "nvidia,tegra30-ahb"; + reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */ + }; + + gpio: gpio { + compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio"; + reg = <0x6000d000 0x1000>; + interrupts = <0 32 0x04 + 0 33 0x04 + 0 34 0x04 + 0 35 0x04 + 0 55 0x04 + 0 87 0x04 + 0 89 0x04 + 0 125 0x04>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + }; + + pinmux: pinmux { + compatible = "nvidia,tegra30-pinmux"; + reg = <0x70000868 0xd0 /* Pad control registers */ + 0x70003000 0x3e0>; /* Mux registers */ + }; + + serial@70006000 { + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; + reg = <0x70006000 0x40>; + reg-shift = <2>; + interrupts = <0 36 0x04>; + }; + + serial@70006040 { + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; + reg = <0x70006040 0x40>; + reg-shift = <2>; + interrupts = <0 37 0x04>; + }; + + serial@70006200 { + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; + reg = <0x70006200 0x100>; + reg-shift = <2>; + interrupts = <0 46 0x04>; + }; + + serial@70006300 { + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; + reg = <0x70006300 0x100>; + reg-shift = <2>; + interrupts = <0 90 0x04>; + }; + + serial@70006400 { + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; + reg = <0x70006400 0x100>; + reg-shift = <2>; + interrupts = <0 91 0x04>; + }; + i2c@7000c000 { #address-cells = <1>; #size-cells = <0>; @@ -102,86 +152,28 @@ interrupts = <0 53 0x04>; }; - gpio: gpio { - compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio"; - reg = <0x6000d000 0x1000>; - interrupts = <0 32 0x04 - 0 33 0x04 - 0 34 0x04 - 0 35 0x04 - 0 55 0x04 - 0 87 0x04 - 0 89 0x04 - 0 125 0x04>; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; + pmc { + compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc"; + reg = <0x7000e400 0x400>; }; - serial@70006000 { - compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; - reg = <0x70006000 0x40>; - reg-shift = <2>; - interrupts = <0 36 0x04>; + mc { + compatible = "nvidia,tegra30-mc"; + reg = <0x7000f000 0x010 + 0x7000f03c 0x1b4 + 0x7000f200 0x028 + 0x7000f284 0x17c>; + interrupts = <0 77 0x04>; }; - serial@70006040 { - compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; - reg = <0x70006040 0x40>; - reg-shift = <2>; - interrupts = <0 37 0x04>; - }; - - serial@70006200 { - compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; - reg = <0x70006200 0x100>; - reg-shift = <2>; - interrupts = <0 46 0x04>; - }; - - serial@70006300 { - compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; - reg = <0x70006300 0x100>; - reg-shift = <2>; - interrupts = <0 90 0x04>; - }; - - serial@70006400 { - compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; - reg = <0x70006400 0x100>; - reg-shift = <2>; - interrupts = <0 91 0x04>; - }; - - sdhci@78000000 { - compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; - reg = <0x78000000 0x200>; - interrupts = <0 14 0x04>; - }; - - sdhci@78000200 { - compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; - reg = <0x78000200 0x200>; - interrupts = <0 15 0x04>; - }; - - sdhci@78000400 { - compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; - reg = <0x78000400 0x200>; - interrupts = <0 19 0x04>; - }; - - sdhci@78000600 { - compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; - reg = <0x78000600 0x200>; - interrupts = <0 31 0x04>; - }; - - pinmux: pinmux { - compatible = "nvidia,tegra30-pinmux"; - reg = <0x70000868 0xd0 /* Pad control registers */ - 0x70003000 0x3e0>; /* Mux registers */ + smmu { + compatible = "nvidia,tegra30-smmu"; + reg = <0x7000f010 0x02c + 0x7000f1f0 0x010 + 0x7000f228 0x05c>; + nvidia,#asids = <4>; /* # of ASIDs */ + dma-window = <0 0x40000000>; /* IOVA start & length */ + nvidia,ahb = <&ahb>; }; ahub { @@ -226,27 +218,35 @@ }; }; - ahb: ahb { - compatible = "nvidia,tegra30-ahb"; - reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */ + sdhci@78000000 { + compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; + reg = <0x78000000 0x200>; + interrupts = <0 14 0x04>; }; - mc { - compatible = "nvidia,tegra30-mc"; - reg = <0x7000f000 0x010 - 0x7000f03c 0x1b4 - 0x7000f200 0x028 - 0x7000f284 0x17c>; - interrupts = <0 77 0x04>; + sdhci@78000200 { + compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; + reg = <0x78000200 0x200>; + interrupts = <0 15 0x04>; }; - smmu { - compatible = "nvidia,tegra30-smmu"; - reg = <0x7000f010 0x02c - 0x7000f1f0 0x010 - 0x7000f228 0x05c>; - nvidia,#asids = <4>; /* # of ASIDs */ - dma-window = <0 0x40000000>; /* IOVA start & length */ - nvidia,ahb = <&ahb>; + sdhci@78000400 { + compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; + reg = <0x78000400 0x200>; + interrupts = <0 19 0x04>; + }; + + sdhci@78000600 { + compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; + reg = <0x78000600 0x200>; + interrupts = <0 31 0x04>; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = <0 144 0x04 + 0 145 0x04 + 0 146 0x04 + 0 147 0x04>; }; }; From 2eaab06ea6cc2d686fd1a6de62b1094bedc4cfca Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 11 May 2012 17:12:52 -0600 Subject: [PATCH 28/29] ARM: dt: tegra: consistent basic property ordering Put properties in order compatible, reg, interrupts, then anything else the node has. Signed-off-by: Stephen Warren Acked-by: Olof Johansson --- arch/arm/boot/dts/tegra-paz00.dts | 4 ++-- arch/arm/boot/dts/tegra20.dtsi | 24 ++++++++++++------------ arch/arm/boot/dts/tegra30.dtsi | 24 ++++++++++++------------ 3 files changed, 26 insertions(+), 26 deletions(-) diff --git a/arch/arm/boot/dts/tegra-paz00.dts b/arch/arm/boot/dts/tegra-paz00.dts index b500212cc01c..6539e8934802 100644 --- a/arch/arm/boot/dts/tegra-paz00.dts +++ b/arch/arm/boot/dts/tegra-paz00.dts @@ -270,11 +270,11 @@ }; nvec { - #address-cells = <1>; - #size-cells = <0>; compatible = "nvidia,nvec"; reg = <0x7000c500 0x100>; interrupts = <0 92 0x04>; + #address-cells = <1>; + #size-cells = <0>; clock-frequency = <80000>; request-gpios = <&gpio 170 0>; /* gpio PV2 */ slave-addr = <138>; diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 0e371f92d1d2..df34defe1bbd 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -6,10 +6,10 @@ intc: interrupt-controller { compatible = "arm,cortex-a9-gic"; - interrupt-controller; - #interrupt-cells = <3>; reg = <0x50041000 0x1000 0x50040100 0x0100>; + interrupt-controller; + #interrupt-cells = <3>; }; apbdma: dma { @@ -117,35 +117,35 @@ }; i2c@7000c000 { - #address-cells = <1>; - #size-cells = <0>; compatible = "nvidia,tegra20-i2c"; reg = <0x7000c000 0x100>; interrupts = <0 38 0x04>; + #address-cells = <1>; + #size-cells = <0>; }; i2c@7000c400 { - #address-cells = <1>; - #size-cells = <0>; compatible = "nvidia,tegra20-i2c"; reg = <0x7000c400 0x100>; interrupts = <0 84 0x04>; + #address-cells = <1>; + #size-cells = <0>; }; i2c@7000c500 { - #address-cells = <1>; - #size-cells = <0>; compatible = "nvidia,tegra20-i2c"; reg = <0x7000c500 0x100>; interrupts = <0 92 0x04>; + #address-cells = <1>; + #size-cells = <0>; }; i2c@7000d000 { - #address-cells = <1>; - #size-cells = <0>; compatible = "nvidia,tegra20-i2c-dvc"; reg = <0x7000d000 0x200>; interrupts = <0 53 0x04>; + #address-cells = <1>; + #size-cells = <0>; }; pmc { @@ -167,10 +167,10 @@ }; emc { - #address-cells = <1>; - #size-cells = <0>; compatible = "nvidia,tegra20-emc"; reg = <0x7000f400 0x200>; + #address-cells = <1>; + #size-cells = <0>; }; usb@c5000000 { diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 9fb47adc935d..5a1c85fbf0f0 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -6,10 +6,10 @@ intc: interrupt-controller { compatible = "arm,cortex-a9-gic"; - interrupt-controller; - #interrupt-cells = <3>; reg = <0x50041000 0x1000 0x50040100 0x0100>; + interrupt-controller; + #interrupt-cells = <3>; }; apbdma: dma { @@ -113,43 +113,43 @@ }; i2c@7000c000 { - #address-cells = <1>; - #size-cells = <0>; compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; reg = <0x7000c000 0x100>; interrupts = <0 38 0x04>; + #address-cells = <1>; + #size-cells = <0>; }; i2c@7000c400 { - #address-cells = <1>; - #size-cells = <0>; compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; reg = <0x7000c400 0x100>; interrupts = <0 84 0x04>; + #address-cells = <1>; + #size-cells = <0>; }; i2c@7000c500 { - #address-cells = <1>; - #size-cells = <0>; compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; reg = <0x7000c500 0x100>; interrupts = <0 92 0x04>; + #address-cells = <1>; + #size-cells = <0>; }; i2c@7000c700 { - #address-cells = <1>; - #size-cells = <0>; compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; reg = <0x7000c700 0x100>; interrupts = <0 120 0x04>; + #address-cells = <1>; + #size-cells = <0>; }; i2c@7000d000 { - #address-cells = <1>; - #size-cells = <0>; compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; reg = <0x7000d000 0x100>; interrupts = <0 53 0x04>; + #address-cells = <1>; + #size-cells = <0>; }; pmc { From 2a5fdc9adde8476751b63a795e3d66ae2ee3979d Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 11 May 2012 17:32:56 -0600 Subject: [PATCH 29/29] ARM: dt: tegra: invert status=disable vs status=okay In tegra*.dtsi, set status="disable" for all HW modules that the board design may choose not to use. Update all boards to specifically enable any of those modules that are useful by setting status="okay". This makes board files say which features they do use, rather than which they don't, which feels more logical. It also makes the .dts files slightly smaller, at least for existing content. Signed-off-by: Stephen Warren Acked-by: Olof Johansson --- arch/arm/boot/dts/tegra-cardhu.dts | 48 ++++++--------------------- arch/arm/boot/dts/tegra-harmony.dts | 40 +++++++++------------- arch/arm/boot/dts/tegra-paz00.dts | 44 ++++++++++-------------- arch/arm/boot/dts/tegra-seaboard.dts | 37 ++++++++------------- arch/arm/boot/dts/tegra-trimslice.dts | 37 ++++++++------------- arch/arm/boot/dts/tegra-ventana.dts | 40 +++++++++------------- arch/arm/boot/dts/tegra20.dtsi | 18 ++++++++++ arch/arm/boot/dts/tegra30.dtsi | 19 +++++++++++ 8 files changed, 123 insertions(+), 160 deletions(-) diff --git a/arch/arm/boot/dts/tegra-cardhu.dts b/arch/arm/boot/dts/tegra-cardhu.dts index 3b5cd7b07553..e14bb450c328 100644 --- a/arch/arm/boot/dts/tegra-cardhu.dts +++ b/arch/arm/boot/dts/tegra-cardhu.dts @@ -64,34 +64,22 @@ }; serial@70006000 { + status = "okay"; clock-frequency = <408000000>; }; - serial@70006040 { - status = "disable"; - }; - - serial@70006200 { - status = "disable"; - }; - - serial@70006300 { - status = "disable"; - }; - - serial@70006400 { - status = "disable"; - }; - i2c@7000c000 { + status = "okay"; clock-frequency = <100000>; }; i2c@7000c400 { + status = "okay"; clock-frequency = <100000>; }; i2c@7000c500 { + status = "okay"; clock-frequency = <100000>; /* ALS and Proximity sensor */ @@ -104,10 +92,12 @@ }; i2c@7000c700 { + status = "okay"; clock-frequency = <100000>; }; i2c@7000d000 { + status = "okay"; clock-frequency = <100000>; wm8903: wm8903@1a { @@ -139,38 +129,20 @@ }; ahub { - i2s@70080300 { - status = "disable"; - }; - - i2s@70080500 { - status = "disable"; - }; - - i2s@70080600 { - status = "disable"; - }; - - i2s@70080700 { - status = "disable"; + i2s@70080400 { + status = "okay"; }; }; sdhci@78000000 { + status = "okay"; cd-gpios = <&gpio 69 0>; /* gpio PI5 */ wp-gpios = <&gpio 155 0>; /* gpio PT3 */ power-gpios = <&gpio 31 0>; /* gpio PD7 */ }; - sdhci@78000200 { - status = "disable"; - }; - - sdhci@78000400 { - status = "disable"; - }; - sdhci@78000600 { + status = "okay"; support-8bit; }; diff --git a/arch/arm/boot/dts/tegra-harmony.dts b/arch/arm/boot/dts/tegra-harmony.dts index f18385d36dde..6bcdad34d2e7 100644 --- a/arch/arm/boot/dts/tegra-harmony.dts +++ b/arch/arm/boot/dts/tegra-harmony.dts @@ -234,31 +234,17 @@ }; }; - i2s@70002a00 { - status = "disable"; - }; - - serial@70006000 { - status = "disable"; - }; - - serial@70006040 { - status = "disable"; - }; - - serial@70006200 { - status = "disable"; + i2s@70002800 { + status = "okay"; }; serial@70006300 { + status = "okay"; clock-frequency = <216000000>; }; - serial@70006400 { - status = "disable"; - }; - i2c@7000c000 { + status = "okay"; clock-frequency = <400000>; wm8903: wm8903@1a { @@ -277,14 +263,17 @@ }; i2c@7000c400 { + status = "okay"; clock-frequency = <400000>; }; i2c@7000c500 { + status = "okay"; clock-frequency = <400000>; }; i2c@7000d000 { + status = "okay"; clock-frequency = <400000>; }; @@ -292,25 +281,28 @@ nvidia,invert-interrupt; }; + usb@c5000000 { + status = "okay"; + }; + usb@c5004000 { + status = "okay"; nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ }; - sdhci@c8000000 { - status = "disable"; + usb@c5008000 { + status = "okay"; }; sdhci@c8000200 { + status = "okay"; cd-gpios = <&gpio 69 0>; /* gpio PI5 */ wp-gpios = <&gpio 57 0>; /* gpio PH1 */ power-gpios = <&gpio 155 0>; /* gpio PT3 */ }; - sdhci@c8000400 { - status = "disable"; - }; - sdhci@c8000600 { + status = "okay"; cd-gpios = <&gpio 58 0>; /* gpio PH2 */ wp-gpios = <&gpio 59 0>; /* gpio PH3 */ power-gpios = <&gpio 70 0>; /* gpio PI6 */ diff --git a/arch/arm/boot/dts/tegra-paz00.dts b/arch/arm/boot/dts/tegra-paz00.dts index 6539e8934802..cb366f0c6ffe 100644 --- a/arch/arm/boot/dts/tegra-paz00.dts +++ b/arch/arm/boot/dts/tegra-paz00.dts @@ -226,31 +226,22 @@ }; }; - i2s@70002a00 { - status = "disable"; + i2s@70002800 { + status = "okay"; }; serial@70006000 { + status = "okay"; clock-frequency = <216000000>; }; - serial@70006040 { - status = "disable"; - }; - serial@70006200 { + status = "okay"; clock-frequency = <216000000>; }; - serial@70006300 { - status = "disable"; - }; - - serial@70006400 { - status = "disable"; - }; - i2c@7000c000 { + status = "okay"; clock-frequency = <400000>; alc5632: alc5632@1e { @@ -262,13 +253,10 @@ }; i2c@7000c400 { + status = "okay"; clock-frequency = <400000>; }; - i2c@7000c500 { - status = "disable"; - }; - nvec { compatible = "nvidia,nvec"; reg = <0x7000c500 0x100>; @@ -281,6 +269,7 @@ }; i2c@7000d000 { + status = "okay"; clock-frequency = <400000>; adt7461@4c { @@ -289,25 +278,28 @@ }; }; + usb@c5000000 { + status = "okay"; + }; + usb@c5004000 { + status = "okay"; nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */ }; + usb@c5008000 { + status = "okay"; + }; + sdhci@c8000000 { + status = "okay"; cd-gpios = <&gpio 173 0>; /* gpio PV5 */ wp-gpios = <&gpio 57 0>; /* gpio PH1 */ power-gpios = <&gpio 169 0>; /* gpio PV1 */ }; - sdhci@c8000200 { - status = "disable"; - }; - - sdhci@c8000400 { - status = "disable"; - }; - sdhci@c8000600 { + status = "okay"; support-8bit; }; diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra-seaboard.dts index 88f3b8e0c8c0..21b586e41e97 100644 --- a/arch/arm/boot/dts/tegra-seaboard.dts +++ b/arch/arm/boot/dts/tegra-seaboard.dts @@ -257,31 +257,17 @@ }; }; - i2s@70002a00 { - status = "disable"; - }; - - serial@70006000 { - status = "disable"; - }; - - serial@70006040 { - status = "disable"; - }; - - serial@70006200 { - status = "disable"; + i2s@70002800 { + status = "okay"; }; serial@70006300 { + status = "okay"; clock-frequency = <216000000>; }; - serial@70006400 { - status = "disable"; - }; - i2c@7000c000 { + status = "okay"; clock-frequency = <400000>; wm8903: wm8903@1a { @@ -315,6 +301,7 @@ }; i2c@7000c400 { + status = "okay"; clock-frequency = <100000>; smart-battery@b { @@ -326,10 +313,12 @@ }; i2c@7000c500 { + status = "okay"; clock-frequency = <400000>; }; i2c@7000d000 { + status = "okay"; clock-frequency = <400000>; temperature-sensor@4c { @@ -384,29 +373,29 @@ }; usb@c5000000 { + status = "okay"; nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */ dr_mode = "otg"; }; usb@c5004000 { + status = "okay"; nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ }; - sdhci@c8000000 { - status = "disable"; - }; - - sdhci@c8000200 { - status = "disable"; + usb@c5008000 { + status = "okay"; }; sdhci@c8000400 { + status = "okay"; cd-gpios = <&gpio 69 0>; /* gpio PI5 */ wp-gpios = <&gpio 57 0>; /* gpio PH1 */ power-gpios = <&gpio 70 0>; /* gpio PI6 */ }; sdhci@c8000600 { + status = "okay"; support-8bit; }; diff --git a/arch/arm/boot/dts/tegra-trimslice.dts b/arch/arm/boot/dts/tegra-trimslice.dts index 1dea6cc68dde..6fc52afa9431 100644 --- a/arch/arm/boot/dts/tegra-trimslice.dts +++ b/arch/arm/boot/dts/tegra-trimslice.dts @@ -240,39 +240,27 @@ }; }; - i2s@70002a00 { - status = "disable"; + i2s@70002800 { + status = "okay"; }; serial@70006000 { + status = "okay"; clock-frequency = <216000000>; }; - serial@70006040 { - status = "disable"; - }; - - serial@70006200 { - status = "disable"; - }; - - serial@70006300 { - status = "disable"; - }; - - serial@70006400 { - status = "disable"; - }; - i2c@7000c000 { + status = "okay"; clock-frequency = <400000>; }; i2c@7000c400 { + status = "okay"; clock-frequency = <400000>; }; i2c@7000c500 { + status = "okay"; clock-frequency = <400000>; codec: codec@1a { @@ -286,23 +274,24 @@ }; }; - i2c@7000d000 { - status = "disable"; + usb@c5000000 { + status = "okay"; }; usb@c5004000 { nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */ }; - sdhci@c8000200 { - status = "disable"; + usb@c5008000 { + status = "okay"; }; - sdhci@c8000400 { - status = "disable"; + sdhci@c8000000 { + status = "okay"; }; sdhci@c8000600 { + status = "okay"; cd-gpios = <&gpio 121 0>; /* gpio PP1 */ wp-gpios = <&gpio 122 0>; /* gpio PP2 */ }; diff --git a/arch/arm/boot/dts/tegra-ventana.dts b/arch/arm/boot/dts/tegra-ventana.dts index 6de4c106024f..15d8fdbe21f2 100644 --- a/arch/arm/boot/dts/tegra-ventana.dts +++ b/arch/arm/boot/dts/tegra-ventana.dts @@ -240,31 +240,17 @@ }; }; - i2s@70002a00 { - status = "disable"; - }; - - serial@70006000 { - status = "disable"; - }; - - serial@70006040 { - status = "disable"; - }; - - serial@70006200 { - status = "disable"; + i2s@70002800 { + status = "okay"; }; serial@70006300 { + status = "okay"; clock-frequency = <216000000>; }; - serial@70006400 { - status = "disable"; - }; - i2c@7000c000 { + status = "okay"; clock-frequency = <400000>; wm8903: wm8903@1a { @@ -291,36 +277,42 @@ }; i2c@7000c400 { + status = "okay"; clock-frequency = <400000>; }; i2c@7000c500 { + status = "okay"; clock-frequency = <400000>; }; i2c@7000d000 { + status = "okay"; clock-frequency = <400000>; }; + usb@c5000000 { + status = "okay"; + }; + usb@c5004000 { + status = "okay"; nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ }; - sdhci@c8000000 { - status = "disable"; - }; - - sdhci@c8000200 { - status = "disable"; + usb@c5008000 { + status = "okay"; }; sdhci@c8000400 { + status = "okay"; cd-gpios = <&gpio 69 0>; /* gpio PI5 */ wp-gpios = <&gpio 57 0>; /* gpio PH1 */ power-gpios = <&gpio 70 0>; /* gpio PI6 */ }; sdhci@c8000600 { + status = "okay"; support-8bit; }; diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index df34defe1bbd..c417d67e9027 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -72,6 +72,7 @@ reg = <0x70002800 0x200>; interrupts = <0 13 0x04>; nvidia,dma-request-selector = <&apbdma 2>; + status = "disable"; }; tegra_i2s2: i2s@70002a00 { @@ -79,6 +80,7 @@ reg = <0x70002a00 0x200>; interrupts = <0 3 0x04>; nvidia,dma-request-selector = <&apbdma 1>; + status = "disable"; }; serial@70006000 { @@ -86,6 +88,7 @@ reg = <0x70006000 0x40>; reg-shift = <2>; interrupts = <0 36 0x04>; + status = "disable"; }; serial@70006040 { @@ -93,6 +96,7 @@ reg = <0x70006040 0x40>; reg-shift = <2>; interrupts = <0 37 0x04>; + status = "disable"; }; serial@70006200 { @@ -100,6 +104,7 @@ reg = <0x70006200 0x100>; reg-shift = <2>; interrupts = <0 46 0x04>; + status = "disable"; }; serial@70006300 { @@ -107,6 +112,7 @@ reg = <0x70006300 0x100>; reg-shift = <2>; interrupts = <0 90 0x04>; + status = "disable"; }; serial@70006400 { @@ -114,6 +120,7 @@ reg = <0x70006400 0x100>; reg-shift = <2>; interrupts = <0 91 0x04>; + status = "disable"; }; i2c@7000c000 { @@ -122,6 +129,7 @@ interrupts = <0 38 0x04>; #address-cells = <1>; #size-cells = <0>; + status = "disable"; }; i2c@7000c400 { @@ -130,6 +138,7 @@ interrupts = <0 84 0x04>; #address-cells = <1>; #size-cells = <0>; + status = "disable"; }; i2c@7000c500 { @@ -138,6 +147,7 @@ interrupts = <0 92 0x04>; #address-cells = <1>; #size-cells = <0>; + status = "disable"; }; i2c@7000d000 { @@ -146,6 +156,7 @@ interrupts = <0 53 0x04>; #address-cells = <1>; #size-cells = <0>; + status = "disable"; }; pmc { @@ -179,6 +190,7 @@ interrupts = <0 20 0x04>; phy_type = "utmi"; nvidia,has-legacy-mode; + status = "disable"; }; usb@c5004000 { @@ -186,6 +198,7 @@ reg = <0xc5004000 0x4000>; interrupts = <0 21 0x04>; phy_type = "ulpi"; + status = "disable"; }; usb@c5008000 { @@ -193,30 +206,35 @@ reg = <0xc5008000 0x4000>; interrupts = <0 97 0x04>; phy_type = "utmi"; + status = "disable"; }; sdhci@c8000000 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000000 0x200>; interrupts = <0 14 0x04>; + status = "disable"; }; sdhci@c8000200 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000200 0x200>; interrupts = <0 15 0x04>; + status = "disable"; }; sdhci@c8000400 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000400 0x200>; interrupts = <0 19 0x04>; + status = "disable"; }; sdhci@c8000600 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000600 0x200>; interrupts = <0 31 0x04>; + status = "disable"; }; pmu { diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 5a1c85fbf0f0..2dcc09e784b5 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -82,6 +82,7 @@ reg = <0x70006000 0x40>; reg-shift = <2>; interrupts = <0 36 0x04>; + status = "disable"; }; serial@70006040 { @@ -89,6 +90,7 @@ reg = <0x70006040 0x40>; reg-shift = <2>; interrupts = <0 37 0x04>; + status = "disable"; }; serial@70006200 { @@ -96,6 +98,7 @@ reg = <0x70006200 0x100>; reg-shift = <2>; interrupts = <0 46 0x04>; + status = "disable"; }; serial@70006300 { @@ -103,6 +106,7 @@ reg = <0x70006300 0x100>; reg-shift = <2>; interrupts = <0 90 0x04>; + status = "disable"; }; serial@70006400 { @@ -110,6 +114,7 @@ reg = <0x70006400 0x100>; reg-shift = <2>; interrupts = <0 91 0x04>; + status = "disable"; }; i2c@7000c000 { @@ -118,6 +123,7 @@ interrupts = <0 38 0x04>; #address-cells = <1>; #size-cells = <0>; + status = "disable"; }; i2c@7000c400 { @@ -126,6 +132,7 @@ interrupts = <0 84 0x04>; #address-cells = <1>; #size-cells = <0>; + status = "disable"; }; i2c@7000c500 { @@ -134,6 +141,7 @@ interrupts = <0 92 0x04>; #address-cells = <1>; #size-cells = <0>; + status = "disable"; }; i2c@7000c700 { @@ -142,6 +150,7 @@ interrupts = <0 120 0x04>; #address-cells = <1>; #size-cells = <0>; + status = "disable"; }; i2c@7000d000 { @@ -150,6 +159,7 @@ interrupts = <0 53 0x04>; #address-cells = <1>; #size-cells = <0>; + status = "disable"; }; pmc { @@ -191,30 +201,35 @@ compatible = "nvidia,tegra30-i2s"; reg = <0x70080300 0x100>; nvidia,ahub-cif-ids = <4 4>; + status = "disable"; }; tegra_i2s1: i2s@70080400 { compatible = "nvidia,tegra30-i2s"; reg = <0x70080400 0x100>; nvidia,ahub-cif-ids = <5 5>; + status = "disable"; }; tegra_i2s2: i2s@70080500 { compatible = "nvidia,tegra30-i2s"; reg = <0x70080500 0x100>; nvidia,ahub-cif-ids = <6 6>; + status = "disable"; }; tegra_i2s3: i2s@70080600 { compatible = "nvidia,tegra30-i2s"; reg = <0x70080600 0x100>; nvidia,ahub-cif-ids = <7 7>; + status = "disable"; }; tegra_i2s4: i2s@70080700 { compatible = "nvidia,tegra30-i2s"; reg = <0x70080700 0x100>; nvidia,ahub-cif-ids = <8 8>; + status = "disable"; }; }; @@ -222,24 +237,28 @@ compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; reg = <0x78000000 0x200>; interrupts = <0 14 0x04>; + status = "disable"; }; sdhci@78000200 { compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; reg = <0x78000200 0x200>; interrupts = <0 15 0x04>; + status = "disable"; }; sdhci@78000400 { compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; reg = <0x78000400 0x200>; interrupts = <0 19 0x04>; + status = "disable"; }; sdhci@78000600 { compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; reg = <0x78000600 0x200>; interrupts = <0 31 0x04>; + status = "disable"; }; pmu {