iwlwifi: pcie: set LTR on more devices
To avoid completion timeouts during device boot, set up the
LTR timeouts on more devices - similar to what we had before
for AX210.
This also corrects the AX210 workaround to be done only on
discrete (non-integrated) devices, otherwise the registers
have no effect.
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
Fixes: edb625208d
("iwlwifi: pcie: set LTR to avoid completion timeout")
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
Link: https://lore.kernel.org/r/iwlwifi.20210115130252.fb819e19530b.I0396f82922db66426f52fbb70d32a29c8fd66951@changeid
This commit is contained in:
Родитель
0f8d5656b3
Коммит
ed0022da8b
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@ -301,6 +301,12 @@
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#define RADIO_RSP_ADDR_POS (6)
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#define RADIO_RSP_RD_CMD (3)
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/* LTR control (Qu only) */
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#define HPM_MAC_LTR_CSR 0xa0348c
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#define HPM_MAC_LRT_ENABLE_ALL 0xf
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/* also uses CSR_LTR_* for values */
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#define HPM_UMAC_LTR 0xa03480
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/* FW monitor */
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#define MON_BUFF_SAMPLE_CTL (0xa03c00)
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#define MON_BUFF_BASE_ADDR (0xa03c1c)
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@ -75,6 +75,15 @@ int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans,
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const struct fw_img *fw)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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u32 ltr_val = CSR_LTR_LONG_VAL_AD_NO_SNOOP_REQ |
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u32_encode_bits(CSR_LTR_LONG_VAL_AD_SCALE_USEC,
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CSR_LTR_LONG_VAL_AD_NO_SNOOP_SCALE) |
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u32_encode_bits(250,
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CSR_LTR_LONG_VAL_AD_NO_SNOOP_VAL) |
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CSR_LTR_LONG_VAL_AD_SNOOP_REQ |
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u32_encode_bits(CSR_LTR_LONG_VAL_AD_SCALE_USEC,
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CSR_LTR_LONG_VAL_AD_SNOOP_SCALE) |
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u32_encode_bits(250, CSR_LTR_LONG_VAL_AD_SNOOP_VAL);
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struct iwl_context_info_gen3 *ctxt_info_gen3;
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struct iwl_prph_scratch *prph_scratch;
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struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl;
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@ -206,23 +215,19 @@ int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans,
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iwl_set_bit(trans, CSR_CTXT_INFO_BOOT_CTRL,
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CSR_AUTO_FUNC_BOOT_ENA);
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if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210) {
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/*
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* The firmware initializes this again later (to a smaller
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* value), but for the boot process initialize the LTR to
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* ~250 usec.
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*/
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u32 val = CSR_LTR_LONG_VAL_AD_NO_SNOOP_REQ |
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u32_encode_bits(CSR_LTR_LONG_VAL_AD_SCALE_USEC,
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CSR_LTR_LONG_VAL_AD_NO_SNOOP_SCALE) |
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u32_encode_bits(250,
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CSR_LTR_LONG_VAL_AD_NO_SNOOP_VAL) |
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CSR_LTR_LONG_VAL_AD_SNOOP_REQ |
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u32_encode_bits(CSR_LTR_LONG_VAL_AD_SCALE_USEC,
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CSR_LTR_LONG_VAL_AD_SNOOP_SCALE) |
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u32_encode_bits(250, CSR_LTR_LONG_VAL_AD_SNOOP_VAL);
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iwl_write32(trans, CSR_LTR_LONG_VAL_AD, val);
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/*
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* To workaround hardware latency issues during the boot process,
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* initialize the LTR to ~250 usec (see ltr_val above).
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* The firmware initializes this again later (to a smaller value).
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*/
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if ((trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210 ||
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trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000) &&
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!trans->trans_cfg->integrated) {
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iwl_write32(trans, CSR_LTR_LONG_VAL_AD, ltr_val);
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} else if (trans->trans_cfg->integrated &&
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trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000) {
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iwl_write_prph(trans, HPM_MAC_LTR_CSR, HPM_MAC_LRT_ENABLE_ALL);
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iwl_write_prph(trans, HPM_UMAC_LTR, ltr_val);
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}
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if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
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