clk: remove sirf prima2/atlas drivers
The CSR SiRF prima2/atlas platforms are getting removed, so this driver is no longer needed. Cc: Barry Song <baohua@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20210120131026.1721788-4-arnd@kernel.org Acked-by: Barry Song <baohua@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Arnd Bergmann
Stephen Boyd
Родитель
bcbe6005eb
Коммит
ed0f3e23d1
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@ -1,55 +0,0 @@
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* Clock and reset bindings for CSR atlas7
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Required properties:
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- compatible: Should be "sirf,atlas7-car"
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- reg: Address and length of the register set
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- #clock-cells: Should be <1>
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- #reset-cells: Should be <1>
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell.
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The ID list atlas7_clks defined in drivers/clk/sirf/clk-atlas7.c
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The reset consumer should specify the desired reset by having the reset
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ID in its "reset" phandle cell.
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The ID list atlas7_reset_unit defined in drivers/clk/sirf/clk-atlas7.c
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Examples: Clock and reset controller node:
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car: clock-controller@18620000 {
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compatible = "sirf,atlas7-car";
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reg = <0x18620000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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Examples: Consumers using clock or reset:
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timer@10dc0000 {
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compatible = "sirf,macro-tick";
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reg = <0x10dc0000 0x1000>;
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clocks = <&car 54>;
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interrupts = <0 0 0>,
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<0 1 0>,
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<0 2 0>,
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<0 49 0>,
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<0 50 0>,
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<0 51 0>;
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};
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uart1: uart@18020000 {
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cell-index = <1>;
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compatible = "sirf,macro-uart";
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reg = <0x18020000 0x1000>;
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clocks = <&clks 95>;
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interrupts = <0 18 0>;
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fifosize = <32>;
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};
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vpp@13110000 {
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compatible = "sirf,prima2-vpp";
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reg = <0x13110000 0x10000>;
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interrupts = <0 31 0>;
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clocks = <&car 85>;
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resets = <&car 29>;
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};
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@ -1,73 +0,0 @@
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* Clock bindings for CSR SiRFprimaII
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Required properties:
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- compatible: Should be "sirf,prima2-clkc"
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- reg: Address and length of the register set
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- interrupts: Should contain clock controller interrupt
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- #clock-cells: Should be <1>
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell. The following is a full list of prima2
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clocks and IDs.
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Clock ID
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---------------------------
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rtc 0
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osc 1
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pll1 2
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pll2 3
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pll3 4
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mem 5
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sys 6
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security 7
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dsp 8
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gps 9
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mf 10
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io 11
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cpu 12
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uart0 13
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uart1 14
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uart2 15
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tsc 16
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i2c0 17
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i2c1 18
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spi0 19
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spi1 20
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pwmc 21
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efuse 22
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pulse 23
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dmac0 24
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dmac1 25
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nand 26
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audio 27
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usp0 28
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usp1 29
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usp2 30
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vip 31
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gfx 32
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mm 33
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lcd 34
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vpp 35
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mmc01 36
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mmc23 37
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mmc45 38
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usbpll 39
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usb0 40
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usb1 41
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Examples:
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clks: clock-controller@88000000 {
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compatible = "sirf,prima2-clkc";
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reg = <0x88000000 0x1000>;
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interrupts = <3>;
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#clock-cells = <1>;
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};
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i2c0: i2c@b00e0000 {
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cell-index = <0>;
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compatible = "sirf,prima2-i2c";
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reg = <0xb00e0000 0x10000>;
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interrupts = <24>;
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clocks = <&clks 17>;
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};
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@ -103,7 +103,6 @@ obj-y += renesas/
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obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
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obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/
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obj-$(CONFIG_CLK_SIFIVE) += sifive/
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obj-$(CONFIG_ARCH_SIRF) += sirf/
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obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/
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obj-$(CONFIG_ARCH_AGILEX) += socfpga/
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obj-$(CONFIG_ARCH_STRATIX10) += socfpga/
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@ -1,6 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0-only
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#
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# Makefile for sirf specific clk
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#
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obj-$(CONFIG_ARCH_SIRF) += clk-prima2.o clk-atlas6.o clk-atlas7.o
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@ -1,32 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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#define SIRFSOC_CLKC_CLK_EN0 0x0000
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#define SIRFSOC_CLKC_CLK_EN1 0x0004
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#define SIRFSOC_CLKC_REF_CFG 0x0020
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#define SIRFSOC_CLKC_CPU_CFG 0x0024
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#define SIRFSOC_CLKC_MEM_CFG 0x0028
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#define SIRFSOC_CLKC_MEMDIV_CFG 0x002C
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#define SIRFSOC_CLKC_SYS_CFG 0x0030
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#define SIRFSOC_CLKC_IO_CFG 0x0034
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#define SIRFSOC_CLKC_DSP_CFG 0x0038
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#define SIRFSOC_CLKC_GFX_CFG 0x003c
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#define SIRFSOC_CLKC_MM_CFG 0x0040
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#define SIRFSOC_CLKC_GFX2D_CFG 0x0040
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#define SIRFSOC_CLKC_LCD_CFG 0x0044
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#define SIRFSOC_CLKC_MMC01_CFG 0x0048
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#define SIRFSOC_CLKC_MMC23_CFG 0x004C
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#define SIRFSOC_CLKC_MMC45_CFG 0x0050
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#define SIRFSOC_CLKC_NAND_CFG 0x0054
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#define SIRFSOC_CLKC_NANDDIV_CFG 0x0058
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#define SIRFSOC_CLKC_PLL1_CFG0 0x0080
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#define SIRFSOC_CLKC_PLL2_CFG0 0x0084
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#define SIRFSOC_CLKC_PLL3_CFG0 0x0088
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#define SIRFSOC_CLKC_PLL1_CFG1 0x008c
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#define SIRFSOC_CLKC_PLL2_CFG1 0x0090
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#define SIRFSOC_CLKC_PLL3_CFG1 0x0094
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#define SIRFSOC_CLKC_PLL1_CFG2 0x0098
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#define SIRFSOC_CLKC_PLL2_CFG2 0x009c
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#define SIRFSOC_CLKC_PLL3_CFG2 0x00A0
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#define SIRFSOC_USBPHY_PLL_CTRL 0x0008
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#define SIRFSOC_USBPHY_PLL_POWERDOWN BIT(1)
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#define SIRFSOC_USBPHY_PLL_BYPASS BIT(2)
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#define SIRFSOC_USBPHY_PLL_LOCK BIT(3)
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@ -1,150 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Clock tree for CSR SiRFatlasVI
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*
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* Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
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* company.
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*/
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#include <linux/module.h>
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#include <linux/bitops.h>
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#include <linux/io.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#include <linux/of_address.h>
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#include <linux/syscore_ops.h>
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#include "atlas6.h"
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#include "clk-common.c"
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static struct clk_dmn clk_mmc01 = {
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.regofs = SIRFSOC_CLKC_MMC01_CFG,
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.enable_bit = 59,
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.hw = {
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.init = &clk_mmc01_init,
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},
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};
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static struct clk_dmn clk_mmc23 = {
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.regofs = SIRFSOC_CLKC_MMC23_CFG,
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.enable_bit = 60,
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.hw = {
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.init = &clk_mmc23_init,
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},
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};
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static struct clk_dmn clk_mmc45 = {
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.regofs = SIRFSOC_CLKC_MMC45_CFG,
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.enable_bit = 61,
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.hw = {
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.init = &clk_mmc45_init,
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},
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};
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static const struct clk_init_data clk_nand_init = {
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.name = "nand",
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.ops = &dmn_ops,
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.parent_names = dmn_clk_parents,
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.num_parents = ARRAY_SIZE(dmn_clk_parents),
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};
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static struct clk_dmn clk_nand = {
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.regofs = SIRFSOC_CLKC_NAND_CFG,
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.enable_bit = 34,
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.hw = {
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.init = &clk_nand_init,
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},
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};
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enum atlas6_clk_index {
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/* 0 1 2 3 4 5 6 7 8 9 */
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rtc, osc, pll1, pll2, pll3, mem, sys, security, dsp, gps,
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mf, io, cpu, uart0, uart1, uart2, tsc, i2c0, i2c1, spi0,
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spi1, pwmc, efuse, pulse, dmac0, dmac1, nand, audio, usp0, usp1,
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usp2, vip, gfx, gfx2d, lcd, vpp, mmc01, mmc23, mmc45, usbpll,
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usb0, usb1, cphif, maxclk,
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};
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static __initdata struct clk_hw *atlas6_clk_hw_array[maxclk] = {
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NULL, /* dummy */
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NULL,
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&clk_pll1.hw,
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&clk_pll2.hw,
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&clk_pll3.hw,
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&clk_mem.hw,
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&clk_sys.hw,
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&clk_security.hw,
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&clk_dsp.hw,
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&clk_gps.hw,
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&clk_mf.hw,
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&clk_io.hw,
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&clk_cpu.hw,
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&clk_uart0.hw,
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&clk_uart1.hw,
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&clk_uart2.hw,
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&clk_tsc.hw,
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&clk_i2c0.hw,
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&clk_i2c1.hw,
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&clk_spi0.hw,
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&clk_spi1.hw,
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&clk_pwmc.hw,
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&clk_efuse.hw,
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&clk_pulse.hw,
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&clk_dmac0.hw,
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&clk_dmac1.hw,
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&clk_nand.hw,
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&clk_audio.hw,
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&clk_usp0.hw,
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&clk_usp1.hw,
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&clk_usp2.hw,
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&clk_vip.hw,
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&clk_gfx.hw,
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&clk_gfx2d.hw,
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&clk_lcd.hw,
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&clk_vpp.hw,
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&clk_mmc01.hw,
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&clk_mmc23.hw,
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&clk_mmc45.hw,
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&usb_pll_clk_hw,
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&clk_usb0.hw,
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&clk_usb1.hw,
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&clk_cphif.hw,
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};
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static struct clk *atlas6_clks[maxclk];
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static void __init atlas6_clk_init(struct device_node *np)
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{
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struct device_node *rscnp;
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int i;
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rscnp = of_find_compatible_node(NULL, NULL, "sirf,prima2-rsc");
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sirfsoc_rsc_vbase = of_iomap(rscnp, 0);
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if (!sirfsoc_rsc_vbase)
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panic("unable to map rsc registers\n");
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of_node_put(rscnp);
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sirfsoc_clk_vbase = of_iomap(np, 0);
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if (!sirfsoc_clk_vbase)
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panic("unable to map clkc registers\n");
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/* These are always available (RTC and 26MHz OSC)*/
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atlas6_clks[rtc] = clk_register_fixed_rate(NULL, "rtc", NULL, 0, 32768);
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atlas6_clks[osc] = clk_register_fixed_rate(NULL, "osc", NULL, 0,
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26000000);
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for (i = pll1; i < maxclk; i++) {
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atlas6_clks[i] = clk_register(NULL, atlas6_clk_hw_array[i]);
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BUG_ON(IS_ERR(atlas6_clks[i]));
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}
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clk_register_clkdev(atlas6_clks[cpu], NULL, "cpu");
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clk_register_clkdev(atlas6_clks[io], NULL, "io");
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clk_register_clkdev(atlas6_clks[mem], NULL, "mem");
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clk_register_clkdev(atlas6_clks[mem], NULL, "osc");
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clk_data.clks = atlas6_clks;
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clk_data.clk_num = maxclk;
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of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
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}
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CLK_OF_DECLARE(atlas6_clk, "sirf,atlas6-clkc", atlas6_clk_init);
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@ -1,149 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Clock tree for CSR SiRFprimaII
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*
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* Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
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* company.
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*/
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#include <linux/module.h>
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#include <linux/bitops.h>
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#include <linux/io.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#include <linux/of_address.h>
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#include <linux/syscore_ops.h>
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#include "prima2.h"
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#include "clk-common.c"
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static struct clk_dmn clk_mmc01 = {
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.regofs = SIRFSOC_CLKC_MMC_CFG,
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.enable_bit = 59,
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.hw = {
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.init = &clk_mmc01_init,
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},
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};
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static struct clk_dmn clk_mmc23 = {
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.regofs = SIRFSOC_CLKC_MMC_CFG,
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.enable_bit = 60,
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.hw = {
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.init = &clk_mmc23_init,
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},
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};
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static struct clk_dmn clk_mmc45 = {
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.regofs = SIRFSOC_CLKC_MMC_CFG,
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.enable_bit = 61,
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.hw = {
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.init = &clk_mmc45_init,
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},
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};
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static const struct clk_init_data clk_nand_init = {
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.name = "nand",
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.ops = &ios_ops,
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.parent_names = std_clk_io_parents,
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.num_parents = ARRAY_SIZE(std_clk_io_parents),
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};
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static struct clk_std clk_nand = {
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.enable_bit = 34,
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.hw = {
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.init = &clk_nand_init,
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},
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};
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enum prima2_clk_index {
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/* 0 1 2 3 4 5 6 7 8 9 */
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rtc, osc, pll1, pll2, pll3, mem, sys, security, dsp, gps,
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mf, io, cpu, uart0, uart1, uart2, tsc, i2c0, i2c1, spi0,
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spi1, pwmc, efuse, pulse, dmac0, dmac1, nand, audio, usp0, usp1,
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usp2, vip, gfx, mm, lcd, vpp, mmc01, mmc23, mmc45, usbpll,
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usb0, usb1, cphif, maxclk,
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};
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static __initdata struct clk_hw *prima2_clk_hw_array[maxclk] = {
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NULL, /* dummy */
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NULL,
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&clk_pll1.hw,
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&clk_pll2.hw,
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&clk_pll3.hw,
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&clk_mem.hw,
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&clk_sys.hw,
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&clk_security.hw,
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&clk_dsp.hw,
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&clk_gps.hw,
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&clk_mf.hw,
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&clk_io.hw,
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&clk_cpu.hw,
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&clk_uart0.hw,
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&clk_uart1.hw,
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&clk_uart2.hw,
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&clk_tsc.hw,
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&clk_i2c0.hw,
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&clk_i2c1.hw,
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&clk_spi0.hw,
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&clk_spi1.hw,
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&clk_pwmc.hw,
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&clk_efuse.hw,
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&clk_pulse.hw,
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&clk_dmac0.hw,
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&clk_dmac1.hw,
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&clk_nand.hw,
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&clk_audio.hw,
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&clk_usp0.hw,
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&clk_usp1.hw,
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&clk_usp2.hw,
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&clk_vip.hw,
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&clk_gfx.hw,
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&clk_mm.hw,
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&clk_lcd.hw,
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&clk_vpp.hw,
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&clk_mmc01.hw,
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&clk_mmc23.hw,
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&clk_mmc45.hw,
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&usb_pll_clk_hw,
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&clk_usb0.hw,
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&clk_usb1.hw,
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&clk_cphif.hw,
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};
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static struct clk *prima2_clks[maxclk];
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|
||||
static void __init prima2_clk_init(struct device_node *np)
|
||||
{
|
||||
struct device_node *rscnp;
|
||||
int i;
|
||||
|
||||
rscnp = of_find_compatible_node(NULL, NULL, "sirf,prima2-rsc");
|
||||
sirfsoc_rsc_vbase = of_iomap(rscnp, 0);
|
||||
if (!sirfsoc_rsc_vbase)
|
||||
panic("unable to map rsc registers\n");
|
||||
of_node_put(rscnp);
|
||||
|
||||
sirfsoc_clk_vbase = of_iomap(np, 0);
|
||||
if (!sirfsoc_clk_vbase)
|
||||
panic("unable to map clkc registers\n");
|
||||
|
||||
/* These are always available (RTC and 26MHz OSC)*/
|
||||
prima2_clks[rtc] = clk_register_fixed_rate(NULL, "rtc", NULL, 0, 32768);
|
||||
prima2_clks[osc] = clk_register_fixed_rate(NULL, "osc", NULL, 0,
|
||||
26000000);
|
||||
|
||||
for (i = pll1; i < maxclk; i++) {
|
||||
prima2_clks[i] = clk_register(NULL, prima2_clk_hw_array[i]);
|
||||
BUG_ON(IS_ERR(prima2_clks[i]));
|
||||
}
|
||||
clk_register_clkdev(prima2_clks[cpu], NULL, "cpu");
|
||||
clk_register_clkdev(prima2_clks[io], NULL, "io");
|
||||
clk_register_clkdev(prima2_clks[mem], NULL, "mem");
|
||||
clk_register_clkdev(prima2_clks[mem], NULL, "osc");
|
||||
|
||||
clk_data.clks = prima2_clks;
|
||||
clk_data.clk_num = maxclk;
|
||||
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
}
|
||||
CLK_OF_DECLARE(prima2_clk, "sirf,prima2-clkc", prima2_clk_init);
|
||||
|
|
@ -1,26 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#define SIRFSOC_CLKC_CLK_EN0 0x0000
|
||||
#define SIRFSOC_CLKC_CLK_EN1 0x0004
|
||||
#define SIRFSOC_CLKC_REF_CFG 0x0014
|
||||
#define SIRFSOC_CLKC_CPU_CFG 0x0018
|
||||
#define SIRFSOC_CLKC_MEM_CFG 0x001c
|
||||
#define SIRFSOC_CLKC_SYS_CFG 0x0020
|
||||
#define SIRFSOC_CLKC_IO_CFG 0x0024
|
||||
#define SIRFSOC_CLKC_DSP_CFG 0x0028
|
||||
#define SIRFSOC_CLKC_GFX_CFG 0x002c
|
||||
#define SIRFSOC_CLKC_MM_CFG 0x0030
|
||||
#define SIRFSOC_CLKC_LCD_CFG 0x0034
|
||||
#define SIRFSOC_CLKC_MMC_CFG 0x0038
|
||||
#define SIRFSOC_CLKC_PLL1_CFG0 0x0040
|
||||
#define SIRFSOC_CLKC_PLL2_CFG0 0x0044
|
||||
#define SIRFSOC_CLKC_PLL3_CFG0 0x0048
|
||||
#define SIRFSOC_CLKC_PLL1_CFG1 0x004c
|
||||
#define SIRFSOC_CLKC_PLL2_CFG1 0x0050
|
||||
#define SIRFSOC_CLKC_PLL3_CFG1 0x0054
|
||||
#define SIRFSOC_CLKC_PLL1_CFG2 0x0058
|
||||
#define SIRFSOC_CLKC_PLL2_CFG2 0x005c
|
||||
#define SIRFSOC_CLKC_PLL3_CFG2 0x0060
|
||||
#define SIRFSOC_USBPHY_PLL_CTRL 0x0008
|
||||
#define SIRFSOC_USBPHY_PLL_POWERDOWN BIT(1)
|
||||
#define SIRFSOC_USBPHY_PLL_BYPASS BIT(2)
|
||||
#define SIRFSOC_USBPHY_PLL_LOCK BIT(3)
|
||||
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