clk: tango4: clkgen driver for Tango4 platforms
Provide support for Sigma Designs Tango4 clock generator. NOTE: This driver is incompatible with Tango3 clkgen. Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com> [sboyd@codeaurora.org: Add kernel.h include for panic/sprintf] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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* Sigma Designs Tango4 Clock Generator
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The Tango4 clock generator outputs cpu_clk and sys_clk (the latter is used
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for RAM and various peripheral devices). The clock binding described here
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is applicable to all Tango4 SoCs.
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Required Properties:
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- compatible: should be "sigma,tango4-clkgen".
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- reg: physical base address of the device and length of memory mapped region.
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- clocks: phandle of the input clock (crystal oscillator).
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- clock-output-names: should be "cpuclk" and "sysclk".
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- #clock-cells: should be set to 1.
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Example:
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clkgen: clkgen@10000 {
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compatible = "sigma,tango4-clkgen";
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reg = <0x10000 0x40>;
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clocks = <&xtal>;
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clock-output-names = "cpuclk", "sysclk";
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#clock-cells = <1>;
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};
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@ -42,6 +42,7 @@ obj-$(CONFIG_COMMON_CLK_SI514) += clk-si514.o
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obj-$(CONFIG_COMMON_CLK_SI570) += clk-si570.o
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obj-$(CONFIG_COMMON_CLK_CDCE925) += clk-cdce925.o
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obj-$(CONFIG_ARCH_STM32) += clk-stm32f4.o
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obj-$(CONFIG_ARCH_TANGOX) += clk-tango4.o
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obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o
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obj-$(CONFIG_ARCH_U300) += clk-u300.o
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obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
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#include <linux/kernel.h>
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#include <linux/clk-provider.h>
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#include <linux/of_address.h>
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#include <linux/init.h>
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#include <linux/io.h>
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static struct clk *out[2];
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static struct clk_onecell_data clk_data = { out, 2 };
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#define SYSCLK_CTRL 0x20
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#define CPUCLK_CTRL 0x24
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#define LEGACY_DIV 0x3c
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#define PLL_N(val) (((val) >> 0) & 0x7f)
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#define PLL_K(val) (((val) >> 13) & 0x7)
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#define PLL_M(val) (((val) >> 16) & 0x7)
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#define DIV_INDEX(val) (((val) >> 8) & 0xf)
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static void __init make_pll(int idx, const char *parent, void __iomem *base)
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{
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char name[8];
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u32 val, mul, div;
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sprintf(name, "pll%d", idx);
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val = readl_relaxed(base + idx*8);
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mul = PLL_N(val) + 1;
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div = (PLL_M(val) + 1) << PLL_K(val);
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clk_register_fixed_factor(NULL, name, parent, 0, mul, div);
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}
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static int __init get_div(void __iomem *base)
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{
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u8 sysclk_tab[16] = { 2, 4, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4 };
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int idx = DIV_INDEX(readl_relaxed(base + LEGACY_DIV));
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return sysclk_tab[idx];
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}
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static void __init tango4_clkgen_setup(struct device_node *np)
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{
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int div, ret;
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void __iomem *base = of_iomap(np, 0);
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const char *parent = of_clk_get_parent_name(np, 0);
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if (!base)
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panic("%s: invalid address\n", np->full_name);
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make_pll(0, parent, base);
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make_pll(1, parent, base);
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out[0] = clk_register_divider(NULL, "cpuclk", "pll0", 0,
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base + CPUCLK_CTRL, 8, 8, CLK_DIVIDER_ONE_BASED, NULL);
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div = readl_relaxed(base + SYSCLK_CTRL) & BIT(23) ? get_div(base) : 4;
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out[1] = clk_register_fixed_factor(NULL, "sysclk", "pll1", 0, 1, div);
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ret = of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
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if (IS_ERR(out[0]) || IS_ERR(out[1]) || ret < 0)
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panic("%s: clk registration failed\n", np->full_name);
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}
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CLK_OF_DECLARE(tango4_clkgen, "sigma,tango4-clkgen", tango4_clkgen_setup);
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