From 339d095ab23cf5de223c9633ee4d3ec1794282af Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 14 Jan 2015 17:37:15 -0800 Subject: [PATCH 1/9] ARM: OMAP2+: Fix error handling for omap2_clk_enable_init_clocks We need to check if we got the clock before trying to do anything with it. Otherwise we will get something like this: Unable to handle kernel paging request at virtual address fffffffe ... [] (clk_prepare) from [] (omap2_clk_enable_init_clocks+0x50/0x8) [] (omap2_clk_enable_init_clocks) from [] (dm816x_dt_clk_init+0) ... Let's add check for the clock and WARN if the init clock was not found. Cc: Brian Hutchinson Cc: Paul Walmsley Cc: Tero Kristo Reviewed-by: Felipe Balbi Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/clock.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 6ad5b4dbd33e..4ae4ccebced2 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -620,6 +620,9 @@ void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks) for (i = 0; i < num_clocks; i++) { init_clk = clk_get(NULL, clk_names[i]); + if (WARN(IS_ERR(init_clk), "could not find init clock %s\n", + clk_names[i])) + continue; clk_prepare_enable(init_clk); } } From e226ebe95e7afb79ff24c53f9984b8acad13cc81 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 14 Jan 2015 17:37:15 -0800 Subject: [PATCH 2/9] ARM: OMAP2+: Fix ti81xx devtype Otherwise we get error "Cannot detect omap type!" and many things can fail with following: Unhandled fault: imprecise external abort (0xc06) at 0xc6031fb0 This is because the omap_type is being used to set up th SoC specific functions for omaps. Cc: Brian Hutchinson Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/control.h | 4 ++++ arch/arm/mach-omap2/id.c | 2 ++ 2 files changed, 6 insertions(+) diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h index a3c013345c45..0fba6d1130a9 100644 --- a/arch/arm/mach-omap2/control.h +++ b/arch/arm/mach-omap2/control.h @@ -53,6 +53,7 @@ #define OMAP343X_CONTROL_GENERAL_WKUP 0xa60 /* TI81XX spefic control submodules */ +#define TI81XX_CONTROL_DEVBOOT 0x040 #define TI81XX_CONTROL_DEVCONF 0x600 /* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */ @@ -246,6 +247,9 @@ #define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250 #define OMAP3_PADCONF_SAD2D_IDLEACK 0x254 +/* TI81XX CONTROL_DEVBOOT register offsets */ +#define TI81XX_CONTROL_STATUS (TI81XX_CONTROL_DEVBOOT + 0x000) + /* TI81XX CONTROL_DEVCONF register offsets */ #define TI81XX_CONTROL_DEVICE_ID (TI81XX_CONTROL_DEVCONF + 0x000) diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index c25feba05818..2a2f4d56e4c8 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -56,6 +56,8 @@ int omap_type(void) if (cpu_is_omap24xx()) { val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS); + } else if (cpu_is_ti81xx()) { + val = omap_ctrl_readl(TI81XX_CONTROL_STATUS); } else if (soc_is_am33xx() || soc_is_am43xx()) { val = omap_ctrl_readl(AM33XX_CONTROL_STATUS); } else if (cpu_is_omap34xx()) { From c27964b5d2f3c36b0160d6d26f79f2d4730c440b Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 14 Jan 2015 17:37:16 -0800 Subject: [PATCH 3/9] ARM: OMAP2+: Fix ti81xx class type Otherwise it will return true for cpu_is_omap34xx() which we don't want for the clocks and hwmod. It's closer to am33xx for the clocks and hwmod than to the omap34xx. We also want to be able to detect 814x and 816x separately as at least the clocks are different with 814x using a apll and 816x using a fapll for the source clocks. Note that we can also remove omap3xxx_clk_init() call as it's wrong and ti81xx are booting in device tree only mode. Cc: Brian Hutchinson Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/common.h | 3 ++- arch/arm/mach-omap2/io.c | 25 +++++++++++++++++---- arch/arm/mach-omap2/powerdomains3xxx_data.c | 2 +- arch/arm/mach-omap2/soc.h | 4 ++-- 4 files changed, 26 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h index 377eea849e7b..900ebdd544a0 100644 --- a/arch/arm/mach-omap2/common.h +++ b/arch/arm/mach-omap2/common.h @@ -110,7 +110,8 @@ void omap3630_init_early(void); void omap3_init_early(void); /* Do not use this one */ void am33xx_init_early(void); void am35xx_init_early(void); -void ti81xx_init_early(void); +void ti814x_init_early(void); +void ti816x_init_early(void); void am33xx_init_early(void); void am43xx_init_early(void); void am43xx_init_late(void); diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index a1bd6affb508..b957776a41b6 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -492,9 +492,28 @@ void __init am35xx_init_early(void) omap_clk_soc_init = am35xx_dt_clk_init; } -void __init ti81xx_init_early(void) +void __init ti814x_init_early(void) { - omap2_set_globals_tap(OMAP343X_CLASS, + omap2_set_globals_tap(TI814X_CLASS, + OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE)); + omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE), + NULL); + omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE)); + omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL); + omap3xxx_check_revision(); + ti81xx_check_features(); + omap3xxx_voltagedomains_init(); + omap3xxx_powerdomains_init(); + omap3xxx_clockdomains_init(); + omap3xxx_hwmod_init(); + omap_hwmod_init_postsetup(); + if (of_have_populated_dt()) + omap_clk_soc_init = ti81xx_dt_clk_init; +} + +void __init ti816x_init_early(void) +{ + omap2_set_globals_tap(TI816X_CLASS, OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE)); omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE), NULL); @@ -509,8 +528,6 @@ void __init ti81xx_init_early(void) omap_hwmod_init_postsetup(); if (of_have_populated_dt()) omap_clk_soc_init = ti81xx_dt_clk_init; - else - omap_clk_soc_init = omap3xxx_clk_init; } void __init omap3_init_late(void) diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c index 328c1037cb60..70bc7066a4c2 100644 --- a/arch/arm/mach-omap2/powerdomains3xxx_data.c +++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c @@ -464,7 +464,7 @@ void __init omap3xxx_powerdomains_init(void) { unsigned int rev; - if (!cpu_is_omap34xx()) + if (!cpu_is_omap34xx() && !cpu_is_ti81xx()) return; pwrdm_register_platform_funcs(&omap3_pwrdm_operations); diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h index c1a3b4416311..f97654d11ea5 100644 --- a/arch/arm/mach-omap2/soc.h +++ b/arch/arm/mach-omap2/soc.h @@ -423,13 +423,13 @@ IS_OMAP_TYPE(3430, 0x3430) #define OMAP3630_REV_ES1_1 (OMAP363X_CLASS | (0x1 << 8)) #define OMAP3630_REV_ES1_2 (OMAP363X_CLASS | (0x2 << 8)) -#define TI816X_CLASS 0x81600034 +#define TI816X_CLASS 0x81600081 #define TI8168_REV_ES1_0 TI816X_CLASS #define TI8168_REV_ES1_1 (TI816X_CLASS | (0x1 << 8)) #define TI8168_REV_ES2_0 (TI816X_CLASS | (0x2 << 8)) #define TI8168_REV_ES2_1 (TI816X_CLASS | (0x3 << 8)) -#define TI814X_CLASS 0x81400034 +#define TI814X_CLASS 0x81400081 #define TI8148_REV_ES1_0 TI814X_CLASS #define TI8148_REV_ES2_0 (TI814X_CLASS | (0x1 << 8)) #define TI8148_REV_ES2_1 (TI814X_CLASS | (0x2 << 8)) From 132754e483d55309ddd714a2c44580379e4ac55a Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 14 Jan 2015 17:37:16 -0800 Subject: [PATCH 4/9] ARM: OMAP2+: Fix dm814 and dm816 for clocks and timer init Fix dm814 and dm816 clocks and timer init. Cc: Brian Hutchinson Cc: Paul Walmsley Cc: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/prm_common.c | 4 ++++ arch/arm/mach-omap2/timer.c | 2 ++ 2 files changed, 6 insertions(+) diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c index 779940cb6e56..b6587854bca5 100644 --- a/arch/arm/mach-omap2/prm_common.c +++ b/arch/arm/mach-omap2/prm_common.c @@ -571,6 +571,10 @@ static const struct of_device_id omap_prcm_dt_match_table[] = { { .compatible = "ti,am3-scrm" }, { .compatible = "ti,am4-prcm" }, { .compatible = "ti,am4-scrm" }, + { .compatible = "ti,dm814-prcm" }, + { .compatible = "ti,dm814-scrm" }, + { .compatible = "ti,dm816-prcm" }, + { .compatible = "ti,dm816-scrm" }, { .compatible = "ti,omap2-prcm" }, { .compatible = "ti,omap2-scrm" }, { .compatible = "ti,omap3-prm" }, diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 4f61148ec168..376b099ba84b 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -146,6 +146,8 @@ static const struct of_device_id omap_timer_match[] __initconst = { { .compatible = "ti,omap3430-timer", }, { .compatible = "ti,omap4430-timer", }, { .compatible = "ti,omap5430-timer", }, + { .compatible = "ti,dm814-timer", }, + { .compatible = "ti,dm816-timer", }, { .compatible = "ti,am335x-timer", }, { .compatible = "ti,am335x-timer-1ms", }, { } From bc7235c97f90c9def22ebda620d7eae2b49a7642 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 14 Jan 2015 17:37:16 -0800 Subject: [PATCH 5/9] ARM: OMAP2+: Fix reboot for 81xx We are missing proper hooks for 81xx for reboot to work. Cc: Brian Hutchinson Reviewed-by: Felipe Balbi Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/Makefile | 1 + arch/arm/mach-omap2/common.h | 8 +++++++ arch/arm/mach-omap2/ti81xx-restart.c | 34 ++++++++++++++++++++++++++++ 3 files changed, 43 insertions(+) create mode 100644 arch/arm/mach-omap2/ti81xx-restart.c diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 5d27dfdef66b..3a6463f88ea2 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -58,6 +58,7 @@ AFLAGS_sram34xx.o :=-Wa,-march=armv7-a # Restart code (OMAP4/5 currently in omap4-common.c) obj-$(CONFIG_SOC_OMAP2420) += omap2-restart.o obj-$(CONFIG_SOC_OMAP2430) += omap2-restart.o +obj-$(CONFIG_SOC_TI81XX) += ti81xx-restart.o obj-$(CONFIG_SOC_AM33XX) += am33xx-restart.o obj-$(CONFIG_SOC_AM43XX) += omap4-restart.o obj-$(CONFIG_ARCH_OMAP3) += omap3-restart.o diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h index 900ebdd544a0..65b4371b3361 100644 --- a/arch/arm/mach-omap2/common.h +++ b/arch/arm/mach-omap2/common.h @@ -164,6 +164,14 @@ static inline void omap3xxx_restart(enum reboot_mode mode, const char *cmd) } #endif +#ifdef CONFIG_SOC_TI81XX +void ti81xx_restart(enum reboot_mode mode, const char *cmd); +#else +static inline void ti81xx_restart(enum reboot_mode mode, const char *cmd) +{ +} +#endif + #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM43XX) void omap44xx_restart(enum reboot_mode mode, const char *cmd); diff --git a/arch/arm/mach-omap2/ti81xx-restart.c b/arch/arm/mach-omap2/ti81xx-restart.c new file mode 100644 index 000000000000..6c3ce7c46ddd --- /dev/null +++ b/arch/arm/mach-omap2/ti81xx-restart.c @@ -0,0 +1,34 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include + +#include "iomap.h" +#include "common.h" +#include "control.h" +#include "prm3xxx.h" + +#define TI81XX_PRM_DEVICE_RSTCTRL 0x00a0 +#define TI81XX_GLOBAL_RST_COLD BIT(1) + +/** + * ti81xx_restart - trigger a software restart of the SoC + * @mode: the "reboot mode", see arch/arm/kernel/{setup,process}.c + * @cmd: passed from the userspace program rebooting the system (if provided) + * + * Resets the SoC. For @cmd, see the 'reboot' syscall in + * kernel/sys.c. No return value. + * + * NOTE: Warm reset does not seem to work, may require resetting + * clocks to bypass mode. + */ +void ti81xx_restart(enum reboot_mode mode, const char *cmd) +{ + omap2_prm_set_mod_reg_bits(TI81XX_GLOBAL_RST_COLD, 0, + TI81XX_PRM_DEVICE_RSTCTRL); + while (1); +} From 13efcb188984f69e1f97b4d9e7d3663fb782946f Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 14 Jan 2015 17:37:16 -0800 Subject: [PATCH 6/9] ARM: OMAP2+: Disable omap3 PM init for ti81xx We cannot use the omap3 pm support on 81xx. Cc: Brian Hutchinson Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/io.c | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index b957776a41b6..e4a5630149e1 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -568,7 +568,6 @@ void __init am35xx_init_late(void) void __init ti81xx_init_late(void) { omap_common_late_init(); - omap3_pm_init(); omap2_clk_enable_autoidle_all(); } #endif From abf8cc1d5bc8babf9ac5410d50089f0004ec5593 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 26 Jan 2015 09:26:31 -0800 Subject: [PATCH 7/9] ARM: OMAP2+: Add board-generic.c entry for ti81xx This allows booting ti81xx boards when a .dts file is in place. Cc: Brian Hutchinson Reviewed-by: Felipe Balbi Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-generic.c | 36 +++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index 608079a1aba6..359fc5dcbba4 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -144,6 +144,42 @@ DT_MACHINE_START(AM3517_DT, "Generic AM3517 (Flattened Device Tree)") MACHINE_END #endif +#ifdef CONFIG_SOC_TI81XX +static const char *const ti814x_boards_compat[] __initconst = { + "ti,dm8148", + "ti,dm814", + NULL, +}; + +DT_MACHINE_START(TI81XX_DT, "Generic ti814x (Flattened Device Tree)") + .reserve = omap_reserve, + .map_io = ti81xx_map_io, + .init_early = ti814x_init_early, + .init_machine = omap_generic_init, + .init_late = ti81xx_init_late, + .init_time = omap3_gptimer_timer_init, + .dt_compat = ti814x_boards_compat, + .restart = ti81xx_restart, +MACHINE_END + +static const char *const ti816x_boards_compat[] __initconst = { + "ti,dm8168", + "ti,dm816", + NULL, +}; + +DT_MACHINE_START(TI816X_DT, "Generic ti816x (Flattened Device Tree)") + .reserve = omap_reserve, + .map_io = ti81xx_map_io, + .init_early = ti816x_init_early, + .init_machine = omap_generic_init, + .init_late = ti81xx_init_late, + .init_time = omap3_gptimer_timer_init, + .dt_compat = ti816x_boards_compat, + .restart = ti81xx_restart, +MACHINE_END +#endif + #ifdef CONFIG_SOC_AM33XX static const char *const am33xx_boards_compat[] __initconst = { "ti,am33xx", From a64459c42d744c765b4d38ae908c318635aaa697 Mon Sep 17 00:00:00 2001 From: Aida Mynzhasova Date: Mon, 26 Jan 2015 09:26:32 -0800 Subject: [PATCH 8/9] ARM: OMAP2+: Add clock domain support for dm816x This patch adds required definitions and structures for clockdomain initialization, so omap3xxx_clockdomains_init() was substituted by new ti81xx_clockdomains_init() while early initialization of TI81XX platform. Note that we now need to have 81xx in a separate CONFIG_SOC_TI81XX block instead inside the ifdef block for omap3 to avoid make randconfig build errors. This code is based on the TI81XX-LINUX-PSP-04.04.00.02 patches published at: http://downloads.ti.com/dsps/dsps_public_sw/psp/LinuxPSP/TI81XX_04_04/04_04_00_02/index_FDS.html Cc: Brian Hutchinson Cc: Paul Walmsley Signed-off-by: Aida Mynzhasova [tony@atomide.com: updated to apply, renamed to clockdomains81xx.c, fixed to use am33xx_clkdm_operations, various fixes suggested by Paul Walmsley] Reviewed-by: Paul Walmsley Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/Makefile | 2 + arch/arm/mach-omap2/clockdomain.h | 1 + arch/arm/mach-omap2/clockdomains81xx_data.c | 194 ++++++++++++++++++++ arch/arm/mach-omap2/cm81xx.h | 61 ++++++ arch/arm/mach-omap2/io.c | 78 ++++---- 5 files changed, 298 insertions(+), 38 deletions(-) create mode 100644 arch/arm/mach-omap2/clockdomains81xx_data.c create mode 100644 arch/arm/mach-omap2/cm81xx.h diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 3a6463f88ea2..352873c7a6a6 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -171,6 +171,8 @@ obj-$(CONFIG_ARCH_OMAP4) += $(clockdomain-common) obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o obj-$(CONFIG_SOC_AM33XX) += $(clockdomain-common) obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o +obj-$(CONFIG_SOC_TI81XX) += $(clockdomain-common) +obj-$(CONFIG_SOC_TI81XX) += clockdomains81xx_data.o obj-$(CONFIG_SOC_AM43XX) += $(clockdomain-common) obj-$(CONFIG_SOC_AM43XX) += clockdomains43xx_data.o obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common) diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h index 82c37b1becc4..77bab5fb6814 100644 --- a/arch/arm/mach-omap2/clockdomain.h +++ b/arch/arm/mach-omap2/clockdomain.h @@ -216,6 +216,7 @@ extern void __init omap242x_clockdomains_init(void); extern void __init omap243x_clockdomains_init(void); extern void __init omap3xxx_clockdomains_init(void); extern void __init am33xx_clockdomains_init(void); +extern void __init ti81xx_clockdomains_init(void); extern void __init omap44xx_clockdomains_init(void); extern void __init omap54xx_clockdomains_init(void); extern void __init dra7xx_clockdomains_init(void); diff --git a/arch/arm/mach-omap2/clockdomains81xx_data.c b/arch/arm/mach-omap2/clockdomains81xx_data.c new file mode 100644 index 000000000000..ce2a82001d0d --- /dev/null +++ b/arch/arm/mach-omap2/clockdomains81xx_data.c @@ -0,0 +1,194 @@ +/* + * TI81XX Clock Domain data. + * + * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/ + * Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_81XX_H +#define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_81XX_H + +#include +#include + +#include "clockdomain.h" +#include "cm81xx.h" + +/* + * Note that 814x seems to have HWSUP_SWSUP for many clockdomains + * while 816x does not. According to the TRM, 816x only has HWSUP + * for ALWON_L3_FAST. Also note that the TI tree clockdomains81xx.h + * seems to have the related ifdef the wrong way around claiming + * 816x supports HWSUP while 814x does not. For now, we only set + * HWSUP for ALWON_L3_FAST as that seems to be supported for both + * dm814x and dm816x. + */ + +/* Common for 81xx */ + +static struct clockdomain alwon_l3_slow_81xx_clkdm = { + .name = "alwon_l3s_clkdm", + .pwrdm = { .name = "alwon_pwrdm" }, + .cm_inst = TI81XX_CM_ALWON_MOD, + .clkdm_offs = TI81XX_CM_ALWON_L3_SLOW_CLKDM, + .flags = CLKDM_CAN_SWSUP, +}; + +static struct clockdomain alwon_l3_med_81xx_clkdm = { + .name = "alwon_l3_med_clkdm", + .pwrdm = { .name = "alwon_pwrdm" }, + .cm_inst = TI81XX_CM_ALWON_MOD, + .clkdm_offs = TI81XX_CM_ALWON_L3_MED_CLKDM, + .flags = CLKDM_CAN_SWSUP, +}; + +static struct clockdomain alwon_l3_fast_81xx_clkdm = { + .name = "alwon_l3_fast_clkdm", + .pwrdm = { .name = "alwon_pwrdm" }, + .cm_inst = TI81XX_CM_ALWON_MOD, + .clkdm_offs = TI81XX_CM_ALWON_L3_FAST_CLKDM, + .flags = CLKDM_CAN_HWSUP_SWSUP, +}; + +static struct clockdomain alwon_ethernet_81xx_clkdm = { + .name = "alwon_ethernet_clkdm", + .pwrdm = { .name = "alwon_pwrdm" }, + .cm_inst = TI81XX_CM_ALWON_MOD, + .clkdm_offs = TI81XX_CM_ETHERNET_CLKDM, + .flags = CLKDM_CAN_SWSUP, +}; + +static struct clockdomain mmu_81xx_clkdm = { + .name = "mmu_clkdm", + .pwrdm = { .name = "alwon_pwrdm" }, + .cm_inst = TI81XX_CM_ALWON_MOD, + .clkdm_offs = TI81XX_CM_MMU_CLKDM, + .flags = CLKDM_CAN_SWSUP, +}; + +static struct clockdomain mmu_cfg_81xx_clkdm = { + .name = "mmu_cfg_clkdm", + .pwrdm = { .name = "alwon_pwrdm" }, + .cm_inst = TI81XX_CM_ALWON_MOD, + .clkdm_offs = TI81XX_CM_MMUCFG_CLKDM, + .flags = CLKDM_CAN_SWSUP, +}; + +/* 816x only */ + +static struct clockdomain alwon_mpu_816x_clkdm = { + .name = "alwon_mpu_clkdm", + .pwrdm = { .name = "alwon_pwrdm" }, + .cm_inst = TI81XX_CM_ALWON_MOD, + .clkdm_offs = TI81XX_CM_ALWON_MPU_CLKDM, + .flags = CLKDM_CAN_SWSUP, +}; + +static struct clockdomain active_gem_816x_clkdm = { + .name = "active_gem_clkdm", + .pwrdm = { .name = "active_pwrdm" }, + .cm_inst = TI816X_CM_ACTIVE_MOD, + .clkdm_offs = TI816X_CM_ACTIVE_GEM_CLKDM, + .flags = CLKDM_CAN_SWSUP, +}; + +static struct clockdomain ivahd0_816x_clkdm = { + .name = "ivahd0_clkdm", + .pwrdm = { .name = "ivahd0_pwrdm" }, + .cm_inst = TI816X_CM_IVAHD0_MOD, + .clkdm_offs = TI816X_CM_IVAHD0_CLKDM, + .flags = CLKDM_CAN_SWSUP, +}; + +static struct clockdomain ivahd1_816x_clkdm = { + .name = "ivahd1_clkdm", + .pwrdm = { .name = "ivahd1_pwrdm" }, + .cm_inst = TI816X_CM_IVAHD1_MOD, + .clkdm_offs = TI816X_CM_IVAHD1_CLKDM, + .flags = CLKDM_CAN_SWSUP, +}; + +static struct clockdomain ivahd2_816x_clkdm = { + .name = "ivahd2_clkdm", + .pwrdm = { .name = "ivahd2_pwrdm" }, + .cm_inst = TI816X_CM_IVAHD2_MOD, + .clkdm_offs = TI816X_CM_IVAHD2_CLKDM, + .flags = CLKDM_CAN_SWSUP, +}; + +static struct clockdomain sgx_816x_clkdm = { + .name = "sgx_clkdm", + .pwrdm = { .name = "sgx_pwrdm" }, + .cm_inst = TI816X_CM_SGX_MOD, + .clkdm_offs = TI816X_CM_SGX_CLKDM, + .flags = CLKDM_CAN_SWSUP, +}; + +static struct clockdomain default_l3_med_816x_clkdm = { + .name = "default_l3_med_clkdm", + .pwrdm = { .name = "default_pwrdm" }, + .cm_inst = TI816X_CM_DEFAULT_MOD, + .clkdm_offs = TI816X_CM_DEFAULT_L3_MED_CLKDM, + .flags = CLKDM_CAN_SWSUP, +}; + +static struct clockdomain default_ducati_816x_clkdm = { + .name = "default_ducati_clkdm", + .pwrdm = { .name = "default_pwrdm" }, + .cm_inst = TI816X_CM_DEFAULT_MOD, + .clkdm_offs = TI816X_CM_DEFAULT_DUCATI_CLKDM, + .flags = CLKDM_CAN_SWSUP, +}; + +static struct clockdomain default_pci_816x_clkdm = { + .name = "default_pci_clkdm", + .pwrdm = { .name = "default_pwrdm" }, + .cm_inst = TI816X_CM_DEFAULT_MOD, + .clkdm_offs = TI816X_CM_DEFAULT_PCI_CLKDM, + .flags = CLKDM_CAN_SWSUP, +}; + +static struct clockdomain default_l3_slow_816x_clkdm = { + .name = "default_l3_slow_clkdm", + .pwrdm = { .name = "default_pwrdm" }, + .cm_inst = TI816X_CM_DEFAULT_MOD, + .clkdm_offs = TI816X_CM_DEFAULT_L3_SLOW_CLKDM, + .flags = CLKDM_CAN_SWSUP, +}; + +static struct clockdomain *clockdomains_ti81xx[] __initdata = { + &alwon_mpu_816x_clkdm, + &alwon_l3_slow_81xx_clkdm, + &alwon_l3_med_81xx_clkdm, + &alwon_l3_fast_81xx_clkdm, + &alwon_ethernet_81xx_clkdm, + &mmu_81xx_clkdm, + &mmu_cfg_81xx_clkdm, + &active_gem_816x_clkdm, + &ivahd0_816x_clkdm, + &ivahd1_816x_clkdm, + &ivahd2_816x_clkdm, + &sgx_816x_clkdm, + &default_l3_med_816x_clkdm, + &default_ducati_816x_clkdm, + &default_pci_816x_clkdm, + &default_l3_slow_816x_clkdm, + NULL, +}; + +void __init ti81xx_clockdomains_init(void) +{ + clkdm_register_platform_funcs(&am33xx_clkdm_operations); + clkdm_register_clkdms(clockdomains_ti81xx); + clkdm_complete_init(); +} +#endif diff --git a/arch/arm/mach-omap2/cm81xx.h b/arch/arm/mach-omap2/cm81xx.h new file mode 100644 index 000000000000..45cb407da222 --- /dev/null +++ b/arch/arm/mach-omap2/cm81xx.h @@ -0,0 +1,61 @@ +/* + * Clock domain register offsets for TI81XX. + * + * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/ + * Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_CM_TI81XX_H +#define __ARCH_ARM_MACH_OMAP2_CM_TI81XX_H + +/* TI81XX common CM module offsets */ +#define TI81XX_CM_ALWON_MOD 0x1400 /* 1KB */ + +/* TI816X CM module offsets */ +#define TI816X_CM_ACTIVE_MOD 0x0400 /* 256B */ +#define TI816X_CM_DEFAULT_MOD 0x0500 /* 256B */ +#define TI816X_CM_IVAHD0_MOD 0x0600 /* 256B */ +#define TI816X_CM_IVAHD1_MOD 0x0700 /* 256B */ +#define TI816X_CM_IVAHD2_MOD 0x0800 /* 256B */ +#define TI816X_CM_SGX_MOD 0x0900 /* 256B */ + +/* ALWON */ +#define TI81XX_CM_ALWON_L3_SLOW_CLKDM 0x0000 +#define TI81XX_CM_ALWON_L3_MED_CLKDM 0x0004 +#define TI81XX_CM_ETHERNET_CLKDM 0x0004 +#define TI81XX_CM_MMU_CLKDM 0x000C +#define TI81XX_CM_MMUCFG_CLKDM 0x0010 +#define TI81XX_CM_ALWON_MPU_CLKDM 0x001C +#define TI81XX_CM_ALWON_L3_FAST_CLKDM 0x0030 + +/* ACTIVE */ +#define TI816X_CM_ACTIVE_GEM_CLKDM 0x0000 + +/* IVAHD0 */ +#define TI816X_CM_IVAHD0_CLKDM 0x0000 + +/* IVAHD1 */ +#define TI816X_CM_IVAHD1_CLKDM 0x0000 + +/* IVAHD2 */ +#define TI816X_CM_IVAHD2_CLKDM 0x0000 + +/* SGX */ +#define TI816X_CM_SGX_CLKDM 0x0000 + +/* DEFAULT */ +#define TI816X_CM_DEFAULT_L3_MED_CLKDM 0x0004 +#define TI816X_CM_DEFAULT_PCI_CLKDM 0x0010 +#define TI816X_CM_DEFAULT_L3_SLOW_CLKDM 0x0014 +#define TI816X_CM_DEFAULT_DUCATI_CLKDM 0x0018 + +#endif diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index e4a5630149e1..ed3e6e8f91df 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -492,44 +492,6 @@ void __init am35xx_init_early(void) omap_clk_soc_init = am35xx_dt_clk_init; } -void __init ti814x_init_early(void) -{ - omap2_set_globals_tap(TI814X_CLASS, - OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE)); - omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE), - NULL); - omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE)); - omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL); - omap3xxx_check_revision(); - ti81xx_check_features(); - omap3xxx_voltagedomains_init(); - omap3xxx_powerdomains_init(); - omap3xxx_clockdomains_init(); - omap3xxx_hwmod_init(); - omap_hwmod_init_postsetup(); - if (of_have_populated_dt()) - omap_clk_soc_init = ti81xx_dt_clk_init; -} - -void __init ti816x_init_early(void) -{ - omap2_set_globals_tap(TI816X_CLASS, - OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE)); - omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE), - NULL); - omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE)); - omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL); - omap3xxx_check_revision(); - ti81xx_check_features(); - omap3xxx_voltagedomains_init(); - omap3xxx_powerdomains_init(); - omap3xxx_clockdomains_init(); - omap3xxx_hwmod_init(); - omap_hwmod_init_postsetup(); - if (of_have_populated_dt()) - omap_clk_soc_init = ti81xx_dt_clk_init; -} - void __init omap3_init_late(void) { omap_common_late_init(); @@ -572,6 +534,46 @@ void __init ti81xx_init_late(void) } #endif +#ifdef CONFIG_SOC_TI81XX +void __init ti814x_init_early(void) +{ + omap2_set_globals_tap(TI814X_CLASS, + OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE)); + omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE), + NULL); + omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE)); + omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL); + omap3xxx_check_revision(); + ti81xx_check_features(); + omap3xxx_voltagedomains_init(); + omap3xxx_powerdomains_init(); + ti81xx_clockdomains_init(); + omap3xxx_hwmod_init(); + omap_hwmod_init_postsetup(); + if (of_have_populated_dt()) + omap_clk_soc_init = ti81xx_dt_clk_init; +} + +void __init ti816x_init_early(void) +{ + omap2_set_globals_tap(TI816X_CLASS, + OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE)); + omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE), + NULL); + omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE)); + omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL); + omap3xxx_check_revision(); + ti81xx_check_features(); + omap3xxx_voltagedomains_init(); + omap3xxx_powerdomains_init(); + ti81xx_clockdomains_init(); + omap3xxx_hwmod_init(); + omap_hwmod_init_postsetup(); + if (of_have_populated_dt()) + omap_clk_soc_init = ti81xx_dt_clk_init; +} +#endif + #ifdef CONFIG_SOC_AM33XX void __init am33xx_init_early(void) { From 4d38bd1237f5bb67c3d5d183fc41db4bf4dbfb6b Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 26 Jan 2015 09:26:32 -0800 Subject: [PATCH 9/9] ARM: OMAP2+: Add dm816x hwmod support Add minimal hwmod support that works at least on dm8168. This is based on the code in the earlier TI CDP tree, and an earlier patch by Aida Mynzhasova . I've set up things to work pretty much the same way as for am33xx. We are basically using cm33xx.c with a different set of clocks and clockdomains. This code is based on the TI81XX-LINUX-PSP-04.04.00.02 patches published at: http://downloads.ti.com/dsps/dsps_public_sw/psp/LinuxPSP/TI81XX_04_04/04_04_00_02/index_FDS.html Cc: Aida Mynzhasova Cc: Brian Hutchinson Acked-by: Paul Walmsley Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/Makefile | 2 + arch/arm/mach-omap2/io.c | 8 +- arch/arm/mach-omap2/omap_hwmod.c | 2 +- arch/arm/mach-omap2/omap_hwmod.h | 1 + arch/arm/mach-omap2/omap_hwmod_81xx_data.c | 1136 ++++++++++++++++++++ 5 files changed, 1146 insertions(+), 3 deletions(-) create mode 100644 arch/arm/mach-omap2/omap_hwmod_81xx_data.c diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 352873c7a6a6..08ed2fe6366c 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -121,6 +121,7 @@ obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common) obj-$(CONFIG_SOC_OMAP5) += $(omap-prcm-4-5-common) obj-$(CONFIG_SOC_DRA7XX) += $(omap-prcm-4-5-common) am33xx-43xx-prcm-common += prm33xx.o cm33xx.o +obj-$(CONFIG_SOC_TI81XX) += $(am33xx-43xx-prcm-common) obj-$(CONFIG_SOC_AM33XX) += $(am33xx-43xx-prcm-common) obj-$(CONFIG_SOC_AM43XX) += $(omap-prcm-4-5-common) \ $(am33xx-43xx-prcm-common) @@ -226,6 +227,7 @@ obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_43xx_ipblock_data.o obj-$(CONFIG_SOC_AM43XX) += omap_hwmod_43xx_data.o obj-$(CONFIG_SOC_AM43XX) += omap_hwmod_33xx_43xx_interconnect_data.o obj-$(CONFIG_SOC_AM43XX) += omap_hwmod_33xx_43xx_ipblock_data.o +obj-$(CONFIG_SOC_TI81XX) += omap_hwmod_81xx_data.o obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o obj-$(CONFIG_SOC_OMAP5) += omap_hwmod_54xx_data.o obj-$(CONFIG_SOC_DRA7XX) += omap_hwmod_7xx_data.o diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index ed3e6e8f91df..e60780f05374 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -545,10 +545,12 @@ void __init ti814x_init_early(void) omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL); omap3xxx_check_revision(); ti81xx_check_features(); + am33xx_prm_init(); + am33xx_cm_init(); omap3xxx_voltagedomains_init(); omap3xxx_powerdomains_init(); ti81xx_clockdomains_init(); - omap3xxx_hwmod_init(); + ti81xx_hwmod_init(); omap_hwmod_init_postsetup(); if (of_have_populated_dt()) omap_clk_soc_init = ti81xx_dt_clk_init; @@ -564,10 +566,12 @@ void __init ti816x_init_early(void) omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL); omap3xxx_check_revision(); ti81xx_check_features(); + am33xx_prm_init(); + am33xx_cm_init(); omap3xxx_voltagedomains_init(); omap3xxx_powerdomains_init(); ti81xx_clockdomains_init(); - omap3xxx_hwmod_init(); + ti81xx_hwmod_init(); omap_hwmod_init_postsetup(); if (of_have_populated_dt()) omap_clk_soc_init = ti81xx_dt_clk_init; diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index cbb908dc5cf0..d7e6d5c8d171 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -4142,7 +4142,7 @@ void __init omap_hwmod_init(void) soc_ops.deassert_hardreset = _omap4_deassert_hardreset; soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted; soc_ops.init_clkdm = _init_clkdm; - } else if (soc_is_am33xx()) { + } else if (cpu_is_ti816x() || soc_is_am33xx()) { soc_ops.enable_module = _omap4_enable_module; soc_ops.disable_module = _omap4_disable_module; soc_ops.wait_target_ready = _omap4_wait_target_ready; diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h index 35ca6efbec31..4b070b42a15c 100644 --- a/arch/arm/mach-omap2/omap_hwmod.h +++ b/arch/arm/mach-omap2/omap_hwmod.h @@ -763,6 +763,7 @@ extern int omap3xxx_hwmod_init(void); extern int omap44xx_hwmod_init(void); extern int omap54xx_hwmod_init(void); extern int am33xx_hwmod_init(void); +extern int ti81xx_hwmod_init(void); extern int dra7xx_hwmod_init(void); int am43xx_hwmod_init(void); diff --git a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c new file mode 100644 index 000000000000..cab1eb61ac96 --- /dev/null +++ b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c @@ -0,0 +1,1136 @@ +/* + * DM81xx hwmod data. + * + * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/ + * Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include + +#include "omap_hwmod_common_data.h" +#include "cm81xx.h" +#include "ti81xx.h" +#include "wd_timer.h" + +/* + * DM816X hardware modules integration data + * + * Note: This is incomplete and at present, not generated from h/w database. + */ + +/* + * The alwon .clkctrl_offs field is offset from the CM_ALWON, that's + * TRM 18.7.17 CM_ALWON device register values minus 0x1400. + */ +#define DM816X_DM_ALWON_BASE 0x1400 +#define DM816X_CM_ALWON_MCASP0_CLKCTRL (0x1540 - DM816X_DM_ALWON_BASE) +#define DM816X_CM_ALWON_MCASP1_CLKCTRL (0x1544 - DM816X_DM_ALWON_BASE) +#define DM816X_CM_ALWON_MCASP2_CLKCTRL (0x1548 - DM816X_DM_ALWON_BASE) +#define DM816X_CM_ALWON_MCBSP_CLKCTRL (0x154c - DM816X_DM_ALWON_BASE) +#define DM816X_CM_ALWON_UART_0_CLKCTRL (0x1550 - DM816X_DM_ALWON_BASE) +#define DM816X_CM_ALWON_UART_1_CLKCTRL (0x1554 - DM816X_DM_ALWON_BASE) +#define DM816X_CM_ALWON_UART_2_CLKCTRL (0x1558 - DM816X_DM_ALWON_BASE) +#define DM816X_CM_ALWON_GPIO_0_CLKCTRL (0x155c - DM816X_DM_ALWON_BASE) +#define DM816X_CM_ALWON_GPIO_1_CLKCTRL (0x1560 - DM816X_DM_ALWON_BASE) +#define DM816X_CM_ALWON_I2C_0_CLKCTRL (0x1564 - DM816X_DM_ALWON_BASE) +#define DM816X_CM_ALWON_I2C_1_CLKCTRL (0x1568 - DM816X_DM_ALWON_BASE) +#define DM816X_CM_ALWON_TIMER_1_CLKCTRL (0x1570 - DM816X_DM_ALWON_BASE) +#define DM816X_CM_ALWON_TIMER_2_CLKCTRL (0x1574 - DM816X_DM_ALWON_BASE) +#define DM816X_CM_ALWON_TIMER_3_CLKCTRL (0x1578 - DM816X_DM_ALWON_BASE) +#define DM816X_CM_ALWON_TIMER_4_CLKCTRL (0x157c - DM816X_DM_ALWON_BASE) +#define DM816X_CM_ALWON_TIMER_5_CLKCTRL (0x1580 - DM816X_DM_ALWON_BASE) +#define DM816X_CM_ALWON_TIMER_6_CLKCTRL (0x1584 - DM816X_DM_ALWON_BASE) +#define DM816X_CM_ALWON_TIMER_7_CLKCTRL (0x1588 - DM816X_DM_ALWON_BASE) +#define DM816X_CM_ALWON_WDTIMER_CLKCTRL (0x158c - DM816X_DM_ALWON_BASE) +#define DM816X_CM_ALWON_SPI_CLKCTRL (0x1590 - DM816X_DM_ALWON_BASE) +#define DM816X_CM_ALWON_MAILBOX_CLKCTRL (0x1594 - DM816X_DM_ALWON_BASE) +#define DM816X_CM_ALWON_SPINBOX_CLKCTRL (0x1598 - DM816X_DM_ALWON_BASE) +#define DM816X_CM_ALWON_MMUDATA_CLKCTRL (0x159c - DM816X_DM_ALWON_BASE) +#define DM816X_CM_ALWON_MMUCFG_CLKCTRL (0x15a8 - DM816X_DM_ALWON_BASE) +#define DM816X_CM_ALWON_SDIO_CLKCTRL (0x15b0 - DM816X_DM_ALWON_BASE) +#define DM816X_CM_ALWON_OCMC_0_CLKCTRL (0x15b4 - DM816X_DM_ALWON_BASE) +#define DM816X_CM_ALWON_OCMC_1_CLKCTRL (0x15b8 - DM816X_DM_ALWON_BASE) +#define DM816X_CM_ALWON_CONTRL_CLKCTRL (0x15c4 - DM816X_DM_ALWON_BASE) +#define DM816X_CM_ALWON_GPMC_CLKCTRL (0x15d0 - DM816X_DM_ALWON_BASE) +#define DM816X_CM_ALWON_ETHERNET_0_CLKCTRL (0x15d4 - DM816X_DM_ALWON_BASE) +#define DM816X_CM_ALWON_ETHERNET_1_CLKCTRL (0x15d8 - DM816X_DM_ALWON_BASE) +#define DM816X_CM_ALWON_MPU_CLKCTRL (0x15dc - DM816X_DM_ALWON_BASE) +#define DM816X_CM_ALWON_L3_CLKCTRL (0x15e4 - DM816X_DM_ALWON_BASE) +#define DM816X_CM_ALWON_L4HS_CLKCTRL (0x15e8 - DM816X_DM_ALWON_BASE) +#define DM816X_CM_ALWON_L4LS_CLKCTRL (0x15ec - DM816X_DM_ALWON_BASE) +#define DM816X_CM_ALWON_RTC_CLKCTRL (0x15f0 - DM816X_DM_ALWON_BASE) +#define DM816X_CM_ALWON_TPCC_CLKCTRL (0x15f4 - DM816X_DM_ALWON_BASE) +#define DM816X_CM_ALWON_TPTC0_CLKCTRL (0x15f8 - DM816X_DM_ALWON_BASE) +#define DM816X_CM_ALWON_TPTC1_CLKCTRL (0x15fc - DM816X_DM_ALWON_BASE) +#define DM816X_CM_ALWON_TPTC2_CLKCTRL (0x1600 - DM816X_DM_ALWON_BASE) +#define DM816X_CM_ALWON_TPTC3_CLKCTRL (0x1604 - DM816X_DM_ALWON_BASE) +#define DM816X_CM_ALWON_SR_0_CLKCTRL (0x1608 - DM816X_DM_ALWON_BASE) +#define DM816X_CM_ALWON_SR_1_CLKCTRL (0x160c - DM816X_DM_ALWON_BASE) + +/* + * The default .clkctrl_offs field is offset from CM_DEFAULT, that's + * TRM 18.7.6 CM_DEFAULT device register values minus 0x500 + */ +#define DM816X_CM_DEFAULT_OFFSET 0x500 +#define DM816X_CM_DEFAULT_USB_CLKCTRL (0x558 - DM816X_CM_DEFAULT_OFFSET) + +/* L3 Interconnect entries clocked at 125, 250 and 500MHz */ +static struct omap_hwmod dm816x_alwon_l3_slow_hwmod = { + .name = "alwon_l3_slow", + .clkdm_name = "alwon_l3s_clkdm", + .class = &l3_hwmod_class, + .flags = HWMOD_NO_IDLEST, +}; + +static struct omap_hwmod dm816x_default_l3_slow_hwmod = { + .name = "default_l3_slow", + .clkdm_name = "default_l3_slow_clkdm", + .class = &l3_hwmod_class, + .flags = HWMOD_NO_IDLEST, +}; + +static struct omap_hwmod dm816x_alwon_l3_med_hwmod = { + .name = "l3_med", + .clkdm_name = "alwon_l3_med_clkdm", + .class = &l3_hwmod_class, + .flags = HWMOD_NO_IDLEST, +}; + +static struct omap_hwmod dm816x_alwon_l3_fast_hwmod = { + .name = "l3_fast", + .clkdm_name = "alwon_l3_fast_clkdm", + .class = &l3_hwmod_class, + .flags = HWMOD_NO_IDLEST, +}; + +/* + * L4 standard peripherals, see TRM table 1-12 for devices using this. + * See TRM table 1-73 for devices using the 125MHz SYSCLK6 clock. + */ +static struct omap_hwmod dm816x_l4_ls_hwmod = { + .name = "l4_ls", + .clkdm_name = "alwon_l3s_clkdm", + .class = &l4_hwmod_class, +}; + +/* + * L4 high-speed peripherals. For devices using this, please see the TRM + * table 1-13. On dm816x, only EMAC, MDIO and SATA use this. See also TRM + * table 1-73 for devices using 250MHz SYSCLK5 clock. + */ +static struct omap_hwmod dm816x_l4_hs_hwmod = { + .name = "l4_hs", + .clkdm_name = "alwon_l3_med_clkdm", + .class = &l4_hwmod_class, +}; + +/* L3 slow -> L4 ls peripheral interface running at 125MHz */ +static struct omap_hwmod_ocp_if dm816x_alwon_l3_slow__l4_ls = { + .master = &dm816x_alwon_l3_slow_hwmod, + .slave = &dm816x_l4_ls_hwmod, + .user = OCP_USER_MPU, +}; + +/* L3 med -> L4 fast peripheral interface running at 250MHz */ +static struct omap_hwmod_ocp_if dm816x_alwon_l3_slow__l4_hs = { + .master = &dm816x_alwon_l3_med_hwmod, + .slave = &dm816x_l4_hs_hwmod, + .user = OCP_USER_MPU, +}; + +/* MPU */ +static struct omap_hwmod dm816x_mpu_hwmod = { + .name = "mpu", + .clkdm_name = "alwon_mpu_clkdm", + .class = &mpu_hwmod_class, + .flags = HWMOD_INIT_NO_IDLE, + .main_clk = "mpu_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DM816X_CM_ALWON_MPU_CLKCTRL, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_slow = { + .master = &dm816x_mpu_hwmod, + .slave = &dm816x_alwon_l3_slow_hwmod, + .user = OCP_USER_MPU, +}; + +/* L3 med peripheral interface running at 250MHz */ +static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_med = { + .master = &dm816x_mpu_hwmod, + .slave = &dm816x_alwon_l3_med_hwmod, + .user = OCP_USER_MPU, +}; + +/* UART common */ +static struct omap_hwmod_class_sysconfig uart_sysc = { + .rev_offs = 0x50, + .sysc_offs = 0x54, + .syss_offs = 0x58, + .sysc_flags = SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | + SYSS_HAS_RESET_STATUS, + .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + MSTANDBY_SMART_WKUP, + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class uart_class = { + .name = "uart", + .sysc = &uart_sysc, +}; + +static struct omap_hwmod dm816x_uart1_hwmod = { + .name = "uart1", + .clkdm_name = "alwon_l3s_clkdm", + .main_clk = "sysclk10_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DM816X_CM_ALWON_UART_0_CLKCTRL, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .class = &uart_class, + .flags = DEBUG_TI81XXUART1_FLAGS, +}; + +static struct omap_hwmod_ocp_if dm816x_l4_ls__uart1 = { + .master = &dm816x_l4_ls_hwmod, + .slave = &dm816x_uart1_hwmod, + .clk = "sysclk6_ck", + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod dm816x_uart2_hwmod = { + .name = "uart2", + .clkdm_name = "alwon_l3s_clkdm", + .main_clk = "sysclk10_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DM816X_CM_ALWON_UART_1_CLKCTRL, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .class = &uart_class, + .flags = DEBUG_TI81XXUART2_FLAGS, +}; + +static struct omap_hwmod_ocp_if dm816x_l4_ls__uart2 = { + .master = &dm816x_l4_ls_hwmod, + .slave = &dm816x_uart2_hwmod, + .clk = "sysclk6_ck", + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod dm816x_uart3_hwmod = { + .name = "uart3", + .clkdm_name = "alwon_l3s_clkdm", + .main_clk = "sysclk10_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DM816X_CM_ALWON_UART_2_CLKCTRL, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .class = &uart_class, + .flags = DEBUG_TI81XXUART3_FLAGS, +}; + +static struct omap_hwmod_ocp_if dm816x_l4_ls__uart3 = { + .master = &dm816x_l4_ls_hwmod, + .slave = &dm816x_uart3_hwmod, + .clk = "sysclk6_ck", + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_class_sysconfig wd_timer_sysc = { + .rev_offs = 0x0, + .sysc_offs = 0x10, + .syss_offs = 0x14, + .sysc_flags = SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET | + SYSS_HAS_RESET_STATUS, + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class wd_timer_class = { + .name = "wd_timer", + .sysc = &wd_timer_sysc, + .pre_shutdown = &omap2_wd_timer_disable, + .reset = &omap2_wd_timer_reset, +}; + +static struct omap_hwmod dm816x_wd_timer_hwmod = { + .name = "wd_timer", + .clkdm_name = "alwon_l3s_clkdm", + .main_clk = "sysclk18_ck", + .flags = HWMOD_NO_IDLEST, + .prcm = { + .omap4 = { + .clkctrl_offs = DM816X_CM_ALWON_WDTIMER_CLKCTRL, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .class = &wd_timer_class, +}; + +static struct omap_hwmod_ocp_if dm816x_l4_ls__wd_timer1 = { + .master = &dm816x_l4_ls_hwmod, + .slave = &dm816x_wd_timer_hwmod, + .clk = "sysclk6_ck", + .user = OCP_USER_MPU, +}; + +/* I2C common */ +static struct omap_hwmod_class_sysconfig i2c_sysc = { + .rev_offs = 0x0, + .sysc_offs = 0x10, + .syss_offs = 0x90, + .sysc_flags = SYSC_HAS_SIDLEMODE | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE, + .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class i2c_class = { + .name = "i2c", + .sysc = &i2c_sysc, +}; + +static struct omap_hwmod dm81xx_i2c1_hwmod = { + .name = "i2c1", + .clkdm_name = "alwon_l3s_clkdm", + .main_clk = "sysclk10_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DM816X_CM_ALWON_I2C_0_CLKCTRL, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .class = &i2c_class, +}; + +static struct omap_hwmod_ocp_if dm816x_l4_ls__i2c1 = { + .master = &dm816x_l4_ls_hwmod, + .slave = &dm81xx_i2c1_hwmod, + .clk = "sysclk6_ck", + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod dm816x_i2c2_hwmod = { + .name = "i2c2", + .clkdm_name = "alwon_l3s_clkdm", + .main_clk = "sysclk10_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DM816X_CM_ALWON_I2C_1_CLKCTRL, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .class = &i2c_class, +}; + +static struct omap_hwmod_class_sysconfig dm81xx_elm_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | + SYSS_HAS_RESET_STATUS, + .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_ocp_if dm816x_l4_ls__i2c2 = { + .master = &dm816x_l4_ls_hwmod, + .slave = &dm816x_i2c2_hwmod, + .clk = "sysclk6_ck", + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_class dm81xx_elm_hwmod_class = { + .name = "elm", + .sysc = &dm81xx_elm_sysc, +}; + +static struct omap_hwmod dm81xx_elm_hwmod = { + .name = "elm", + .clkdm_name = "alwon_l3s_clkdm", + .class = &dm81xx_elm_hwmod_class, + .main_clk = "sysclk6_ck", +}; + +static struct omap_hwmod_ocp_if dm81xx_l4_ls__elm = { + .master = &dm816x_l4_ls_hwmod, + .slave = &dm81xx_elm_hwmod, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_class_sysconfig dm81xx_gpio_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0114, + .sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | + SYSS_HAS_RESET_STATUS, + .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP, + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class dm81xx_gpio_hwmod_class = { + .name = "gpio", + .sysc = &dm81xx_gpio_sysc, + .rev = 2, +}; + +static struct omap_gpio_dev_attr gpio_dev_attr = { + .bank_width = 32, + .dbck_flag = true, +}; + +static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { + { .role = "dbclk", .clk = "sysclk18_ck" }, +}; + +static struct omap_hwmod dm81xx_gpio1_hwmod = { + .name = "gpio1", + .clkdm_name = "alwon_l3s_clkdm", + .class = &dm81xx_gpio_hwmod_class, + .main_clk = "sysclk6_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DM816X_CM_ALWON_GPIO_0_CLKCTRL, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = gpio1_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), + .dev_attr = &gpio_dev_attr, +}; + +static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio1 = { + .master = &dm816x_l4_ls_hwmod, + .slave = &dm81xx_gpio1_hwmod, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { + { .role = "dbclk", .clk = "sysclk18_ck" }, +}; + +static struct omap_hwmod dm81xx_gpio2_hwmod = { + .name = "gpio2", + .clkdm_name = "alwon_l3s_clkdm", + .class = &dm81xx_gpio_hwmod_class, + .main_clk = "sysclk6_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DM816X_CM_ALWON_GPIO_1_CLKCTRL, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = gpio2_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), + .dev_attr = &gpio_dev_attr, +}; + +static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio2 = { + .master = &dm816x_l4_ls_hwmod, + .slave = &dm81xx_gpio2_hwmod, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_class_sysconfig dm81xx_gpmc_sysc = { + .rev_offs = 0x0, + .sysc_offs = 0x10, + .syss_offs = 0x14, + .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS, + .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class dm81xx_gpmc_hwmod_class = { + .name = "gpmc", + .sysc = &dm81xx_gpmc_sysc, +}; + +static struct omap_hwmod dm81xx_gpmc_hwmod = { + .name = "gpmc", + .clkdm_name = "alwon_l3s_clkdm", + .class = &dm81xx_gpmc_hwmod_class, + .main_clk = "sysclk6_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DM816X_CM_ALWON_GPMC_CLKCTRL, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__gpmc = { + .master = &dm816x_alwon_l3_slow_hwmod, + .slave = &dm81xx_gpmc_hwmod, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_class_sysconfig dm81xx_usbhsotg_sysc = { + .rev_offs = 0x0, + .sysc_offs = 0x10, + .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | + SYSC_HAS_SOFTRESET, + .idlemodes = SIDLE_SMART | MSTANDBY_FORCE | MSTANDBY_SMART, + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class dm81xx_usbotg_class = { + .name = "usbotg", + .sysc = &dm81xx_usbhsotg_sysc, +}; + +static struct omap_hwmod dm81xx_usbss_hwmod = { + .name = "usb_otg_hs", + .clkdm_name = "default_l3_slow_clkdm", + .main_clk = "sysclk6_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DM816X_CM_DEFAULT_USB_CLKCTRL, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .class = &dm81xx_usbotg_class, +}; + +static struct omap_hwmod_ocp_if dm81xx_default_l3_slow__usbss = { + .master = &dm816x_default_l3_slow_hwmod, + .slave = &dm81xx_usbss_hwmod, + .clk = "sysclk6_ck", + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_class_sysconfig dm816x_timer_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET, + .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP, + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class dm816x_timer_hwmod_class = { + .name = "timer", + .sysc = &dm816x_timer_sysc, +}; + +static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { + .timer_capability = OMAP_TIMER_ALWON, +}; + +static struct omap_hwmod dm816x_timer1_hwmod = { + .name = "timer1", + .clkdm_name = "alwon_l3s_clkdm", + .main_clk = "timer1_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = DM816X_CM_ALWON_TIMER_1_CLKCTRL, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &capability_alwon_dev_attr, + .class = &dm816x_timer_hwmod_class, +}; + +static struct omap_hwmod_ocp_if dm816x_l4_ls__timer1 = { + .master = &dm816x_l4_ls_hwmod, + .slave = &dm816x_timer1_hwmod, + .clk = "sysclk6_ck", + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod dm816x_timer2_hwmod = { + .name = "timer2", + .clkdm_name = "alwon_l3s_clkdm", + .main_clk = "timer2_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = DM816X_CM_ALWON_TIMER_2_CLKCTRL, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &capability_alwon_dev_attr, + .class = &dm816x_timer_hwmod_class, +}; + +static struct omap_hwmod_ocp_if dm816x_l4_ls__timer2 = { + .master = &dm816x_l4_ls_hwmod, + .slave = &dm816x_timer2_hwmod, + .clk = "sysclk6_ck", + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod dm816x_timer3_hwmod = { + .name = "timer3", + .clkdm_name = "alwon_l3s_clkdm", + .main_clk = "timer3_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = DM816X_CM_ALWON_TIMER_3_CLKCTRL, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &capability_alwon_dev_attr, + .class = &dm816x_timer_hwmod_class, +}; + +static struct omap_hwmod_ocp_if dm816x_l4_ls__timer3 = { + .master = &dm816x_l4_ls_hwmod, + .slave = &dm816x_timer3_hwmod, + .clk = "sysclk6_ck", + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod dm816x_timer4_hwmod = { + .name = "timer4", + .clkdm_name = "alwon_l3s_clkdm", + .main_clk = "timer4_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = DM816X_CM_ALWON_TIMER_4_CLKCTRL, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &capability_alwon_dev_attr, + .class = &dm816x_timer_hwmod_class, +}; + +static struct omap_hwmod_ocp_if dm816x_l4_ls__timer4 = { + .master = &dm816x_l4_ls_hwmod, + .slave = &dm816x_timer4_hwmod, + .clk = "sysclk6_ck", + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod dm816x_timer5_hwmod = { + .name = "timer5", + .clkdm_name = "alwon_l3s_clkdm", + .main_clk = "timer5_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = DM816X_CM_ALWON_TIMER_5_CLKCTRL, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &capability_alwon_dev_attr, + .class = &dm816x_timer_hwmod_class, +}; + +static struct omap_hwmod_ocp_if dm816x_l4_ls__timer5 = { + .master = &dm816x_l4_ls_hwmod, + .slave = &dm816x_timer5_hwmod, + .clk = "sysclk6_ck", + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod dm816x_timer6_hwmod = { + .name = "timer6", + .clkdm_name = "alwon_l3s_clkdm", + .main_clk = "timer6_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = DM816X_CM_ALWON_TIMER_6_CLKCTRL, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &capability_alwon_dev_attr, + .class = &dm816x_timer_hwmod_class, +}; + +static struct omap_hwmod_ocp_if dm816x_l4_ls__timer6 = { + .master = &dm816x_l4_ls_hwmod, + .slave = &dm816x_timer6_hwmod, + .clk = "sysclk6_ck", + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod dm816x_timer7_hwmod = { + .name = "timer7", + .clkdm_name = "alwon_l3s_clkdm", + .main_clk = "timer7_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = DM816X_CM_ALWON_TIMER_7_CLKCTRL, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &capability_alwon_dev_attr, + .class = &dm816x_timer_hwmod_class, +}; + +static struct omap_hwmod_ocp_if dm816x_l4_ls__timer7 = { + .master = &dm816x_l4_ls_hwmod, + .slave = &dm816x_timer7_hwmod, + .clk = "sysclk6_ck", + .user = OCP_USER_MPU, +}; + +/* EMAC Ethernet */ +static struct omap_hwmod_class_sysconfig dm816x_emac_sysc = { + .rev_offs = 0x0, + .sysc_offs = 0x4, + .sysc_flags = SYSC_HAS_SOFTRESET, + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class dm816x_emac_hwmod_class = { + .name = "emac", + .sysc = &dm816x_emac_sysc, +}; + +/* + * On dm816x the MDIO is within EMAC0. As the MDIO driver is a separate + * driver probed before EMAC0, we let MDIO do the clock idling. + */ +static struct omap_hwmod dm816x_emac0_hwmod = { + .name = "emac0", + .clkdm_name = "alwon_ethernet_clkdm", + .class = &dm816x_emac_hwmod_class, +}; + +static struct omap_hwmod_ocp_if dm816x_l4_hs__emac0 = { + .master = &dm816x_l4_hs_hwmod, + .slave = &dm816x_emac0_hwmod, + .clk = "sysclk5_ck", + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_class dm816x_mdio_hwmod_class = { + .name = "davinci_mdio", + .sysc = &dm816x_emac_sysc, +}; + +struct omap_hwmod dm816x_emac0_mdio_hwmod = { + .name = "davinci_mdio", + .class = &dm816x_mdio_hwmod_class, + .clkdm_name = "alwon_ethernet_clkdm", + .main_clk = "sysclk24_ck", + .flags = HWMOD_NO_IDLEST, + /* + * REVISIT: This should be moved to the emac0_hwmod + * once we have a better way to handle device slaves. + */ + .prcm = { + .omap4 = { + .clkctrl_offs = DM816X_CM_ALWON_ETHERNET_0_CLKCTRL, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +struct omap_hwmod_ocp_if dm816x_emac0__mdio = { + .master = &dm816x_l4_hs_hwmod, + .slave = &dm816x_emac0_mdio_hwmod, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod dm816x_emac1_hwmod = { + .name = "emac1", + .clkdm_name = "alwon_ethernet_clkdm", + .main_clk = "sysclk24_ck", + .flags = HWMOD_NO_IDLEST, + .prcm = { + .omap4 = { + .clkctrl_offs = DM816X_CM_ALWON_ETHERNET_1_CLKCTRL, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .class = &dm816x_emac_hwmod_class, +}; + +static struct omap_hwmod_ocp_if dm816x_l4_hs__emac1 = { + .master = &dm816x_l4_hs_hwmod, + .slave = &dm816x_emac1_hwmod, + .clk = "sysclk5_ck", + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_class_sysconfig dm816x_mmc_sysc = { + .rev_offs = 0x0, + .sysc_offs = 0x110, + .syss_offs = 0x114, + .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS, + .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class dm816x_mmc_class = { + .name = "mmc", + .sysc = &dm816x_mmc_sysc, +}; + +static struct omap_hwmod_opt_clk dm816x_mmc1_opt_clks[] = { + { .role = "dbck", .clk = "sysclk18_ck", }, +}; + +static struct omap_hsmmc_dev_attr mmc1_dev_attr = { + .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, +}; + +static struct omap_hwmod dm816x_mmc1_hwmod = { + .name = "mmc1", + .clkdm_name = "alwon_l3s_clkdm", + .opt_clks = dm816x_mmc1_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(dm816x_mmc1_opt_clks), + .main_clk = "sysclk10_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DM816X_CM_ALWON_SDIO_CLKCTRL, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &mmc1_dev_attr, + .class = &dm816x_mmc_class, +}; + +static struct omap_hwmod_ocp_if dm816x_l4_ls__mmc1 = { + .master = &dm816x_l4_ls_hwmod, + .slave = &dm816x_mmc1_hwmod, + .clk = "sysclk6_ck", + .user = OCP_USER_MPU, + .flags = OMAP_FIREWALL_L4 +}; + +static struct omap_hwmod_class_sysconfig dm816x_mcspi_sysc = { + .rev_offs = 0x0, + .sysc_offs = 0x110, + .syss_offs = 0x114, + .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS, + .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class dm816x_mcspi_class = { + .name = "mcspi", + .sysc = &dm816x_mcspi_sysc, + .rev = OMAP3_MCSPI_REV, +}; + +static struct omap2_mcspi_dev_attr dm816x_mcspi1_dev_attr = { + .num_chipselect = 4, +}; + +static struct omap_hwmod dm816x_mcspi1_hwmod = { + .name = "mcspi1", + .clkdm_name = "alwon_l3s_clkdm", + .main_clk = "sysclk10_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DM816X_CM_ALWON_SPI_CLKCTRL, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .class = &dm816x_mcspi_class, + .dev_attr = &dm816x_mcspi1_dev_attr, +}; + +static struct omap_hwmod_ocp_if dm816x_l4_ls__mcspi1 = { + .master = &dm816x_l4_ls_hwmod, + .slave = &dm816x_mcspi1_hwmod, + .clk = "sysclk6_ck", + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_class_sysconfig dm816x_mailbox_sysc = { + .rev_offs = 0x000, + .sysc_offs = 0x010, + .syss_offs = 0x014, + .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE, + .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class dm816x_mailbox_hwmod_class = { + .name = "mailbox", + .sysc = &dm816x_mailbox_sysc, +}; + +static struct omap_hwmod dm816x_mailbox_hwmod = { + .name = "mailbox", + .clkdm_name = "alwon_l3s_clkdm", + .class = &dm816x_mailbox_hwmod_class, + .main_clk = "sysclk6_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DM816X_CM_ALWON_MAILBOX_CLKCTRL, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +static struct omap_hwmod_ocp_if dm816x_l4_ls__mailbox = { + .master = &dm816x_l4_ls_hwmod, + .slave = &dm816x_mailbox_hwmod, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_class dm816x_tpcc_hwmod_class = { + .name = "tpcc", +}; + +struct omap_hwmod dm816x_tpcc_hwmod = { + .name = "tpcc", + .class = &dm816x_tpcc_hwmod_class, + .clkdm_name = "alwon_l3s_clkdm", + .main_clk = "sysclk4_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DM816X_CM_ALWON_TPCC_CLKCTRL, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +struct omap_hwmod_ocp_if dm816x_alwon_l3_fast__tpcc = { + .master = &dm816x_alwon_l3_fast_hwmod, + .slave = &dm816x_tpcc_hwmod, + .clk = "sysclk4_ck", + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space dm816x_tptc0_addr_space[] = { + { + .pa_start = 0x49800000, + .pa_end = 0x49800000 + SZ_8K - 1, + .flags = ADDR_TYPE_RT, + }, + { }, +}; + +static struct omap_hwmod_class dm816x_tptc0_hwmod_class = { + .name = "tptc0", +}; + +struct omap_hwmod dm816x_tptc0_hwmod = { + .name = "tptc0", + .class = &dm816x_tptc0_hwmod_class, + .clkdm_name = "alwon_l3s_clkdm", + .main_clk = "sysclk4_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DM816X_CM_ALWON_TPTC0_CLKCTRL, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +struct omap_hwmod_ocp_if dm816x_alwon_l3_fast__tptc0 = { + .master = &dm816x_alwon_l3_fast_hwmod, + .slave = &dm816x_tptc0_hwmod, + .clk = "sysclk4_ck", + .addr = dm816x_tptc0_addr_space, + .user = OCP_USER_MPU, +}; + +struct omap_hwmod_ocp_if dm816x_tptc0__alwon_l3_fast = { + .master = &dm816x_tptc0_hwmod, + .slave = &dm816x_alwon_l3_fast_hwmod, + .clk = "sysclk4_ck", + .addr = dm816x_tptc0_addr_space, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space dm816x_tptc1_addr_space[] = { + { + .pa_start = 0x49900000, + .pa_end = 0x49900000 + SZ_8K - 1, + .flags = ADDR_TYPE_RT, + }, + { }, +}; + +static struct omap_hwmod_class dm816x_tptc1_hwmod_class = { + .name = "tptc1", +}; + +struct omap_hwmod dm816x_tptc1_hwmod = { + .name = "tptc1", + .class = &dm816x_tptc1_hwmod_class, + .clkdm_name = "alwon_l3s_clkdm", + .main_clk = "sysclk4_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DM816X_CM_ALWON_TPTC1_CLKCTRL, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +struct omap_hwmod_ocp_if dm816x_alwon_l3_fast__tptc1 = { + .master = &dm816x_alwon_l3_fast_hwmod, + .slave = &dm816x_tptc1_hwmod, + .clk = "sysclk4_ck", + .addr = dm816x_tptc1_addr_space, + .user = OCP_USER_MPU, +}; + +struct omap_hwmod_ocp_if dm816x_tptc1__alwon_l3_fast = { + .master = &dm816x_tptc1_hwmod, + .slave = &dm816x_alwon_l3_fast_hwmod, + .clk = "sysclk4_ck", + .addr = dm816x_tptc1_addr_space, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space dm816x_tptc2_addr_space[] = { + { + .pa_start = 0x49a00000, + .pa_end = 0x49a00000 + SZ_8K - 1, + .flags = ADDR_TYPE_RT, + }, + { }, +}; + +static struct omap_hwmod_class dm816x_tptc2_hwmod_class = { + .name = "tptc2", +}; + +struct omap_hwmod dm816x_tptc2_hwmod = { + .name = "tptc2", + .class = &dm816x_tptc2_hwmod_class, + .clkdm_name = "alwon_l3s_clkdm", + .main_clk = "sysclk4_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DM816X_CM_ALWON_TPTC2_CLKCTRL, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +struct omap_hwmod_ocp_if dm816x_alwon_l3_fast__tptc2 = { + .master = &dm816x_alwon_l3_fast_hwmod, + .slave = &dm816x_tptc2_hwmod, + .clk = "sysclk4_ck", + .addr = dm816x_tptc2_addr_space, + .user = OCP_USER_MPU, +}; + +struct omap_hwmod_ocp_if dm816x_tptc2__alwon_l3_fast = { + .master = &dm816x_tptc2_hwmod, + .slave = &dm816x_alwon_l3_fast_hwmod, + .clk = "sysclk4_ck", + .addr = dm816x_tptc2_addr_space, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space dm816x_tptc3_addr_space[] = { + { + .pa_start = 0x49b00000, + .pa_end = 0x49b00000 + SZ_8K - 1, + .flags = ADDR_TYPE_RT, + }, + { }, +}; + +static struct omap_hwmod_class dm816x_tptc3_hwmod_class = { + .name = "tptc3", +}; + +struct omap_hwmod dm816x_tptc3_hwmod = { + .name = "tptc3", + .class = &dm816x_tptc3_hwmod_class, + .clkdm_name = "alwon_l3s_clkdm", + .main_clk = "sysclk4_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DM816X_CM_ALWON_TPTC3_CLKCTRL, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +struct omap_hwmod_ocp_if dm816x_alwon_l3_fast__tptc3 = { + .master = &dm816x_alwon_l3_fast_hwmod, + .slave = &dm816x_tptc3_hwmod, + .clk = "sysclk4_ck", + .addr = dm816x_tptc3_addr_space, + .user = OCP_USER_MPU, +}; + +struct omap_hwmod_ocp_if dm816x_tptc3__alwon_l3_fast = { + .master = &dm816x_tptc3_hwmod, + .slave = &dm816x_alwon_l3_fast_hwmod, + .clk = "sysclk4_ck", + .addr = dm816x_tptc3_addr_space, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_ocp_if *dm816x_hwmod_ocp_ifs[] __initdata = { + &dm816x_mpu__alwon_l3_slow, + &dm816x_mpu__alwon_l3_med, + &dm816x_alwon_l3_slow__l4_ls, + &dm816x_alwon_l3_slow__l4_hs, + &dm816x_l4_ls__uart1, + &dm816x_l4_ls__uart2, + &dm816x_l4_ls__uart3, + &dm816x_l4_ls__wd_timer1, + &dm816x_l4_ls__i2c1, + &dm816x_l4_ls__i2c2, + &dm81xx_l4_ls__gpio1, + &dm81xx_l4_ls__gpio2, + &dm81xx_l4_ls__elm, + &dm816x_l4_ls__mmc1, + &dm816x_l4_ls__timer1, + &dm816x_l4_ls__timer2, + &dm816x_l4_ls__timer3, + &dm816x_l4_ls__timer4, + &dm816x_l4_ls__timer5, + &dm816x_l4_ls__timer6, + &dm816x_l4_ls__timer7, + &dm816x_l4_ls__mcspi1, + &dm816x_l4_ls__mailbox, + &dm816x_l4_hs__emac0, + &dm816x_emac0__mdio, + &dm816x_l4_hs__emac1, + &dm816x_alwon_l3_fast__tpcc, + &dm816x_alwon_l3_fast__tptc0, + &dm816x_alwon_l3_fast__tptc1, + &dm816x_alwon_l3_fast__tptc2, + &dm816x_alwon_l3_fast__tptc3, + &dm816x_tptc0__alwon_l3_fast, + &dm816x_tptc1__alwon_l3_fast, + &dm816x_tptc2__alwon_l3_fast, + &dm816x_tptc3__alwon_l3_fast, + &dm81xx_alwon_l3_slow__gpmc, + &dm81xx_default_l3_slow__usbss, + NULL, +}; + +int __init ti81xx_hwmod_init(void) +{ + omap_hwmod_init(); + return omap_hwmod_register_links(dm816x_hwmod_ocp_ifs); +}