drm/i915/lvds: Restore initial HW state during encoder enabling
Atm the LVDS encoder depends on the PPS HW context being saved/restored from generic suspend/resume code. Since the PPS is specific to the LVDS and eDP encoders a cleaner way is to reinitialize it during encoder enabling, so do this here for LVDS. Follow-up patches will init the PPS for the eDP encoder similarly and remove the suspend/resume time save / restore. v2: - Apply BSpec +1 offset and use DIV_ROUND_UP() when programming the power cycle delay. (Ville) v3: (Ville) - Fix +1 vs. round-up order. - s/reset_on_powerdown/powerdown_on_reset/ Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1470827254-21954-3-git-send-email-imre.deak@intel.com
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Imre Deak
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ed6143b8f7
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@ -3710,6 +3710,7 @@ enum {
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#define _PP_ON_DELAYS 0x61208
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#define PP_ON_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_ON_DELAYS)
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#define PANEL_PORT_SELECT_SHIFT 30
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#define PANEL_PORT_SELECT_MASK (3 << 30)
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#define PANEL_PORT_SELECT_LVDS (0 << 30)
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#define PANEL_PORT_SELECT_DPA (1 << 30)
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@ -48,6 +48,20 @@ struct intel_lvds_connector {
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struct notifier_block lid_notifier;
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};
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struct intel_lvds_pps {
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/* 100us units */
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int t1_t2;
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int t3;
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int t4;
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int t5;
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int tx;
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int divider;
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int port;
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bool powerdown_on_reset;
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};
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struct intel_lvds_encoder {
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struct intel_encoder base;
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@ -55,6 +69,9 @@ struct intel_lvds_encoder {
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i915_reg_t reg;
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u32 a3_power;
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struct intel_lvds_pps init_pps;
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u32 init_lvds_val;
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struct intel_lvds_connector *attached_connector;
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};
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@ -136,6 +153,83 @@ static void intel_lvds_get_config(struct intel_encoder *encoder,
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pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
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}
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static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv,
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struct intel_lvds_pps *pps)
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{
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u32 val;
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pps->powerdown_on_reset = I915_READ(PP_CONTROL(0)) & PANEL_POWER_RESET;
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val = I915_READ(PP_ON_DELAYS(0));
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pps->port = (val & PANEL_PORT_SELECT_MASK) >>
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PANEL_PORT_SELECT_SHIFT;
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pps->t1_t2 = (val & PANEL_POWER_UP_DELAY_MASK) >>
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PANEL_POWER_UP_DELAY_SHIFT;
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pps->t5 = (val & PANEL_LIGHT_ON_DELAY_MASK) >>
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PANEL_LIGHT_ON_DELAY_SHIFT;
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val = I915_READ(PP_OFF_DELAYS(0));
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pps->t3 = (val & PANEL_POWER_DOWN_DELAY_MASK) >>
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PANEL_POWER_DOWN_DELAY_SHIFT;
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pps->tx = (val & PANEL_LIGHT_OFF_DELAY_MASK) >>
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PANEL_LIGHT_OFF_DELAY_SHIFT;
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val = I915_READ(PP_DIVISOR(0));
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pps->divider = (val & PP_REFERENCE_DIVIDER_MASK) >>
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PP_REFERENCE_DIVIDER_SHIFT;
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val = (val & PANEL_POWER_CYCLE_DELAY_MASK) >>
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PANEL_POWER_CYCLE_DELAY_SHIFT;
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/*
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* Remove the BSpec specified +1 (100ms) offset that accounts for a
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* too short power-cycle delay due to the asynchronous programming of
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* the register.
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*/
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if (val)
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val--;
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/* Convert from 100ms to 100us units */
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pps->t4 = val * 1000;
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if (INTEL_INFO(dev_priv)->gen <= 4 &&
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pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) {
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DRM_DEBUG_KMS("Panel power timings uninitialized, "
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"setting defaults\n");
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/* Set T2 to 40ms and T5 to 200ms in 100 usec units */
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pps->t1_t2 = 40 * 10;
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pps->t5 = 200 * 10;
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/* Set T3 to 35ms and Tx to 200ms in 100 usec units */
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pps->t3 = 35 * 10;
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pps->tx = 200 * 10;
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}
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DRM_DEBUG_DRIVER("LVDS PPS:t1+t2 %d t3 %d t4 %d t5 %d tx %d "
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"divider %d port %d powerdown_on_reset %d\n",
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pps->t1_t2, pps->t3, pps->t4, pps->t5, pps->tx,
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pps->divider, pps->port, pps->powerdown_on_reset);
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}
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static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv,
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struct intel_lvds_pps *pps)
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{
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u32 val;
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val = I915_READ(PP_CONTROL(0));
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WARN_ON((val & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS);
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if (pps->powerdown_on_reset)
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val |= PANEL_POWER_RESET;
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I915_WRITE(PP_CONTROL(0), val);
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I915_WRITE(PP_ON_DELAYS(0), (pps->port << PANEL_PORT_SELECT_SHIFT) |
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(pps->t1_t2 << PANEL_POWER_UP_DELAY_SHIFT) |
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(pps->t5 << PANEL_LIGHT_ON_DELAY_SHIFT));
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I915_WRITE(PP_OFF_DELAYS(0), (pps->t3 << PANEL_POWER_DOWN_DELAY_SHIFT) |
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(pps->tx << PANEL_LIGHT_OFF_DELAY_SHIFT));
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val = pps->divider << PP_REFERENCE_DIVIDER_SHIFT;
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val |= (DIV_ROUND_UP(pps->t4, 1000) + 1) <<
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PANEL_POWER_CYCLE_DELAY_SHIFT;
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I915_WRITE(PP_DIVISOR(0), val);
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}
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static void intel_pre_enable_lvds(struct intel_encoder *encoder)
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{
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struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
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@ -154,7 +248,9 @@ static void intel_pre_enable_lvds(struct intel_encoder *encoder)
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assert_pll_disabled(dev_priv, pipe);
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}
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temp = I915_READ(lvds_encoder->reg);
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intel_lvds_pps_init_hw(dev_priv, &lvds_encoder->init_pps);
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temp = lvds_encoder->init_lvds_val;
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temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
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if (HAS_PCH_CPT(dev)) {
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@ -922,18 +1018,6 @@ void intel_lvds_init(struct drm_device *dev)
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DRM_DEBUG_KMS("LVDS is not present in VBT, but enabled anyway\n");
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}
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/* Set the Panel Power On/Off timings if uninitialized. */
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if (INTEL_INFO(dev_priv)->gen < 5 &&
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I915_READ(PP_ON_DELAYS(0)) == 0 && I915_READ(PP_OFF_DELAYS(0)) == 0) {
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/* Set T2 to 40ms and T5 to 200ms */
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I915_WRITE(PP_ON_DELAYS(0), 0x019007d0);
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/* Set T3 to 35ms and Tx to 200ms */
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I915_WRITE(PP_OFF_DELAYS(0), 0x015e07d0);
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DRM_DEBUG_KMS("Panel power timings uninitialized, setting defaults\n");
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}
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lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL);
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if (!lvds_encoder)
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return;
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@ -999,6 +1083,10 @@ void intel_lvds_init(struct drm_device *dev)
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dev->mode_config.scaling_mode_property,
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DRM_MODE_SCALE_ASPECT);
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intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
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intel_lvds_pps_get_hw_state(dev_priv, &lvds_encoder->init_pps);
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lvds_encoder->init_lvds_val = lvds;
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/*
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* LVDS discovery:
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* 1) check for EDID on DDC
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