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[POWERPC] Fix IPIC pending register assignments 

This patch fixes the assignment of pending registers to IRQ numbers for
the IPIC; the code previously assigned all IRQs to the high pending word
regardless of which word the interrupt belonged to.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Scott Wood 2006-09-21 13:10:51 -05:00 коммит произвёл Paul Mackerras
Родитель 7d452c326c
Коммит ed709d134d
1 изменённых файлов: 21 добавлений и 21 удалений
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42
arch/powerpc/sysdev/ipic.c
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@ -210,7 +210,7 @@ static struct ipic_info ipic_info[] = {
.prio_mask = 4, .prio_mask = 4,
}, },
[64] = { [64] = {
.pend = IPIC_SIPNR_H, .pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L, .mask = IPIC_SIMSR_L,
.prio = IPIC_SMPRR_A, .prio = IPIC_SMPRR_A,
.force = IPIC_SIFCR_L, .force = IPIC_SIFCR_L,
@ -218,7 +218,7 @@ static struct ipic_info ipic_info[] = {
.prio_mask = 0, .prio_mask = 0,
}, },
[65] = { [65] = {
.pend = IPIC_SIPNR_H, .pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L, .mask = IPIC_SIMSR_L,
.prio = IPIC_SMPRR_A, .prio = IPIC_SMPRR_A,
.force = IPIC_SIFCR_L, .force = IPIC_SIFCR_L,
@ -226,7 +226,7 @@ static struct ipic_info ipic_info[] = {
.prio_mask = 1, .prio_mask = 1,
}, },
[66] = { [66] = {
.pend = IPIC_SIPNR_H, .pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L, .mask = IPIC_SIMSR_L,
.prio = IPIC_SMPRR_A, .prio = IPIC_SMPRR_A,
.force = IPIC_SIFCR_L, .force = IPIC_SIFCR_L,
@ -234,7 +234,7 @@ static struct ipic_info ipic_info[] = {
.prio_mask = 2, .prio_mask = 2,
}, },
[67] = { [67] = {
.pend = IPIC_SIPNR_H, .pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L, .mask = IPIC_SIMSR_L,
.prio = IPIC_SMPRR_A, .prio = IPIC_SMPRR_A,
.force = IPIC_SIFCR_L, .force = IPIC_SIFCR_L,
@ -242,7 +242,7 @@ static struct ipic_info ipic_info[] = {
.prio_mask = 3, .prio_mask = 3,
}, },
[68] = { [68] = {
.pend = IPIC_SIPNR_H, .pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L, .mask = IPIC_SIMSR_L,
.prio = IPIC_SMPRR_B, .prio = IPIC_SMPRR_B,
.force = IPIC_SIFCR_L, .force = IPIC_SIFCR_L,
@ -250,7 +250,7 @@ static struct ipic_info ipic_info[] = {
.prio_mask = 0, .prio_mask = 0,
}, },
[69] = { [69] = {
.pend = IPIC_SIPNR_H, .pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L, .mask = IPIC_SIMSR_L,
.prio = IPIC_SMPRR_B, .prio = IPIC_SMPRR_B,
.force = IPIC_SIFCR_L, .force = IPIC_SIFCR_L,
@ -258,7 +258,7 @@ static struct ipic_info ipic_info[] = {
.prio_mask = 1, .prio_mask = 1,
}, },
[70] = { [70] = {
.pend = IPIC_SIPNR_H, .pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L, .mask = IPIC_SIMSR_L,
.prio = IPIC_SMPRR_B, .prio = IPIC_SMPRR_B,
.force = IPIC_SIFCR_L, .force = IPIC_SIFCR_L,
@ -266,7 +266,7 @@ static struct ipic_info ipic_info[] = {
.prio_mask = 2, .prio_mask = 2,
}, },
[71] = { [71] = {
.pend = IPIC_SIPNR_H, .pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L, .mask = IPIC_SIMSR_L,
.prio = IPIC_SMPRR_B, .prio = IPIC_SMPRR_B,
.force = IPIC_SIFCR_L, .force = IPIC_SIFCR_L,
@ -274,91 +274,91 @@ static struct ipic_info ipic_info[] = {
.prio_mask = 3, .prio_mask = 3,
}, },
[72] = { [72] = {
.pend = IPIC_SIPNR_H, .pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L, .mask = IPIC_SIMSR_L,
.prio = 0, .prio = 0,
.force = IPIC_SIFCR_L, .force = IPIC_SIFCR_L,
.bit = 8, .bit = 8,
}, },
[73] = { [73] = {
.pend = IPIC_SIPNR_H, .pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L, .mask = IPIC_SIMSR_L,
.prio = 0, .prio = 0,
.force = IPIC_SIFCR_L, .force = IPIC_SIFCR_L,
.bit = 9, .bit = 9,
}, },
[74] = { [74] = {
.pend = IPIC_SIPNR_H, .pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L, .mask = IPIC_SIMSR_L,
.prio = 0, .prio = 0,
.force = IPIC_SIFCR_L, .force = IPIC_SIFCR_L,
.bit = 10, .bit = 10,
}, },
[75] = { [75] = {
.pend = IPIC_SIPNR_H, .pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L, .mask = IPIC_SIMSR_L,
.prio = 0, .prio = 0,
.force = IPIC_SIFCR_L, .force = IPIC_SIFCR_L,
.bit = 11, .bit = 11,
}, },
[76] = { [76] = {
.pend = IPIC_SIPNR_H, .pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L, .mask = IPIC_SIMSR_L,
.prio = 0, .prio = 0,
.force = IPIC_SIFCR_L, .force = IPIC_SIFCR_L,
.bit = 12, .bit = 12,
}, },
[77] = { [77] = {
.pend = IPIC_SIPNR_H, .pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L, .mask = IPIC_SIMSR_L,
.prio = 0, .prio = 0,
.force = IPIC_SIFCR_L, .force = IPIC_SIFCR_L,
.bit = 13, .bit = 13,
}, },
[78] = { [78] = {
.pend = IPIC_SIPNR_H, .pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L, .mask = IPIC_SIMSR_L,
.prio = 0, .prio = 0,
.force = IPIC_SIFCR_L, .force = IPIC_SIFCR_L,
.bit = 14, .bit = 14,
}, },
[79] = { [79] = {
.pend = IPIC_SIPNR_H, .pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L, .mask = IPIC_SIMSR_L,
.prio = 0, .prio = 0,
.force = IPIC_SIFCR_L, .force = IPIC_SIFCR_L,
.bit = 15, .bit = 15,
}, },
[80] = { [80] = {
.pend = IPIC_SIPNR_H, .pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L, .mask = IPIC_SIMSR_L,
.prio = 0, .prio = 0,
.force = IPIC_SIFCR_L, .force = IPIC_SIFCR_L,
.bit = 16, .bit = 16,
}, },
[84] = { [84] = {
.pend = IPIC_SIPNR_H, .pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L, .mask = IPIC_SIMSR_L,
.prio = 0, .prio = 0,
.force = IPIC_SIFCR_L, .force = IPIC_SIFCR_L,
.bit = 20, .bit = 20,
}, },
[85] = { [85] = {
.pend = IPIC_SIPNR_H, .pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L, .mask = IPIC_SIMSR_L,
.prio = 0, .prio = 0,
.force = IPIC_SIFCR_L, .force = IPIC_SIFCR_L,
.bit = 21, .bit = 21,
}, },
[90] = { [90] = {
.pend = IPIC_SIPNR_H, .pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L, .mask = IPIC_SIMSR_L,
.prio = 0, .prio = 0,
.force = IPIC_SIFCR_L, .force = IPIC_SIFCR_L,
.bit = 26, .bit = 26,
}, },
[91] = { [91] = {
.pend = IPIC_SIPNR_H, .pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L, .mask = IPIC_SIMSR_L,
.prio = 0, .prio = 0,
.force = IPIC_SIFCR_L, .force = IPIC_SIFCR_L,