PCI: qcom: Add support for SDM845 PCIe controller
The SDM845 has one Gen2 and one Gen3 controller, add support for these. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Andrew Murray <andrew.murray@arm.com> Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
This commit is contained in:
Bjorn Andersson
Lorenzo Pieralisi
Родитель
5d28bee7c9
Коммит
ed8cc3b1fc
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@ -54,6 +54,7 @@
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#define PCIE20_PARF_LTSSM 0x1B0
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#define PCIE20_PARF_SID_OFFSET 0x234
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#define PCIE20_PARF_BDF_TRANSLATE_CFG 0x24C
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#define PCIE20_PARF_DEVICE_TYPE 0x1000
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#define PCIE20_ELBI_SYS_CTRL 0x04
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#define PCIE20_ELBI_SYS_CTRL_LT_ENABLE BIT(0)
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@ -80,6 +81,8 @@
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#define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358
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#define SLV_ADDR_SPACE_SZ 0x10000000
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#define DEVICE_TYPE_RC 0x4
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#define QCOM_PCIE_2_1_0_MAX_SUPPLY 3
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struct qcom_pcie_resources_2_1_0 {
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struct clk *iface_clk;
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@ -139,12 +142,20 @@ struct qcom_pcie_resources_2_3_3 {
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struct reset_control *rst[7];
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};
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struct qcom_pcie_resources_2_7_0 {
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struct clk_bulk_data clks[6];
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struct regulator_bulk_data supplies[2];
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struct reset_control *pci_reset;
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struct clk *pipe_clk;
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};
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union qcom_pcie_resources {
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struct qcom_pcie_resources_1_0_0 v1_0_0;
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struct qcom_pcie_resources_2_1_0 v2_1_0;
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struct qcom_pcie_resources_2_3_2 v2_3_2;
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struct qcom_pcie_resources_2_3_3 v2_3_3;
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struct qcom_pcie_resources_2_4_0 v2_4_0;
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struct qcom_pcie_resources_2_7_0 v2_7_0;
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};
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struct qcom_pcie;
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@ -1068,6 +1079,134 @@ err_clk_iface:
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return ret;
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}
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static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)
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{
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struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
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struct dw_pcie *pci = pcie->pci;
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struct device *dev = pci->dev;
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int ret;
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res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
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if (IS_ERR(res->pci_reset))
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return PTR_ERR(res->pci_reset);
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res->supplies[0].supply = "vdda";
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res->supplies[1].supply = "vddpe-3v3";
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ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies),
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res->supplies);
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if (ret)
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return ret;
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res->clks[0].id = "aux";
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res->clks[1].id = "cfg";
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res->clks[2].id = "bus_master";
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res->clks[3].id = "bus_slave";
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res->clks[4].id = "slave_q2a";
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res->clks[5].id = "tbu";
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ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks);
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if (ret < 0)
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return ret;
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res->pipe_clk = devm_clk_get(dev, "pipe");
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return PTR_ERR_OR_ZERO(res->pipe_clk);
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}
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static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
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{
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struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
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struct dw_pcie *pci = pcie->pci;
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struct device *dev = pci->dev;
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u32 val;
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int ret;
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ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);
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if (ret < 0) {
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dev_err(dev, "cannot enable regulators\n");
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return ret;
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}
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ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
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if (ret < 0)
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goto err_disable_regulators;
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ret = reset_control_assert(res->pci_reset);
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if (ret < 0) {
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dev_err(dev, "cannot deassert pci reset\n");
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goto err_disable_clocks;
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}
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usleep_range(1000, 1500);
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ret = reset_control_deassert(res->pci_reset);
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if (ret < 0) {
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dev_err(dev, "cannot deassert pci reset\n");
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goto err_disable_clocks;
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}
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ret = clk_prepare_enable(res->pipe_clk);
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if (ret) {
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dev_err(dev, "cannot prepare/enable pipe clock\n");
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goto err_disable_clocks;
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}
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/* configure PCIe to RC mode */
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writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE);
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/* enable PCIe clocks and resets */
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val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
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val &= ~BIT(0);
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writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
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/* change DBI base address */
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writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
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/* MAC PHY_POWERDOWN MUX DISABLE */
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val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL);
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val &= ~BIT(29);
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writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL);
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val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
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val |= BIT(4);
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writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
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if (IS_ENABLED(CONFIG_PCI_MSI)) {
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val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
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val |= BIT(31);
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writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
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}
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return 0;
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err_disable_clocks:
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clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
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err_disable_regulators:
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regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
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return ret;
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}
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static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie)
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{
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struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
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clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
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regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
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}
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static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie)
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{
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struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
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return clk_prepare_enable(res->pipe_clk);
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}
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static void qcom_pcie_post_deinit_2_7_0(struct qcom_pcie *pcie)
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{
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struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
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clk_disable_unprepare(res->pipe_clk);
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}
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static int qcom_pcie_link_up(struct dw_pcie *pci)
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{
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u16 val = readw(pci->dbi_base + PCIE20_CAP + PCI_EXP_LNKSTA);
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@ -1167,6 +1306,16 @@ static const struct qcom_pcie_ops ops_2_3_3 = {
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.ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
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};
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/* Qcom IP rev.: 2.7.0 Synopsys IP rev.: 4.30a */
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static const struct qcom_pcie_ops ops_2_7_0 = {
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.get_resources = qcom_pcie_get_resources_2_7_0,
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.init = qcom_pcie_init_2_7_0,
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.deinit = qcom_pcie_deinit_2_7_0,
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.ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
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.post_init = qcom_pcie_post_init_2_7_0,
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.post_deinit = qcom_pcie_post_deinit_2_7_0,
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};
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static const struct dw_pcie_ops dw_pcie_ops = {
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.link_up = qcom_pcie_link_up,
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};
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@ -1282,6 +1431,7 @@ static const struct of_device_id qcom_pcie_match[] = {
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{ .compatible = "qcom,pcie-ipq8074", .data = &ops_2_3_3 },
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{ .compatible = "qcom,pcie-ipq4019", .data = &ops_2_4_0 },
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{ .compatible = "qcom,pcie-qcs404", .data = &ops_2_4_0 },
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{ .compatible = "qcom,pcie-sdm845", .data = &ops_2_7_0 },
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{ }
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};
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