ARM64: SoC changes for 3.19
This adds support for two new ARM64 platforms: * ARM Juno * AMD Seattle We had submissions for a number of additional platforms from Samsung, Freescale and Spreadtrum but are still working out the best process for getting these merged. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIVAwUAVIcj62CrR//JCVInAQKv9w/+LXBBfJbNetHE17PoeV10O+ni6a3Xuv7F ZIkx+GgxEYT/8JPBeORUs0Boa6llpsUpn+GqCuqhMmFAPImxoQJ1ULmf6SFfbppB b7FRNoaW5GPUsi6mDfat4w3yXZK3LX0qlPprym1d9yGOXN9hnH8LkvnSsqZM1Ntn 4jnj7nQJyn/BG5OyFDWnTsyO7dIYMLm90s/VnVPxu7VGacDEnhAXdvqQkzkmavTK K9zOBYa4vGhfYM7Wy/3xQrJfHTZOkLOQh4TGwfCQjDoFxvhCXrDo7fU+TKdawq10 KGHbxj8rhCaAUhc0Gqn77/Cri3LXGJyw+97VZeh9KWR1a1YAV5nsCvz3sZuQY78J qbTOwMq9xQ3nQnerkmGPeGV/UyouvdxO/SnOyZnTU0OaYJlFIbsdu8mIUH4xHkGm +7DceBhuDk+iVgDtULKpz0RA4XNsUV81Cb6FyVgmEcnuThRtCDetrN7RpMKmqynA ZQ/VM/0qtnzQp+XYIxJf7A6iexVtJp00Yffw7y0F8QaoBCwWEsPA1TMk4wPirCYn tsQ9C0jYKAWAI8scYpThiTOK8IoBvDIv5OMoxqwtvr4RZQqO9CZQcgtlHOAYNMtX zhh+r/1B27vFXoGva065AKIyGPbQSeUJesfVxwN9+RbWplWusaqLPuwfbyNttacf mkkNrudQ9g4= =yqur -----END PGP SIGNATURE----- Merge tag 'arm64-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM64 SoC changes from Arnd Bergmann: "This adds support for two new ARM64 platforms: - ARM Juno - AMD Seattle We had submissions for a number of additional platforms from Samsung, Freescale and Spreadtrum but are still working out the best process for getting these merged" * tag 'arm64-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: arm64: amd-seattle: Fix PCI bus range due to SMMU limitation arm64: ARM: Fix the Generic Timers interrupt active level description arm64: amd-seattle: Adding device tree for AMD Seattle platform arm64: Add Juno board device tree. arm64: Create link to include/dt-bindings to enable C preprocessor use.
This commit is contained in:
Linus Torvalds
Коммит
ed8efd2de7
|
|
@ -145,6 +145,11 @@ source "kernel/Kconfig.freezer"
|
|||
|
||||
menu "Platform selection"
|
||||
|
||||
config ARCH_SEATTLE
|
||||
bool "AMD Seattle SoC Family"
|
||||
help
|
||||
This enables support for AMD Seattle SOC Family
|
||||
|
||||
config ARCH_THUNDER
|
||||
bool "Cavium Inc. Thunder SoC Family"
|
||||
help
|
||||
|
|
|
|||
|
|
@ -1,3 +1,4 @@
|
|||
dts-dirs += amd
|
||||
dts-dirs += apm
|
||||
dts-dirs += arm
|
||||
dts-dirs += cavium
|
||||
|
|
|
|||
|
|
@ -0,0 +1,5 @@
|
|||
dtb-$(CONFIG_ARCH_SEATTLE) += amd-overdrive.dtb
|
||||
|
||||
always := $(dtb-y)
|
||||
subdir-y := $(dts-dirs)
|
||||
clean-files := *.dtb
|
||||
|
|
@ -0,0 +1,66 @@
|
|||
/*
|
||||
* DTS file for AMD Seattle Overdrive Development Board
|
||||
*
|
||||
* Copyright (C) 2014 Advanced Micro Devices, Inc.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "amd-seattle-soc.dtsi"
|
||||
|
||||
/ {
|
||||
model = "AMD Seattle Development Board (Overdrive)";
|
||||
compatible = "amd,seattle-overdrive", "amd,seattle";
|
||||
|
||||
chosen {
|
||||
stdout-path = &serial0;
|
||||
linux,pci-probe-only;
|
||||
};
|
||||
};
|
||||
|
||||
&ccp0 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
status = "ok";
|
||||
sdcard0: sdcard@0 {
|
||||
compatible = "mmc-spi-slot";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <20000000>;
|
||||
voltage-ranges = <3200 3400>;
|
||||
gpios = <&gpio0 7 0>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <7 3>;
|
||||
pl022,hierarchy = <0>;
|
||||
pl022,interface = <0>;
|
||||
pl022,com-mode = <0x0>;
|
||||
pl022,rx-level-trig = <0>;
|
||||
pl022,tx-level-trig = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&v2m0 {
|
||||
arm,msi-base-spi = <64>;
|
||||
arm,msi-num-spis = <256>;
|
||||
};
|
||||
|
|
@ -0,0 +1,54 @@
|
|||
/*
|
||||
* DTS file for AMD Seattle Clocks
|
||||
*
|
||||
* Copyright (C) 2014 Advanced Micro Devices, Inc.
|
||||
*/
|
||||
|
||||
adl3clk_100mhz: clk100mhz_0 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <100000000>;
|
||||
clock-output-names = "adl3clk_100mhz";
|
||||
};
|
||||
|
||||
ccpclk_375mhz: clk375mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <375000000>;
|
||||
clock-output-names = "ccpclk_375mhz";
|
||||
};
|
||||
|
||||
sataclk_333mhz: clk333mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <333000000>;
|
||||
clock-output-names = "sataclk_333mhz";
|
||||
};
|
||||
|
||||
pcieclk_500mhz: clk500mhz_0 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <500000000>;
|
||||
clock-output-names = "pcieclk_500mhz";
|
||||
};
|
||||
|
||||
dmaclk_500mhz: clk500mhz_1 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <500000000>;
|
||||
clock-output-names = "dmaclk_500mhz";
|
||||
};
|
||||
|
||||
miscclk_250mhz: clk250mhz_4 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <250000000>;
|
||||
clock-output-names = "miscclk_250mhz";
|
||||
};
|
||||
|
||||
uartspiclk_100mhz: clk100mhz_1 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <100000000>;
|
||||
clock-output-names = "uartspiclk_100mhz";
|
||||
};
|
||||
|
|
@ -0,0 +1,172 @@
|
|||
/*
|
||||
* DTS file for AMD Seattle SoC
|
||||
*
|
||||
* Copyright (C) 2014 Advanced Micro Devices, Inc.
|
||||
*/
|
||||
|
||||
/ {
|
||||
compatible = "amd,seattle";
|
||||
interrupt-parent = <&gic0>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
gic0: interrupt-controller@e1101000 {
|
||||
compatible = "arm,gic-400", "arm,cortex-a15-gic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
reg = <0x0 0xe1110000 0 0x1000>,
|
||||
<0x0 0xe112f000 0 0x2000>,
|
||||
<0x0 0xe1140000 0 0x10000>,
|
||||
<0x0 0xe1160000 0 0x10000>;
|
||||
interrupts = <1 9 0xf04>;
|
||||
ranges = <0 0 0 0xe1100000 0 0x100000>;
|
||||
v2m0: v2m@e0080000 {
|
||||
compatible = "arm,gic-v2m-frame";
|
||||
msi-controller;
|
||||
reg = <0x0 0x00080000 0 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <1 13 0xff04>,
|
||||
<1 14 0xff04>,
|
||||
<1 11 0xff04>,
|
||||
<1 10 0xff04>;
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,armv8-pmuv3";
|
||||
interrupts = <0 7 4>,
|
||||
<0 8 4>,
|
||||
<0 9 4>,
|
||||
<0 10 4>,
|
||||
<0 11 4>,
|
||||
<0 12 4>,
|
||||
<0 13 4>,
|
||||
<0 14 4>;
|
||||
};
|
||||
|
||||
smb0: smb {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
/* DDR range is 40-bit addressing */
|
||||
dma-ranges = <0x80 0x0 0x80 0x0 0x7f 0xffffffff>;
|
||||
|
||||
/include/ "amd-seattle-clks.dtsi"
|
||||
|
||||
sata0: sata@e0300000 {
|
||||
compatible = "snps,dwc-ahci";
|
||||
reg = <0 0xe0300000 0 0x800>;
|
||||
interrupts = <0 355 4>;
|
||||
clocks = <&sataclk_333mhz>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
i2c0: i2c@e1000000 {
|
||||
status = "disabled";
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0 0xe1000000 0 0x1000>;
|
||||
interrupts = <0 357 4>;
|
||||
clocks = <&uartspiclk_100mhz>;
|
||||
};
|
||||
|
||||
serial0: serial@e1010000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0 0xe1010000 0 0x1000>;
|
||||
interrupts = <0 328 4>;
|
||||
clocks = <&uartspiclk_100mhz>, <&uartspiclk_100mhz>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
spi0: ssp@e1020000 {
|
||||
status = "disabled";
|
||||
compatible = "arm,pl022", "arm,primecell";
|
||||
#gpio-cells = <2>;
|
||||
reg = <0 0xe1020000 0 0x1000>;
|
||||
spi-controller;
|
||||
interrupts = <0 330 4>;
|
||||
clocks = <&uartspiclk_100mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
spi1: ssp@e1030000 {
|
||||
status = "disabled";
|
||||
compatible = "arm,pl022", "arm,primecell";
|
||||
#gpio-cells = <2>;
|
||||
reg = <0 0xe1030000 0 0x1000>;
|
||||
spi-controller;
|
||||
interrupts = <0 329 4>;
|
||||
clocks = <&uartspiclk_100mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
num-cs = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
gpio0: gpio@e1040000 {
|
||||
status = "disabled";
|
||||
compatible = "arm,pl061", "arm,primecell";
|
||||
#gpio-cells = <2>;
|
||||
reg = <0 0xe1040000 0 0x1000>;
|
||||
gpio-controller;
|
||||
interrupts = <0 359 4>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&uartspiclk_100mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
gpio1: gpio@e1050000 {
|
||||
status = "disabled";
|
||||
compatible = "arm,pl061", "arm,primecell";
|
||||
#gpio-cells = <2>;
|
||||
reg = <0 0xe1050000 0 0x1000>;
|
||||
gpio-controller;
|
||||
interrupts = <0 358 4>;
|
||||
clocks = <&uartspiclk_100mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
ccp0: ccp@e0100000 {
|
||||
status = "disabled";
|
||||
compatible = "amd,ccp-seattle-v1a";
|
||||
reg = <0 0xe0100000 0 0x10000>;
|
||||
interrupts = <0 3 4>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
pcie0: pcie@f0000000 {
|
||||
compatible = "pci-host-ecam-generic";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
device_type = "pci";
|
||||
bus-range = <0 0x7f>;
|
||||
msi-parent = <&v2m0>;
|
||||
reg = <0 0xf0000000 0 0x10000000>;
|
||||
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map =
|
||||
<0x1000 0x0 0x0 0x1 &gic0 0x0 0x0 0x0 0x120 0x1>,
|
||||
<0x1000 0x0 0x0 0x2 &gic0 0x0 0x0 0x0 0x121 0x1>,
|
||||
<0x1000 0x0 0x0 0x3 &gic0 0x0 0x0 0x0 0x122 0x1>,
|
||||
<0x1000 0x0 0x0 0x4 &gic0 0x0 0x0 0x0 0x123 0x1>;
|
||||
|
||||
dma-coherent;
|
||||
dma-ranges = <0x43000000 0x80 0x0 0x80 0x0 0x7f 0xffffffff>;
|
||||
ranges =
|
||||
/* I/O Memory (size=64K) */
|
||||
<0x01000000 0x00 0x00000000 0x00 0xefff0000 0x00 0x00010000>,
|
||||
/* 32-bit MMIO (size=2G) */
|
||||
<0x02000000 0x00 0x40000000 0x00 0x40000000 0x00 0x80000000>,
|
||||
/* 64-bit MMIO (size= 124G) */
|
||||
<0x03000000 0x01 0x00000000 0x01 0x00000000 0x7f 0x00000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -1,4 +1,5 @@
|
|||
dtb-$(CONFIG_ARCH_VEXPRESS) += foundation-v8.dtb
|
||||
dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb
|
||||
dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb
|
||||
|
||||
always := $(dtb-y)
|
||||
|
|
|
|||
|
|
@ -78,10 +78,10 @@
|
|||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <1 13 0xff01>,
|
||||
<1 14 0xff01>,
|
||||
<1 11 0xff01>,
|
||||
<1 10 0xff01>;
|
||||
interrupts = <1 13 0xf08>,
|
||||
<1 14 0xf08>,
|
||||
<1 11 0xf08>,
|
||||
<1 10 0xf08>;
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,44 @@
|
|||
/*
|
||||
* ARM Juno Platform clocks
|
||||
*
|
||||
* Copyright (c) 2013-2014 ARM Ltd
|
||||
*
|
||||
* This file is licensed under a dual GPLv2 or BSD license.
|
||||
*
|
||||
*/
|
||||
|
||||
/* SoC fixed clocks */
|
||||
soc_uartclk: refclk72738khz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <7273800>;
|
||||
clock-output-names = "juno:uartclk";
|
||||
};
|
||||
|
||||
soc_usb48mhz: clk48mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <48000000>;
|
||||
clock-output-names = "clk48mhz";
|
||||
};
|
||||
|
||||
soc_smc50mhz: clk50mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <50000000>;
|
||||
clock-output-names = "smc_clk";
|
||||
};
|
||||
|
||||
soc_refclk100mhz: refclk100mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <100000000>;
|
||||
clock-output-names = "apb_pclk";
|
||||
};
|
||||
|
||||
soc_faxiclk: refclk533mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <533000000>;
|
||||
clock-output-names = "faxi_clk";
|
||||
};
|
||||
|
|
@ -0,0 +1,129 @@
|
|||
/*
|
||||
* ARM Juno Platform motherboard peripherals
|
||||
*
|
||||
* Copyright (c) 2013-2014 ARM Ltd
|
||||
*
|
||||
* This file is licensed under a dual GPLv2 or BSD license.
|
||||
*
|
||||
*/
|
||||
|
||||
mb_clk24mhz: clk24mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
clock-output-names = "juno_mb:clk24mhz";
|
||||
};
|
||||
|
||||
mb_clk25mhz: clk25mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <25000000>;
|
||||
clock-output-names = "juno_mb:clk25mhz";
|
||||
};
|
||||
|
||||
motherboard {
|
||||
compatible = "arm,vexpress,v2p-p1", "simple-bus";
|
||||
#address-cells = <2>; /* SMB chipselect number and offset */
|
||||
#size-cells = <1>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
model = "V2M-Juno";
|
||||
arm,hbi = <0x252>;
|
||||
arm,vexpress,site = <0>;
|
||||
arm,v2m-memory-map = "rs1";
|
||||
|
||||
mb_fixed_3v3: fixedregulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "MCC_SB_3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ethernet@2,00000000 {
|
||||
compatible = "smsc,lan9118", "smsc,lan9115";
|
||||
reg = <2 0x00000000 0x10000>;
|
||||
interrupts = <3>;
|
||||
phy-mode = "mii";
|
||||
reg-io-width = <4>;
|
||||
smsc,irq-active-high;
|
||||
smsc,irq-push-pull;
|
||||
clocks = <&mb_clk25mhz>;
|
||||
vdd33a-supply = <&mb_fixed_3v3>;
|
||||
vddvario-supply = <&mb_fixed_3v3>;
|
||||
};
|
||||
|
||||
usb@5,00000000 {
|
||||
compatible = "nxp,usb-isp1763";
|
||||
reg = <5 0x00000000 0x20000>;
|
||||
bus-width = <16>;
|
||||
interrupts = <4>;
|
||||
};
|
||||
|
||||
iofpga@3,00000000 {
|
||||
compatible = "arm,amba-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 3 0 0x200000>;
|
||||
|
||||
mmci@050000 {
|
||||
compatible = "arm,pl180", "arm,primecell";
|
||||
reg = <0x050000 0x1000>;
|
||||
interrupts = <5>;
|
||||
/* cd-gpios = <&v2m_mmc_gpios 0 0>;
|
||||
wp-gpios = <&v2m_mmc_gpios 1 0>; */
|
||||
max-frequency = <12000000>;
|
||||
vmmc-supply = <&mb_fixed_3v3>;
|
||||
clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
|
||||
clock-names = "mclk", "apb_pclk";
|
||||
};
|
||||
|
||||
kmi@060000 {
|
||||
compatible = "arm,pl050", "arm,primecell";
|
||||
reg = <0x060000 0x1000>;
|
||||
interrupts = <8>;
|
||||
clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
|
||||
clock-names = "KMIREFCLK", "apb_pclk";
|
||||
};
|
||||
|
||||
kmi@070000 {
|
||||
compatible = "arm,pl050", "arm,primecell";
|
||||
reg = <0x070000 0x1000>;
|
||||
interrupts = <8>;
|
||||
clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
|
||||
clock-names = "KMIREFCLK", "apb_pclk";
|
||||
};
|
||||
|
||||
wdt@0f0000 {
|
||||
compatible = "arm,sp805", "arm,primecell";
|
||||
reg = <0x0f0000 0x10000>;
|
||||
interrupts = <7>;
|
||||
clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
|
||||
clock-names = "wdogclk", "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_timer01: timer@110000 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0x110000 0x10000>;
|
||||
interrupts = <9>;
|
||||
clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
|
||||
clock-names = "timclken1", "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_timer23: timer@120000 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0x120000 0x10000>;
|
||||
interrupts = <9>;
|
||||
clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
|
||||
clock-names = "timclken1", "apb_pclk";
|
||||
};
|
||||
|
||||
rtc@170000 {
|
||||
compatible = "arm,pl031", "arm,primecell";
|
||||
reg = <0x170000 0x10000>;
|
||||
interrupts = <0>;
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,218 @@
|
|||
/*
|
||||
* ARM Ltd. Juno Platform
|
||||
*
|
||||
* Copyright (c) 2013-2014 ARM Ltd.
|
||||
*
|
||||
* This file is licensed under a dual GPLv2 or BSD license.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/ {
|
||||
model = "ARM Juno development board (r0)";
|
||||
compatible = "arm,juno", "arm,vexpress";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
serial0 = &soc_uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = &soc_uart0;
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-0.2";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
A57_0: cpu@0 {
|
||||
compatible = "arm,cortex-a57","arm,armv8";
|
||||
reg = <0x0 0x0>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
A57_1: cpu@1 {
|
||||
compatible = "arm,cortex-a57","arm,armv8";
|
||||
reg = <0x0 0x1>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
A53_0: cpu@100 {
|
||||
compatible = "arm,cortex-a53","arm,armv8";
|
||||
reg = <0x0 0x100>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
A53_1: cpu@101 {
|
||||
compatible = "arm,cortex-a53","arm,armv8";
|
||||
reg = <0x0 0x101>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
A53_2: cpu@102 {
|
||||
compatible = "arm,cortex-a53","arm,armv8";
|
||||
reg = <0x0 0x102>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
A53_3: cpu@103 {
|
||||
compatible = "arm,cortex-a53","arm,armv8";
|
||||
reg = <0x0 0x103>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
};
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
/* last 16MB of the first memory area is reserved for secure world use by firmware */
|
||||
reg = <0x00000000 0x80000000 0x0 0x7f000000>,
|
||||
<0x00000008 0x80000000 0x1 0x80000000>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@2c001000 {
|
||||
compatible = "arm,gic-400", "arm,cortex-a15-gic";
|
||||
reg = <0x0 0x2c010000 0 0x1000>,
|
||||
<0x0 0x2c02f000 0 0x2000>,
|
||||
<0x0 0x2c04f000 0 0x2000>,
|
||||
<0x0 0x2c06f000 0 0x2000>;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,armv8-pmuv3";
|
||||
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
/include/ "juno-clocks.dtsi"
|
||||
|
||||
dma@7ff00000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x0 0x7ff00000 0 0x1000>;
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <32>;
|
||||
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&soc_faxiclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
soc_uart0: uart@7ff80000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x0 0x7ff80000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
i2c@7ffa0000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0x0 0x7ffa0000 0x0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <400000>;
|
||||
i2c-sda-hold-time-ns = <500>;
|
||||
clocks = <&soc_smc50mhz>;
|
||||
|
||||
dvi0: dvi-transmitter@70 {
|
||||
compatible = "nxp,tda998x";
|
||||
reg = <0x70>;
|
||||
};
|
||||
|
||||
dvi1: dvi-transmitter@71 {
|
||||
compatible = "nxp,tda998x";
|
||||
reg = <0x71>;
|
||||
};
|
||||
};
|
||||
|
||||
ohci@7ffb0000 {
|
||||
compatible = "generic-ohci";
|
||||
reg = <0x0 0x7ffb0000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&soc_usb48mhz>;
|
||||
};
|
||||
|
||||
ehci@7ffc0000 {
|
||||
compatible = "generic-ehci";
|
||||
reg = <0x0 0x7ffc0000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&soc_usb48mhz>;
|
||||
};
|
||||
|
||||
memory-controller@7ffd0000 {
|
||||
compatible = "arm,pl354", "arm,primecell";
|
||||
reg = <0 0x7ffd0000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
smb {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0 0x08000000 0x04000000>,
|
||||
<1 0 0 0x14000000 0x04000000>,
|
||||
<2 0 0 0x18000000 0x04000000>,
|
||||
<3 0 0 0x1c000000 0x04000000>,
|
||||
<4 0 0 0x0c000000 0x04000000>,
|
||||
<5 0 0 0x10000000 0x04000000>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 15>;
|
||||
interrupt-map = <0 0 0 &gic 0 68 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 1 &gic 0 69 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 2 &gic 0 70 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 3 &gic 0 160 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 4 &gic 0 161 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 5 &gic 0 162 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 6 &gic 0 163 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 7 &gic 0 164 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 8 &gic 0 165 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 9 &gic 0 166 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 10 &gic 0 167 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 11 &gic 0 168 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 12 &gic 0 169 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
/include/ "juno-motherboard.dtsi"
|
||||
};
|
||||
};
|
||||
|
|
@ -81,10 +81,10 @@
|
|||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <1 13 0xff01>,
|
||||
<1 14 0xff01>,
|
||||
<1 11 0xff01>,
|
||||
<1 10 0xff01>;
|
||||
interrupts = <1 13 0xf08>,
|
||||
<1 14 0xf08>,
|
||||
<1 11 0xf08>,
|
||||
<1 10 0xf08>;
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1 @@
|
|||
../../../../../include/dt-bindings
|
||||
Загрузка…
Ссылка в новой задаче