mmc: mmci: Initial support to manage variant specific callbacks
To be able to better support different mmci variants, we need to be able to use variant specific callbacks, rather than continue to sprinkle the code with additional variant data. To move in this direction, let's add an optional ->init() callback to the variant data struct, which variants shall use to assign the mmci_host_ops pointer. Using an ->init() callback enables us to partition the code between different files. To allow separate mmci variant files to implement the variant specifics, let's also move the definition of the struct variant_data to the common mmci header file. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Ludovic Barre <ludovic.barre@st.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Ulf Hansson
Родитель
57d1654ec9
Коммит
ed9067fd5f
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@ -48,78 +48,6 @@
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static unsigned int fmax = 515633;
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/**
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* struct variant_data - MMCI variant-specific quirks
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* @clkreg: default value for MCICLOCK register
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* @clkreg_enable: enable value for MMCICLOCK register
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* @clkreg_8bit_bus_enable: enable value for 8 bit bus
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* @clkreg_neg_edge_enable: enable value for inverted data/cmd output
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* @datalength_bits: number of bits in the MMCIDATALENGTH register
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* @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY
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* is asserted (likewise for RX)
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* @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY
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* is asserted (likewise for RX)
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* @data_cmd_enable: enable value for data commands.
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* @st_sdio: enable ST specific SDIO logic
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* @st_clkdiv: true if using a ST-specific clock divider algorithm
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* @datactrl_mask_ddrmode: ddr mode mask in datactrl register.
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* @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register
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* @blksz_datactrl4: true if Block size is at b4..b16 position in datactrl
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* register
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* @datactrl_mask_sdio: SDIO enable mask in datactrl register
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* @pwrreg_powerup: power up value for MMCIPOWER register
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* @f_max: maximum clk frequency supported by the controller.
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* @signal_direction: input/out direction of bus signals can be indicated
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* @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock
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* @busy_detect: true if the variant supports busy detection on DAT0.
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* @busy_dpsm_flag: bitmask enabling busy detection in the DPSM
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* @busy_detect_flag: bitmask identifying the bit in the MMCISTATUS register
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* indicating that the card is busy
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* @busy_detect_mask: bitmask identifying the bit in the MMCIMASK0 to mask for
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* getting busy end detection interrupts
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* @pwrreg_nopower: bits in MMCIPOWER don't controls ext. power supply
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* @explicit_mclk_control: enable explicit mclk control in driver.
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* @qcom_fifo: enables qcom specific fifo pio read logic.
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* @qcom_dml: enables qcom specific dma glue for dma transfers.
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* @reversed_irq_handling: handle data irq before cmd irq.
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* @mmcimask1: true if variant have a MMCIMASK1 register.
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* @start_err: bitmask identifying the STARTBITERR bit inside MMCISTATUS
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* register.
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* @opendrain: bitmask identifying the OPENDRAIN bit inside MMCIPOWER register
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*/
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struct variant_data {
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unsigned int clkreg;
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unsigned int clkreg_enable;
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unsigned int clkreg_8bit_bus_enable;
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unsigned int clkreg_neg_edge_enable;
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unsigned int datalength_bits;
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unsigned int fifosize;
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unsigned int fifohalfsize;
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unsigned int data_cmd_enable;
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unsigned int datactrl_mask_ddrmode;
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unsigned int datactrl_mask_sdio;
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bool st_sdio;
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bool st_clkdiv;
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bool blksz_datactrl16;
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bool blksz_datactrl4;
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u32 pwrreg_powerup;
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u32 f_max;
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bool signal_direction;
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bool pwrreg_clkgate;
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bool busy_detect;
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u32 busy_dpsm_flag;
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u32 busy_detect_flag;
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u32 busy_detect_mask;
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bool pwrreg_nopower;
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bool explicit_mclk_control;
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bool qcom_fifo;
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bool qcom_dml;
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bool reversed_irq_handling;
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bool mmcimask1;
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u32 start_err;
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u32 opendrain;
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};
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static struct variant_data variant_arm = {
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.fifosize = 16 * 4,
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.fifohalfsize = 8 * 4,
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@ -1706,6 +1634,9 @@ static int mmci_probe(struct amba_device *dev,
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goto clk_disable;
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}
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if (variant->init)
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variant->init(host);
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/*
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* The ARM and ST versions of the block have slightly different
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* clock divider equations which means that the minimum divider
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@ -195,8 +195,85 @@
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#define MMCI_PINCTRL_STATE_OPENDRAIN "opendrain"
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struct clk;
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struct variant_data;
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struct dma_chan;
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struct mmci_host;
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/**
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* struct variant_data - MMCI variant-specific quirks
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* @clkreg: default value for MCICLOCK register
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* @clkreg_enable: enable value for MMCICLOCK register
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* @clkreg_8bit_bus_enable: enable value for 8 bit bus
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* @clkreg_neg_edge_enable: enable value for inverted data/cmd output
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* @datalength_bits: number of bits in the MMCIDATALENGTH register
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* @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY
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* is asserted (likewise for RX)
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* @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY
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* is asserted (likewise for RX)
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* @data_cmd_enable: enable value for data commands.
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* @st_sdio: enable ST specific SDIO logic
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* @st_clkdiv: true if using a ST-specific clock divider algorithm
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* @datactrl_mask_ddrmode: ddr mode mask in datactrl register.
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* @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register
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* @blksz_datactrl4: true if Block size is at b4..b16 position in datactrl
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* register
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* @datactrl_mask_sdio: SDIO enable mask in datactrl register
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* @pwrreg_powerup: power up value for MMCIPOWER register
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* @f_max: maximum clk frequency supported by the controller.
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* @signal_direction: input/out direction of bus signals can be indicated
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* @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock
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* @busy_detect: true if the variant supports busy detection on DAT0.
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* @busy_dpsm_flag: bitmask enabling busy detection in the DPSM
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* @busy_detect_flag: bitmask identifying the bit in the MMCISTATUS register
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* indicating that the card is busy
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* @busy_detect_mask: bitmask identifying the bit in the MMCIMASK0 to mask for
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* getting busy end detection interrupts
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* @pwrreg_nopower: bits in MMCIPOWER don't controls ext. power supply
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* @explicit_mclk_control: enable explicit mclk control in driver.
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* @qcom_fifo: enables qcom specific fifo pio read logic.
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* @qcom_dml: enables qcom specific dma glue for dma transfers.
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* @reversed_irq_handling: handle data irq before cmd irq.
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* @mmcimask1: true if variant have a MMCIMASK1 register.
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* @start_err: bitmask identifying the STARTBITERR bit inside MMCISTATUS
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* register.
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* @opendrain: bitmask identifying the OPENDRAIN bit inside MMCIPOWER register
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*/
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struct variant_data {
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unsigned int clkreg;
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unsigned int clkreg_enable;
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unsigned int clkreg_8bit_bus_enable;
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unsigned int clkreg_neg_edge_enable;
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unsigned int datalength_bits;
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unsigned int fifosize;
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unsigned int fifohalfsize;
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unsigned int data_cmd_enable;
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unsigned int datactrl_mask_ddrmode;
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unsigned int datactrl_mask_sdio;
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bool st_sdio;
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bool st_clkdiv;
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bool blksz_datactrl16;
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bool blksz_datactrl4;
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u32 pwrreg_powerup;
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u32 f_max;
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bool signal_direction;
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bool pwrreg_clkgate;
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bool busy_detect;
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u32 busy_dpsm_flag;
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u32 busy_detect_flag;
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u32 busy_detect_mask;
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bool pwrreg_nopower;
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bool explicit_mclk_control;
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bool qcom_fifo;
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bool qcom_dml;
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bool reversed_irq_handling;
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bool mmcimask1;
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u32 start_err;
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u32 opendrain;
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void (*init)(struct mmci_host *host);
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};
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/* mmci variant callbacks */
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struct mmci_host_ops {
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};
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struct mmci_host_next {
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struct dma_async_tx_descriptor *dma_desc;
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@ -228,6 +305,7 @@ struct mmci_host {
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u32 mask1_reg;
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bool vqmmc_enabled;
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struct mmci_platform_data *plat;
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struct mmci_host_ops *ops;
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struct variant_data *variant;
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struct pinctrl *pinctrl;
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struct pinctrl_state *pins_default;
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