x86: more coding style fixes in centaur.c
no code changed:
arch/x86/kernel/cpu/centaur.o:
text data bss dec hex filename
1031 324 0 1355 54b centaur.o.before
1031 324 0 1355 54b centaur.o.after
md5:
4f306a7f980b58eb69c4bdcfcde565f1 centaur.o.before.asm
4f306a7f980b58eb69c4bdcfcde565f1 centaur.o.after.asm
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
Ingo Molnar
Родитель
29a9994bd8
Коммит
edc05e6de3
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@ -1,10 +1,12 @@
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/bitops.h>
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#include <asm/processor.h>
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#include <asm/msr.h>
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#include <asm/e820.h>
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#include <asm/mtrr.h>
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#include "cpu.h"
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#ifdef CONFIG_X86_OOSTORE
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@ -12,8 +14,10 @@
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static u32 __cpuinit power2(u32 x)
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{
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u32 s = 1;
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while (s <= x)
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s <<= 1;
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return s >>= 1;
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}
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@ -21,7 +25,6 @@ static u32 __cpuinit power2(u32 x)
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/*
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* Set up an actual MCR
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*/
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static void __cpuinit centaur_mcr_insert(int reg, u32 base, u32 size, int key)
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{
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u32 lo, hi;
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@ -39,12 +42,11 @@ static void __cpuinit centaur_mcr_insert(int reg, u32 base, u32 size, int key)
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*
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* Shortcut: We know you can't put 4Gig of RAM on a winchip
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*/
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static u32 __cpuinit ramtop(void) /* 16388 */
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static u32 __cpuinit ramtop(void)
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{
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int i;
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u32 top = 0;
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u32 clip = 0xFFFFFFFFUL;
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u32 top = 0;
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int i;
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for (i = 0; i < e820.nr_map; i++) {
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unsigned long start, end;
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@ -55,10 +57,9 @@ static u32 __cpuinit ramtop(void) /* 16388 */
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* Don't MCR over reserved space. Ignore the ISA hole
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* we frob around that catastrophe already
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*/
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if (e820.map[i].type == E820_RESERVED)
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{
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if (e820.map[i].addr >= 0x100000UL && e820.map[i].addr < clip)
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if (e820.map[i].type == E820_RESERVED) {
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if (e820.map[i].addr >= 0x100000UL &&
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e820.map[i].addr < clip)
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clip = e820.map[i].addr;
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continue;
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}
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@ -69,18 +70,18 @@ static u32 __cpuinit ramtop(void) /* 16388 */
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if (end > top)
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top = end;
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}
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/* Everything below 'top' should be RAM except for the ISA hole.
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Because of the limited MCR's we want to map NV/ACPI into our
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MCR range for gunk in RAM
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Clip might cause us to MCR insufficient RAM but that is an
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acceptable failure mode and should only bite obscure boxes with
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a VESA hole at 15Mb
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The second case Clip sometimes kicks in is when the EBDA is marked
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as reserved. Again we fail safe with reasonable results
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/*
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* Everything below 'top' should be RAM except for the ISA hole.
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* Because of the limited MCR's we want to map NV/ACPI into our
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* MCR range for gunk in RAM
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*
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* Clip might cause us to MCR insufficient RAM but that is an
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* acceptable failure mode and should only bite obscure boxes with
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* a VESA hole at 15Mb
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*
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* The second case Clip sometimes kicks in is when the EBDA is marked
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* as reserved. Again we fail safe with reasonable results
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*/
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if (top > clip)
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top = clip;
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@ -90,7 +91,6 @@ static u32 __cpuinit ramtop(void) /* 16388 */
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/*
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* Compute a set of MCR's to give maximum coverage
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*/
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static int __cpuinit centaur_mcr_compute(int nr, int key)
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{
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u32 mem = ramtop();
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@ -100,27 +100,25 @@ static int __cpuinit centaur_mcr_compute(int nr, int key)
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u32 floor = 0;
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int ct = 0;
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while (ct < nr)
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{
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while (ct < nr) {
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u32 fspace = 0;
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u32 high;
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u32 low;
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/*
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* Find the largest block we will fill going upwards
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*/
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u32 high = power2(mem-top);
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high = power2(mem-top);
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/*
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* Find the largest block we will fill going downwards
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*/
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u32 low = base/2;
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low = base/2;
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/*
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* Don't fill below 1Mb going downwards as there
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* is an ISA hole in the way.
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*/
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if (base <= 1024*1024)
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low = 0;
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@ -139,34 +137,31 @@ static int __cpuinit centaur_mcr_compute(int nr, int key)
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/*
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* Now install the largest coverage we get
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*/
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if (fspace > high && fspace > low)
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{
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if (fspace > high && fspace > low) {
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centaur_mcr_insert(ct, floor, fspace, key);
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floor += fspace;
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}
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else if (high > low) {
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} else if (high > low) {
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centaur_mcr_insert(ct, top, high, key);
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top += high;
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}
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else if (low > 0) {
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} else if (low > 0) {
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base -= low;
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centaur_mcr_insert(ct, base, low, key);
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}
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else break;
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} else
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break;
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ct++;
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}
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/*
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* We loaded ct values. We now need to set the mask. The caller
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* must do this bit.
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*/
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return ct;
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}
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static void __cpuinit centaur_create_optimal_mcr(void)
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{
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int used;
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int i;
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/*
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* Allocate up to 6 mcrs to mark as much of ram as possible
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* as write combining and weak write ordered.
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@ -177,12 +172,11 @@ static void __cpuinit centaur_create_optimal_mcr(void)
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* Load the registers with type 31 - full write combining, all
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* writes weakly ordered.
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*/
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int used = centaur_mcr_compute(6, 31);
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used = centaur_mcr_compute(6, 31);
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/*
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* Wipe unused MCRs
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*/
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for (i = used; i < 8; i++)
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wrmsr(MSR_IDT_MCR0+i, 0, 0);
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}
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@ -190,6 +184,7 @@ static void __cpuinit centaur_create_optimal_mcr(void)
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static void __cpuinit winchip2_create_optimal_mcr(void)
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{
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u32 lo, hi;
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int used;
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int i;
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/*
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@ -201,13 +196,11 @@ static void __cpuinit winchip2_create_optimal_mcr(void)
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* 16 - weak read ordering
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* 1 - write combining
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*/
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int used = centaur_mcr_compute(6, 25);
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used = centaur_mcr_compute(6, 25);
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/*
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* Mark the registers we are using.
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*/
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rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
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for (i = 0; i < used; i++)
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lo |= 1<<(9+i);
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@ -224,7 +217,6 @@ static void __cpuinit winchip2_create_optimal_mcr(void)
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/*
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* Handle the MCR key on the Winchip 2.
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*/
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static void __cpuinit winchip2_unprotect_mcr(void)
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{
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u32 lo, hi;
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@ -301,8 +293,6 @@ static void __cpuinit init_c3(struct cpuinfo_x86 *c)
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display_cacheinfo(c);
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}
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static void __cpuinit init_centaur(struct cpuinfo_x86 *c)
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{
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enum {
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ECX8 = 1<<1,
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EIERRINT = 1<<2,
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@ -324,18 +314,22 @@ static void __cpuinit init_centaur(struct cpuinfo_x86 *c)
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EAMD3D = 1<<20,
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};
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static void __cpuinit init_centaur(struct cpuinfo_x86 *c)
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{
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char *name;
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u32 fcr_set = 0;
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u32 fcr_clr = 0;
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u32 lo, hi, newlo;
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u32 aa, bb, cc, dd;
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/* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
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3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
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/*
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* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
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* 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
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*/
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clear_bit(0*32+31, c->x86_capability);
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switch (c->x86) {
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case 5:
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switch (c->x86_model) {
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case 4:
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@ -346,15 +340,16 @@ static void __cpuinit init_centaur(struct cpuinfo_x86 *c)
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clear_bit(X86_FEATURE_TSC, c->x86_capability);
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#ifdef CONFIG_X86_OOSTORE
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centaur_create_optimal_mcr();
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/* Enable
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write combining on non-stack, non-string
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write combining on string, all types
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weak write ordering
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The C6 original lacks weak read order
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Note 0x120 is write only on Winchip 1 */
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/*
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* Enable:
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* write combining on non-stack, non-string
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* write combining on string, all types
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* weak write ordering
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*
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* The C6 original lacks weak read order
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*
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* Note 0x120 is write only on Winchip 1
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*/
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wrmsr(MSR_IDT_MCR_CTRL, 0x01F0001F, 0);
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#endif
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break;
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@ -370,16 +365,18 @@ static void __cpuinit init_centaur(struct cpuinfo_x86 *c)
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name = "2B";
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break;
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}
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fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|E2MMX|EAMD3D;
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fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|
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E2MMX|EAMD3D;
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fcr_clr = DPDC;
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#ifdef CONFIG_X86_OOSTORE
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winchip2_unprotect_mcr();
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winchip2_create_optimal_mcr();
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rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
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/* Enable
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write combining on non-stack, non-string
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write combining on string, all types
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weak write ordering
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/*
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* Enable:
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* write combining on non-stack, non-string
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* write combining on string, all types
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* weak write ordering
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*/
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lo |= 31;
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wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
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@ -388,16 +385,18 @@ static void __cpuinit init_centaur(struct cpuinfo_x86 *c)
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break;
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case 9:
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name = "3";
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fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|E2MMX|EAMD3D;
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fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|
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E2MMX|EAMD3D;
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fcr_clr = DPDC;
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#ifdef CONFIG_X86_OOSTORE
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winchip2_unprotect_mcr();
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winchip2_create_optimal_mcr();
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rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
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/* Enable
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write combining on non-stack, non-string
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write combining on string, all types
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weak write ordering
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/*
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* Enable:
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* write combining on non-stack, non-string
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* write combining on string, all types
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* weak write ordering
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*/
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lo |= 31;
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wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
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@ -412,7 +411,8 @@ static void __cpuinit init_centaur(struct cpuinfo_x86 *c)
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newlo = (lo|fcr_set) & (~fcr_clr);
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if (newlo != lo) {
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printk(KERN_INFO "Centaur FCR was 0x%X now 0x%X\n", lo, newlo);
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printk(KERN_INFO "Centaur FCR was 0x%X now 0x%X\n",
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lo, newlo);
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wrmsr(MSR_IDT_FCR1, newlo, hi);
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} else {
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printk(KERN_INFO "Centaur FCR is 0x%X\n", lo);
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@ -440,16 +440,20 @@ static void __cpuinit init_centaur(struct cpuinfo_x86 *c)
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}
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}
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static unsigned int __cpuinit centaur_size_cache(struct cpuinfo_x86 *c, unsigned int size)
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static unsigned int __cpuinit
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centaur_size_cache(struct cpuinfo_x86 *c, unsigned int size)
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{
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/* VIA C3 CPUs (670-68F) need further shifting. */
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if ((c->x86 == 6) && ((c->x86_model == 7) || (c->x86_model == 8)))
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size >>= 8;
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/* VIA also screwed up Nehemiah stepping 1, and made
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it return '65KB' instead of '64KB'
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- Note, it seems this may only be in engineering samples. */
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if ((c->x86 == 6) && (c->x86_model == 9) && (c->x86_mask == 1) && (size == 65))
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/*
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* There's also an erratum in Nehemiah stepping 1, which
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* returns '65KB' instead of '64KB'
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* - Note, it seems this may only be in engineering samples.
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*/
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if ((c->x86 == 6) && (c->x86_model == 9) &&
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(c->x86_mask == 1) && (size == 65))
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size -= 1;
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return size;
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