radeon: fix PCI bus mastering support enables.
Someone noticed these registers moved around for later chips, so we redo the codepaths per-chip. PCIE chips don't appear to require explicit enables. Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Alex Deucher
Dave Airlie
Родитель
b2ceddfa52
Коммит
edc6f389f6
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@ -363,6 +363,7 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
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R300_cp_microcode[i][0]);
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}
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} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
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((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R423) ||
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((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
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DRM_INFO("Loading R400 Microcode\n");
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for (i = 0; i < 256; i++) {
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@ -652,8 +653,18 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
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RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
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/* Turn on bus mastering */
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tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
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RADEON_WRITE(RADEON_BUS_CNTL, tmp);
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if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
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((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
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((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
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/* rs400, rs690/rs740 */
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tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS400_BUS_MASTER_DIS;
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RADEON_WRITE(RADEON_BUS_CNTL, tmp);
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} else if (!(((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
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((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R423))) {
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/* r1xx, r2xx, r300, r(v)350, r420/r481, rs480 */
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tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
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RADEON_WRITE(RADEON_BUS_CNTL, tmp);
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} /* PCIE cards appears to not need this */
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dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
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RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
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@ -1719,6 +1730,7 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
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case CHIP_R300:
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case CHIP_R350:
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case CHIP_R420:
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case CHIP_R423:
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case CHIP_RV410:
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case CHIP_RV515:
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case CHIP_R520:
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@ -122,6 +122,7 @@ enum radeon_family {
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CHIP_RV350,
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CHIP_RV380,
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CHIP_R420,
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CHIP_R423,
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CHIP_RV410,
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CHIP_RS400,
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CHIP_RS480,
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@ -439,8 +440,31 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
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# define RADEON_SCISSOR_1_ENABLE (1 << 29)
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# define RADEON_SCISSOR_2_ENABLE (1 << 30)
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/*
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* PCIE radeons (rv370/rv380, rv410, r423/r430/r480, r5xx)
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* don't have an explicit bus mastering disable bit. It's handled
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* by the PCI D-states. PMI_BM_DIS disables D-state bus master
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* handling, not bus mastering itself.
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*/
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#define RADEON_BUS_CNTL 0x0030
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/* r1xx, r2xx, r300, r(v)350, r420/r481, rs480 */
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# define RADEON_BUS_MASTER_DIS (1 << 6)
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/* rs400, rs690/rs740 */
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# define RS400_BUS_MASTER_DIS (1 << 14)
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# define RS400_MSI_REARM (1 << 20)
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/* see RS480_MSI_REARM in AIC_CNTL for rs480 */
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#define RADEON_BUS_CNTL1 0x0034
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# define RADEON_PMI_BM_DIS (1 << 2)
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# define RADEON_PMI_INT_DIS (1 << 3)
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#define RV370_BUS_CNTL 0x004c
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# define RV370_PMI_BM_DIS (1 << 5)
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# define RV370_PMI_INT_DIS (1 << 6)
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#define RADEON_MSI_REARM_EN 0x0160
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/* rv370/rv380, rv410, r423/r430/r480, r5xx */
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# define RV370_MSI_REARM_EN (1 << 0)
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#define RADEON_CLOCK_CNTL_DATA 0x000c
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# define RADEON_PLL_WR_EN (1 << 7)
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@ -913,6 +937,7 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
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#define RADEON_AIC_CNTL 0x01d0
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# define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
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# define RS480_MSI_REARM (1 << 3)
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#define RADEON_AIC_STAT 0x01d4
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#define RADEON_AIC_PT_BASE 0x01d8
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#define RADEON_AIC_LO_ADDR 0x01dc
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@ -84,18 +84,18 @@
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{0x1002, 0x5462, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \
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{0x1002, 0x5464, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \
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{0x1002, 0x5657, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x5548, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x5549, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x554A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x554B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x554C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x554D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x554E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x554F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x5550, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x5551, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x5552, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x5554, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x5548, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x5549, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x554A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x554B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x554C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x554D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x554E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x554F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x5550, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x5551, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x5552, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x5554, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x564A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x564B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x564F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
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@ -124,16 +124,16 @@
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{0x1002, 0x5b65, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x5c61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280|RADEON_IS_MOBILITY}, \
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{0x1002, 0x5c63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280|RADEON_IS_MOBILITY}, \
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{0x1002, 0x5d48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x5d49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x5d4a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x5d4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x5d4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x5d4e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x5d4f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x5d50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x5d52, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x5d57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x5d48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x5d49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x5d4a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x5d4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x5d4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x5d4e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x5d4f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x5d50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x5d52, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x5d57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x5e48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x5e4a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x5e4b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \
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