OMAP2420: hwmod data: add dmtimer
Add dmtimer data. Signed-off-by: Thara Gopinath <thara@ti.com> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com> Acked-by: Benoit Cousson <b-cousson@ti.com>
This commit is contained in:
Thara Gopinath
Paul Walmsley
Родитель
7cab8713b1
Коммит
eddb12624d
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@ -19,6 +19,7 @@
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#include <plat/i2c.h>
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#include <plat/gpio.h>
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#include <plat/mcspi.h>
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#include <plat/dmtimer.h>
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#include <plat/l3_2xxx.h>
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#include <plat/l4_2xxx.h>
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@ -337,6 +338,625 @@ static struct omap_hwmod omap2420_iva_hwmod = {
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
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};
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/* Timer Common */
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static struct omap_hwmod_class_sysconfig omap2420_timer_sysc = {
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.rev_offs = 0x0000,
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.sysc_offs = 0x0010,
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.syss_offs = 0x0014,
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.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
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SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
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SYSC_HAS_AUTOIDLE),
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
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.sysc_fields = &omap_hwmod_sysc_type1,
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};
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static struct omap_hwmod_class omap2420_timer_hwmod_class = {
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.name = "timer",
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.sysc = &omap2420_timer_sysc,
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.rev = OMAP_TIMER_IP_VERSION_1,
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};
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/* timer1 */
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static struct omap_hwmod omap2420_timer1_hwmod;
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static struct omap_hwmod_irq_info omap2420_timer1_mpu_irqs[] = {
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{ .irq = 37, },
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};
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static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
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{
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.pa_start = 0x48028000,
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.pa_end = 0x48028000 + SZ_1K - 1,
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.flags = ADDR_TYPE_RT
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},
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};
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/* l4_wkup -> timer1 */
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static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
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.master = &omap2420_l4_wkup_hwmod,
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.slave = &omap2420_timer1_hwmod,
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.clk = "gpt1_ick",
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.addr = omap2420_timer1_addrs,
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.addr_cnt = ARRAY_SIZE(omap2420_timer1_addrs),
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* timer1 slave port */
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static struct omap_hwmod_ocp_if *omap2420_timer1_slaves[] = {
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&omap2420_l4_wkup__timer1,
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};
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/* timer1 hwmod */
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static struct omap_hwmod omap2420_timer1_hwmod = {
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.name = "timer1",
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.mpu_irqs = omap2420_timer1_mpu_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer1_mpu_irqs),
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.main_clk = "gpt1_fck",
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.prcm = {
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.omap2 = {
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.prcm_reg_id = 1,
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.module_bit = OMAP24XX_EN_GPT1_SHIFT,
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.module_offs = WKUP_MOD,
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.idlest_reg_id = 1,
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.idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
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},
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},
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.slaves = omap2420_timer1_slaves,
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.slaves_cnt = ARRAY_SIZE(omap2420_timer1_slaves),
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.class = &omap2420_timer_hwmod_class,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
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};
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/* timer2 */
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static struct omap_hwmod omap2420_timer2_hwmod;
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static struct omap_hwmod_irq_info omap2420_timer2_mpu_irqs[] = {
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{ .irq = 38, },
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};
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static struct omap_hwmod_addr_space omap2420_timer2_addrs[] = {
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{
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.pa_start = 0x4802a000,
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.pa_end = 0x4802a000 + SZ_1K - 1,
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.flags = ADDR_TYPE_RT
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},
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};
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/* l4_core -> timer2 */
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static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = {
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.master = &omap2420_l4_core_hwmod,
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.slave = &omap2420_timer2_hwmod,
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.clk = "gpt2_ick",
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.addr = omap2420_timer2_addrs,
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.addr_cnt = ARRAY_SIZE(omap2420_timer2_addrs),
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* timer2 slave port */
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static struct omap_hwmod_ocp_if *omap2420_timer2_slaves[] = {
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&omap2420_l4_core__timer2,
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};
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/* timer2 hwmod */
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static struct omap_hwmod omap2420_timer2_hwmod = {
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.name = "timer2",
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.mpu_irqs = omap2420_timer2_mpu_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer2_mpu_irqs),
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.main_clk = "gpt2_fck",
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.prcm = {
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.omap2 = {
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.prcm_reg_id = 1,
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.module_bit = OMAP24XX_EN_GPT2_SHIFT,
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.module_offs = CORE_MOD,
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.idlest_reg_id = 1,
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.idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
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},
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},
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.slaves = omap2420_timer2_slaves,
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.slaves_cnt = ARRAY_SIZE(omap2420_timer2_slaves),
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.class = &omap2420_timer_hwmod_class,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
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};
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/* timer3 */
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static struct omap_hwmod omap2420_timer3_hwmod;
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static struct omap_hwmod_irq_info omap2420_timer3_mpu_irqs[] = {
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{ .irq = 39, },
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};
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static struct omap_hwmod_addr_space omap2420_timer3_addrs[] = {
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{
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.pa_start = 0x48078000,
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.pa_end = 0x48078000 + SZ_1K - 1,
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.flags = ADDR_TYPE_RT
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},
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};
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/* l4_core -> timer3 */
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static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = {
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.master = &omap2420_l4_core_hwmod,
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.slave = &omap2420_timer3_hwmod,
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.clk = "gpt3_ick",
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.addr = omap2420_timer3_addrs,
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.addr_cnt = ARRAY_SIZE(omap2420_timer3_addrs),
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* timer3 slave port */
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static struct omap_hwmod_ocp_if *omap2420_timer3_slaves[] = {
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&omap2420_l4_core__timer3,
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};
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/* timer3 hwmod */
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static struct omap_hwmod omap2420_timer3_hwmod = {
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.name = "timer3",
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.mpu_irqs = omap2420_timer3_mpu_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer3_mpu_irqs),
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.main_clk = "gpt3_fck",
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.prcm = {
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.omap2 = {
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.prcm_reg_id = 1,
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.module_bit = OMAP24XX_EN_GPT3_SHIFT,
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.module_offs = CORE_MOD,
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.idlest_reg_id = 1,
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.idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
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},
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},
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.slaves = omap2420_timer3_slaves,
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.slaves_cnt = ARRAY_SIZE(omap2420_timer3_slaves),
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.class = &omap2420_timer_hwmod_class,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
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};
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/* timer4 */
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static struct omap_hwmod omap2420_timer4_hwmod;
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static struct omap_hwmod_irq_info omap2420_timer4_mpu_irqs[] = {
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{ .irq = 40, },
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};
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static struct omap_hwmod_addr_space omap2420_timer4_addrs[] = {
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{
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.pa_start = 0x4807a000,
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.pa_end = 0x4807a000 + SZ_1K - 1,
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.flags = ADDR_TYPE_RT
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},
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};
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/* l4_core -> timer4 */
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static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = {
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.master = &omap2420_l4_core_hwmod,
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.slave = &omap2420_timer4_hwmod,
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.clk = "gpt4_ick",
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.addr = omap2420_timer4_addrs,
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.addr_cnt = ARRAY_SIZE(omap2420_timer4_addrs),
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* timer4 slave port */
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static struct omap_hwmod_ocp_if *omap2420_timer4_slaves[] = {
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&omap2420_l4_core__timer4,
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};
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/* timer4 hwmod */
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static struct omap_hwmod omap2420_timer4_hwmod = {
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.name = "timer4",
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.mpu_irqs = omap2420_timer4_mpu_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer4_mpu_irqs),
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.main_clk = "gpt4_fck",
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.prcm = {
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.omap2 = {
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.prcm_reg_id = 1,
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.module_bit = OMAP24XX_EN_GPT4_SHIFT,
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.module_offs = CORE_MOD,
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.idlest_reg_id = 1,
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.idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
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},
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},
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.slaves = omap2420_timer4_slaves,
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.slaves_cnt = ARRAY_SIZE(omap2420_timer4_slaves),
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.class = &omap2420_timer_hwmod_class,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
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};
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/* timer5 */
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static struct omap_hwmod omap2420_timer5_hwmod;
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static struct omap_hwmod_irq_info omap2420_timer5_mpu_irqs[] = {
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{ .irq = 41, },
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};
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static struct omap_hwmod_addr_space omap2420_timer5_addrs[] = {
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{
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.pa_start = 0x4807c000,
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.pa_end = 0x4807c000 + SZ_1K - 1,
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.flags = ADDR_TYPE_RT
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},
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};
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/* l4_core -> timer5 */
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static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = {
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.master = &omap2420_l4_core_hwmod,
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.slave = &omap2420_timer5_hwmod,
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.clk = "gpt5_ick",
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.addr = omap2420_timer5_addrs,
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.addr_cnt = ARRAY_SIZE(omap2420_timer5_addrs),
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* timer5 slave port */
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static struct omap_hwmod_ocp_if *omap2420_timer5_slaves[] = {
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&omap2420_l4_core__timer5,
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};
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/* timer5 hwmod */
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static struct omap_hwmod omap2420_timer5_hwmod = {
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.name = "timer5",
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.mpu_irqs = omap2420_timer5_mpu_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer5_mpu_irqs),
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.main_clk = "gpt5_fck",
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.prcm = {
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.omap2 = {
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.prcm_reg_id = 1,
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.module_bit = OMAP24XX_EN_GPT5_SHIFT,
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.module_offs = CORE_MOD,
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.idlest_reg_id = 1,
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.idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
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},
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},
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.slaves = omap2420_timer5_slaves,
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.slaves_cnt = ARRAY_SIZE(omap2420_timer5_slaves),
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.class = &omap2420_timer_hwmod_class,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
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};
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/* timer6 */
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static struct omap_hwmod omap2420_timer6_hwmod;
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static struct omap_hwmod_irq_info omap2420_timer6_mpu_irqs[] = {
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{ .irq = 42, },
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};
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static struct omap_hwmod_addr_space omap2420_timer6_addrs[] = {
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{
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.pa_start = 0x4807e000,
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.pa_end = 0x4807e000 + SZ_1K - 1,
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.flags = ADDR_TYPE_RT
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},
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};
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/* l4_core -> timer6 */
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static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = {
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.master = &omap2420_l4_core_hwmod,
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.slave = &omap2420_timer6_hwmod,
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.clk = "gpt6_ick",
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.addr = omap2420_timer6_addrs,
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.addr_cnt = ARRAY_SIZE(omap2420_timer6_addrs),
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* timer6 slave port */
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static struct omap_hwmod_ocp_if *omap2420_timer6_slaves[] = {
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&omap2420_l4_core__timer6,
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};
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/* timer6 hwmod */
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static struct omap_hwmod omap2420_timer6_hwmod = {
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.name = "timer6",
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.mpu_irqs = omap2420_timer6_mpu_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer6_mpu_irqs),
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.main_clk = "gpt6_fck",
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.prcm = {
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.omap2 = {
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.prcm_reg_id = 1,
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.module_bit = OMAP24XX_EN_GPT6_SHIFT,
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.module_offs = CORE_MOD,
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.idlest_reg_id = 1,
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.idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
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},
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},
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.slaves = omap2420_timer6_slaves,
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.slaves_cnt = ARRAY_SIZE(omap2420_timer6_slaves),
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.class = &omap2420_timer_hwmod_class,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
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};
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/* timer7 */
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static struct omap_hwmod omap2420_timer7_hwmod;
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static struct omap_hwmod_irq_info omap2420_timer7_mpu_irqs[] = {
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{ .irq = 43, },
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};
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static struct omap_hwmod_addr_space omap2420_timer7_addrs[] = {
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{
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.pa_start = 0x48080000,
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.pa_end = 0x48080000 + SZ_1K - 1,
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.flags = ADDR_TYPE_RT
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},
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};
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/* l4_core -> timer7 */
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static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = {
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.master = &omap2420_l4_core_hwmod,
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.slave = &omap2420_timer7_hwmod,
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.clk = "gpt7_ick",
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.addr = omap2420_timer7_addrs,
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.addr_cnt = ARRAY_SIZE(omap2420_timer7_addrs),
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* timer7 slave port */
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static struct omap_hwmod_ocp_if *omap2420_timer7_slaves[] = {
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&omap2420_l4_core__timer7,
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};
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/* timer7 hwmod */
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static struct omap_hwmod omap2420_timer7_hwmod = {
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.name = "timer7",
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.mpu_irqs = omap2420_timer7_mpu_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer7_mpu_irqs),
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.main_clk = "gpt7_fck",
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.prcm = {
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.omap2 = {
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.prcm_reg_id = 1,
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.module_bit = OMAP24XX_EN_GPT7_SHIFT,
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.module_offs = CORE_MOD,
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.idlest_reg_id = 1,
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.idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
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},
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},
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.slaves = omap2420_timer7_slaves,
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.slaves_cnt = ARRAY_SIZE(omap2420_timer7_slaves),
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.class = &omap2420_timer_hwmod_class,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
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};
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/* timer8 */
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static struct omap_hwmod omap2420_timer8_hwmod;
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static struct omap_hwmod_irq_info omap2420_timer8_mpu_irqs[] = {
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{ .irq = 44, },
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};
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static struct omap_hwmod_addr_space omap2420_timer8_addrs[] = {
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{
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.pa_start = 0x48082000,
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.pa_end = 0x48082000 + SZ_1K - 1,
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.flags = ADDR_TYPE_RT
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},
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};
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/* l4_core -> timer8 */
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static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = {
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.master = &omap2420_l4_core_hwmod,
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.slave = &omap2420_timer8_hwmod,
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.clk = "gpt8_ick",
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.addr = omap2420_timer8_addrs,
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.addr_cnt = ARRAY_SIZE(omap2420_timer8_addrs),
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* timer8 slave port */
|
||||
static struct omap_hwmod_ocp_if *omap2420_timer8_slaves[] = {
|
||||
&omap2420_l4_core__timer8,
|
||||
};
|
||||
|
||||
/* timer8 hwmod */
|
||||
static struct omap_hwmod omap2420_timer8_hwmod = {
|
||||
.name = "timer8",
|
||||
.mpu_irqs = omap2420_timer8_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer8_mpu_irqs),
|
||||
.main_clk = "gpt8_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_GPT8_SHIFT,
|
||||
.module_offs = CORE_MOD,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
|
||||
},
|
||||
},
|
||||
.slaves = omap2420_timer8_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2420_timer8_slaves),
|
||||
.class = &omap2420_timer_hwmod_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
|
||||
};
|
||||
|
||||
/* timer9 */
|
||||
static struct omap_hwmod omap2420_timer9_hwmod;
|
||||
static struct omap_hwmod_irq_info omap2420_timer9_mpu_irqs[] = {
|
||||
{ .irq = 45, },
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap2420_timer9_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48084000,
|
||||
.pa_end = 0x48084000 + SZ_1K - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
};
|
||||
|
||||
/* l4_core -> timer9 */
|
||||
static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = {
|
||||
.master = &omap2420_l4_core_hwmod,
|
||||
.slave = &omap2420_timer9_hwmod,
|
||||
.clk = "gpt9_ick",
|
||||
.addr = omap2420_timer9_addrs,
|
||||
.addr_cnt = ARRAY_SIZE(omap2420_timer9_addrs),
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* timer9 slave port */
|
||||
static struct omap_hwmod_ocp_if *omap2420_timer9_slaves[] = {
|
||||
&omap2420_l4_core__timer9,
|
||||
};
|
||||
|
||||
/* timer9 hwmod */
|
||||
static struct omap_hwmod omap2420_timer9_hwmod = {
|
||||
.name = "timer9",
|
||||
.mpu_irqs = omap2420_timer9_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer9_mpu_irqs),
|
||||
.main_clk = "gpt9_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_GPT9_SHIFT,
|
||||
.module_offs = CORE_MOD,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
|
||||
},
|
||||
},
|
||||
.slaves = omap2420_timer9_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2420_timer9_slaves),
|
||||
.class = &omap2420_timer_hwmod_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
|
||||
};
|
||||
|
||||
/* timer10 */
|
||||
static struct omap_hwmod omap2420_timer10_hwmod;
|
||||
static struct omap_hwmod_irq_info omap2420_timer10_mpu_irqs[] = {
|
||||
{ .irq = 46, },
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap2420_timer10_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48086000,
|
||||
.pa_end = 0x48086000 + SZ_1K - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
};
|
||||
|
||||
/* l4_core -> timer10 */
|
||||
static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = {
|
||||
.master = &omap2420_l4_core_hwmod,
|
||||
.slave = &omap2420_timer10_hwmod,
|
||||
.clk = "gpt10_ick",
|
||||
.addr = omap2420_timer10_addrs,
|
||||
.addr_cnt = ARRAY_SIZE(omap2420_timer10_addrs),
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* timer10 slave port */
|
||||
static struct omap_hwmod_ocp_if *omap2420_timer10_slaves[] = {
|
||||
&omap2420_l4_core__timer10,
|
||||
};
|
||||
|
||||
/* timer10 hwmod */
|
||||
static struct omap_hwmod omap2420_timer10_hwmod = {
|
||||
.name = "timer10",
|
||||
.mpu_irqs = omap2420_timer10_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer10_mpu_irqs),
|
||||
.main_clk = "gpt10_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_GPT10_SHIFT,
|
||||
.module_offs = CORE_MOD,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
|
||||
},
|
||||
},
|
||||
.slaves = omap2420_timer10_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2420_timer10_slaves),
|
||||
.class = &omap2420_timer_hwmod_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
|
||||
};
|
||||
|
||||
/* timer11 */
|
||||
static struct omap_hwmod omap2420_timer11_hwmod;
|
||||
static struct omap_hwmod_irq_info omap2420_timer11_mpu_irqs[] = {
|
||||
{ .irq = 47, },
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap2420_timer11_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48088000,
|
||||
.pa_end = 0x48088000 + SZ_1K - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
};
|
||||
|
||||
/* l4_core -> timer11 */
|
||||
static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = {
|
||||
.master = &omap2420_l4_core_hwmod,
|
||||
.slave = &omap2420_timer11_hwmod,
|
||||
.clk = "gpt11_ick",
|
||||
.addr = omap2420_timer11_addrs,
|
||||
.addr_cnt = ARRAY_SIZE(omap2420_timer11_addrs),
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* timer11 slave port */
|
||||
static struct omap_hwmod_ocp_if *omap2420_timer11_slaves[] = {
|
||||
&omap2420_l4_core__timer11,
|
||||
};
|
||||
|
||||
/* timer11 hwmod */
|
||||
static struct omap_hwmod omap2420_timer11_hwmod = {
|
||||
.name = "timer11",
|
||||
.mpu_irqs = omap2420_timer11_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer11_mpu_irqs),
|
||||
.main_clk = "gpt11_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_GPT11_SHIFT,
|
||||
.module_offs = CORE_MOD,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
|
||||
},
|
||||
},
|
||||
.slaves = omap2420_timer11_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2420_timer11_slaves),
|
||||
.class = &omap2420_timer_hwmod_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
|
||||
};
|
||||
|
||||
/* timer12 */
|
||||
static struct omap_hwmod omap2420_timer12_hwmod;
|
||||
static struct omap_hwmod_irq_info omap2420_timer12_mpu_irqs[] = {
|
||||
{ .irq = 48, },
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap2420_timer12_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x4808a000,
|
||||
.pa_end = 0x4808a000 + SZ_1K - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
};
|
||||
|
||||
/* l4_core -> timer12 */
|
||||
static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = {
|
||||
.master = &omap2420_l4_core_hwmod,
|
||||
.slave = &omap2420_timer12_hwmod,
|
||||
.clk = "gpt12_ick",
|
||||
.addr = omap2420_timer12_addrs,
|
||||
.addr_cnt = ARRAY_SIZE(omap2420_timer12_addrs),
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* timer12 slave port */
|
||||
static struct omap_hwmod_ocp_if *omap2420_timer12_slaves[] = {
|
||||
&omap2420_l4_core__timer12,
|
||||
};
|
||||
|
||||
/* timer12 hwmod */
|
||||
static struct omap_hwmod omap2420_timer12_hwmod = {
|
||||
.name = "timer12",
|
||||
.mpu_irqs = omap2420_timer12_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer12_mpu_irqs),
|
||||
.main_clk = "gpt12_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_GPT12_SHIFT,
|
||||
.module_offs = CORE_MOD,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
|
||||
},
|
||||
},
|
||||
.slaves = omap2420_timer12_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2420_timer12_slaves),
|
||||
.class = &omap2420_timer_hwmod_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
|
||||
};
|
||||
|
||||
/* l4_wkup -> wd_timer2 */
|
||||
static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
|
||||
{
|
||||
|
|
@ -1326,6 +1946,20 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = {
|
|||
&omap2420_l4_wkup_hwmod,
|
||||
&omap2420_mpu_hwmod,
|
||||
&omap2420_iva_hwmod,
|
||||
|
||||
&omap2420_timer1_hwmod,
|
||||
&omap2420_timer2_hwmod,
|
||||
&omap2420_timer3_hwmod,
|
||||
&omap2420_timer4_hwmod,
|
||||
&omap2420_timer5_hwmod,
|
||||
&omap2420_timer6_hwmod,
|
||||
&omap2420_timer7_hwmod,
|
||||
&omap2420_timer8_hwmod,
|
||||
&omap2420_timer9_hwmod,
|
||||
&omap2420_timer10_hwmod,
|
||||
&omap2420_timer11_hwmod,
|
||||
&omap2420_timer12_hwmod,
|
||||
|
||||
&omap2420_wd_timer2_hwmod,
|
||||
&omap2420_uart1_hwmod,
|
||||
&omap2420_uart2_hwmod,
|
||||
|
|
|
|||
|
|
@ -3,6 +3,12 @@
|
|||
*
|
||||
* OMAP Dual-Mode Timers
|
||||
*
|
||||
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* Tarun Kanti DebBarma <tarun.kanti@ti.com>
|
||||
* Thara Gopinath <thara@ti.com>
|
||||
*
|
||||
* Platform device conversion and hwmod support.
|
||||
*
|
||||
* Copyright (C) 2005 Nokia Corporation
|
||||
* Author: Lauri Leukkunen <lauri.leukkunen@nokia.com>
|
||||
* PWM and clock framwork support by Timo Teras.
|
||||
|
|
@ -44,6 +50,11 @@
|
|||
#define OMAP_TIMER_TRIGGER_OVERFLOW 0x01
|
||||
#define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02
|
||||
|
||||
/*
|
||||
* IP revision identifier so that Highlander IP
|
||||
* in OMAP4 can be distinguished.
|
||||
*/
|
||||
#define OMAP_TIMER_IP_VERSION_1 0x1
|
||||
struct omap_dm_timer;
|
||||
extern struct omap_dm_timer *gptimer_wakeup;
|
||||
extern struct sys_timer omap_timer;
|
||||
|
|
|
|||
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