Intel FB: obvious changes and corrections
Intel FB: obvious changes and corrections Signed-off-by: Krzysztof Halasa <khc@pm.waw.pl> Cc: "Antonino A. Daplas" <adaplas@pol.net> Cc: <sylvain.meyer@worldonline.fr> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Родитель
689c9568f5
Коммит
ee5618f493
|
@ -355,7 +355,10 @@ struct intelfb_info {
|
|||
struct intelfb_output_rec output[MAX_OUTPUTS];
|
||||
};
|
||||
|
||||
#define IS_I9XX(dinfo) (((dinfo)->chipset == INTEL_915G)||(dinfo->chipset == INTEL_915GM)||((dinfo)->chipset == INTEL_945G)||(dinfo->chipset==INTEL_945GM))
|
||||
#define IS_I9XX(dinfo) (((dinfo)->chipset == INTEL_915G) || \
|
||||
((dinfo)->chipset == INTEL_915GM) || \
|
||||
((dinfo)->chipset == INTEL_945G) || \
|
||||
((dinfo)->chipset==INTEL_945GM))
|
||||
|
||||
#ifndef FBIO_WAITFORVSYNC
|
||||
#define FBIO_WAITFORVSYNC _IOW('F', 0x20, __u32)
|
||||
|
|
|
@ -434,14 +434,14 @@ void intelfbhw_setcolreg(struct intelfb_info *dinfo, unsigned regno,
|
|||
unsigned red, unsigned green, unsigned blue,
|
||||
unsigned transp)
|
||||
{
|
||||
u32 palette_reg = (dinfo->pipe == PIPE_A) ?
|
||||
PALETTE_A : PALETTE_B;
|
||||
|
||||
#if VERBOSE > 0
|
||||
DBG_MSG("intelfbhw_setcolreg: %d: (%d, %d, %d)\n",
|
||||
regno, red, green, blue);
|
||||
#endif
|
||||
|
||||
u32 palette_reg = (dinfo->pipe == PIPE_A) ?
|
||||
PALETTE_A : PALETTE_B;
|
||||
|
||||
OUTREG(palette_reg + (regno << 2),
|
||||
(red << PALETTE_8_RED_SHIFT) |
|
||||
(green << PALETTE_8_GREEN_SHIFT) |
|
||||
|
@ -1305,8 +1305,8 @@ int intelfbhw_program_mode(struct intelfb_info *dinfo,
|
|||
|
||||
count = 0;
|
||||
do {
|
||||
tmp_val[count%3] = INREG(0x70000);
|
||||
if ((tmp_val[0] == tmp_val[1]) && (tmp_val[1]==tmp_val[2]))
|
||||
tmp_val[count % 3] = INREG(PIPEA_DSL);
|
||||
if ((tmp_val[0] == tmp_val[1]) && (tmp_val[1] == tmp_val[2]))
|
||||
break;
|
||||
count++;
|
||||
udelay(1);
|
||||
|
@ -2004,7 +2004,6 @@ intelfbhw_enable_irq(struct intelfb_info *dinfo, int reenable) {
|
|||
|
||||
void
|
||||
intelfbhw_disable_irq(struct intelfb_info *dinfo) {
|
||||
u16 tmp;
|
||||
|
||||
if (test_and_clear_bit(0, &dinfo->irq_flags)) {
|
||||
if (dinfo->vsync.pan_display) {
|
||||
|
@ -2016,8 +2015,7 @@ intelfbhw_disable_irq(struct intelfb_info *dinfo) {
|
|||
OUTREG16(IMR, 0xffff);
|
||||
OUTREG16(IER, 0x0);
|
||||
|
||||
tmp = INREG16(IIR);
|
||||
OUTREG16(IIR, tmp);
|
||||
OUTREG16(IIR, INREG16(IIR)); /* clear IRQ requests */
|
||||
spin_unlock_irq(&dinfo->int_lock);
|
||||
|
||||
free_irq(dinfo->pdev->irq, dinfo);
|
||||
|
|
|
@ -93,7 +93,7 @@
|
|||
#define IIR 0x20A4
|
||||
#define IMR 0x20A8
|
||||
#define VSYNC_PIPE_A_INTERRUPT (1 << 7)
|
||||
#define PIPE_A_EVENT_INTERRUPT (1 << 4)
|
||||
#define PIPE_A_EVENT_INTERRUPT (1 << 6)
|
||||
#define VSYNC_PIPE_B_INTERRUPT (1 << 5)
|
||||
#define PIPE_B_EVENT_INTERRUPT (1 << 4)
|
||||
#define HOST_PORT_EVENT_INTERRUPT (1 << 3)
|
||||
|
@ -276,6 +276,8 @@
|
|||
#define DVOB_SRCDIM 0x61144
|
||||
#define DVOC_SRCDIM 0x61164
|
||||
|
||||
#define PIPEA_DSL 0x70000
|
||||
#define PIPEB_DSL 0x71000
|
||||
#define PIPEACONF 0x70008
|
||||
#define PIPEBCONF 0x71008
|
||||
#define PIPECONF_ENABLE (1 << 31)
|
||||
|
|
Загрузка…
Ссылка в новой задаче