Merge branch 'topic/mpc512x' into for-linus
This commit is contained in:
Vinod Koul
Коммит
ee5644ce4b
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@ -3,6 +3,7 @@
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* Copyright (C) Semihalf 2009
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* Copyright (C) Ilya Yanok, Emcraft Systems 2010
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* Copyright (C) Alexander Popov, Promcontroller 2014
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* Copyright (C) Mario Six, Guntermann & Drunck GmbH, 2016
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*
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* Written by Piotr Ziecik <kosmo@semihalf.com>. Hardware description
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* (defines, structures and comments) was taken from MPC5121 DMA driver
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@ -26,18 +27,19 @@
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*/
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/*
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* MPC512x and MPC8308 DMA driver. It supports
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* memory to memory data transfers (tested using dmatest module) and
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* data transfers between memory and peripheral I/O memory
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* by means of slave scatter/gather with these limitations:
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* - chunked transfers (described by s/g lists with more than one item)
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* are refused as long as proper support for scatter/gather is missing;
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* - transfers on MPC8308 always start from software as this SoC appears
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* not to have external request lines for peripheral flow control;
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* - only peripheral devices with 4-byte FIFO access register are supported;
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* - minimal memory <-> I/O memory transfer chunk is 4 bytes and consequently
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* source and destination addresses must be 4-byte aligned
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* and transfer size must be aligned on (4 * maxburst) boundary;
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* MPC512x and MPC8308 DMA driver. It supports memory to memory data transfers
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* (tested using dmatest module) and data transfers between memory and
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* peripheral I/O memory by means of slave scatter/gather with these
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* limitations:
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* - chunked transfers (described by s/g lists with more than one item) are
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* refused as long as proper support for scatter/gather is missing
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* - transfers on MPC8308 always start from software as this SoC does not have
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* external request lines for peripheral flow control
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* - memory <-> I/O memory transfer chunks of sizes of 1, 2, 4, 16 (for
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* MPC512x), and 32 bytes are supported, and, consequently, source
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* addresses and destination addresses must be aligned accordingly;
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* furthermore, for MPC512x SoCs, the transfer size must be aligned on
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* (chunk size * maxburst)
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*/
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#include <linux/module.h>
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@ -213,8 +215,10 @@ struct mpc_dma_chan {
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/* Settings for access to peripheral FIFO */
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dma_addr_t src_per_paddr;
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u32 src_tcd_nunits;
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u8 swidth;
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dma_addr_t dst_per_paddr;
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u32 dst_tcd_nunits;
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u8 dwidth;
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/* Lock for this structure */
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spinlock_t lock;
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@ -247,6 +251,7 @@ static inline struct mpc_dma_chan *dma_chan_to_mpc_dma_chan(struct dma_chan *c)
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static inline struct mpc_dma *dma_chan_to_mpc_dma(struct dma_chan *c)
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{
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struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(c);
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return container_of(mchan, struct mpc_dma, channels[c->chan_id]);
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}
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@ -254,9 +259,9 @@ static inline struct mpc_dma *dma_chan_to_mpc_dma(struct dma_chan *c)
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* Execute all queued DMA descriptors.
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*
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* Following requirements must be met while calling mpc_dma_execute():
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* a) mchan->lock is acquired,
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* b) mchan->active list is empty,
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* c) mchan->queued list contains at least one entry.
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* a) mchan->lock is acquired,
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* b) mchan->active list is empty,
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* c) mchan->queued list contains at least one entry.
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*/
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static void mpc_dma_execute(struct mpc_dma_chan *mchan)
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{
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@ -446,20 +451,15 @@ static void mpc_dma_tasklet(unsigned long data)
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if (es & MPC_DMA_DMAES_SAE)
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dev_err(mdma->dma.dev, "- Source Address Error\n");
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if (es & MPC_DMA_DMAES_SOE)
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dev_err(mdma->dma.dev, "- Source Offset"
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" Configuration Error\n");
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dev_err(mdma->dma.dev, "- Source Offset Configuration Error\n");
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if (es & MPC_DMA_DMAES_DAE)
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dev_err(mdma->dma.dev, "- Destination Address"
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" Error\n");
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dev_err(mdma->dma.dev, "- Destination Address Error\n");
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if (es & MPC_DMA_DMAES_DOE)
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dev_err(mdma->dma.dev, "- Destination Offset"
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" Configuration Error\n");
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dev_err(mdma->dma.dev, "- Destination Offset Configuration Error\n");
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if (es & MPC_DMA_DMAES_NCE)
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dev_err(mdma->dma.dev, "- NBytes/Citter"
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" Configuration Error\n");
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dev_err(mdma->dma.dev, "- NBytes/Citter Configuration Error\n");
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if (es & MPC_DMA_DMAES_SGE)
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dev_err(mdma->dma.dev, "- Scatter/Gather"
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" Configuration Error\n");
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dev_err(mdma->dma.dev, "- Scatter/Gather Configuration Error\n");
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if (es & MPC_DMA_DMAES_SBE)
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dev_err(mdma->dma.dev, "- Source Bus Error\n");
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if (es & MPC_DMA_DMAES_DBE)
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@ -518,8 +518,8 @@ static int mpc_dma_alloc_chan_resources(struct dma_chan *chan)
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for (i = 0; i < MPC_DMA_DESCRIPTORS; i++) {
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mdesc = kzalloc(sizeof(struct mpc_dma_desc), GFP_KERNEL);
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if (!mdesc) {
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dev_notice(mdma->dma.dev, "Memory allocation error. "
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"Allocated only %u descriptors\n", i);
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dev_notice(mdma->dma.dev,
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"Memory allocation error. Allocated only %u descriptors\n", i);
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break;
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}
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@ -684,6 +684,15 @@ mpc_dma_prep_memcpy(struct dma_chan *chan, dma_addr_t dst, dma_addr_t src,
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return &mdesc->desc;
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}
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inline u8 buswidth_to_dmatsize(u8 buswidth)
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{
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u8 res;
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for (res = 0; buswidth > 1; buswidth /= 2)
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res++;
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return res;
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}
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static struct dma_async_tx_descriptor *
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mpc_dma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
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unsigned int sg_len, enum dma_transfer_direction direction,
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@ -742,39 +751,54 @@ mpc_dma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
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memset(tcd, 0, sizeof(struct mpc_dma_tcd));
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if (!IS_ALIGNED(sg_dma_address(sg), 4))
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goto err_prep;
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if (direction == DMA_DEV_TO_MEM) {
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tcd->saddr = per_paddr;
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tcd->daddr = sg_dma_address(sg);
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if (!IS_ALIGNED(sg_dma_address(sg), mchan->dwidth))
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goto err_prep;
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tcd->soff = 0;
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tcd->doff = 4;
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tcd->doff = mchan->dwidth;
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} else {
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tcd->saddr = sg_dma_address(sg);
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tcd->daddr = per_paddr;
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tcd->soff = 4;
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if (!IS_ALIGNED(sg_dma_address(sg), mchan->swidth))
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goto err_prep;
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tcd->soff = mchan->swidth;
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tcd->doff = 0;
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}
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tcd->ssize = MPC_DMA_TSIZE_4;
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tcd->dsize = MPC_DMA_TSIZE_4;
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tcd->ssize = buswidth_to_dmatsize(mchan->swidth);
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tcd->dsize = buswidth_to_dmatsize(mchan->dwidth);
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len = sg_dma_len(sg);
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tcd->nbytes = tcd_nunits * 4;
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if (!IS_ALIGNED(len, tcd->nbytes))
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goto err_prep;
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if (mdma->is_mpc8308) {
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tcd->nbytes = sg_dma_len(sg);
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if (!IS_ALIGNED(tcd->nbytes, mchan->swidth))
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goto err_prep;
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iter = len / tcd->nbytes;
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if (iter >= 1 << 15) {
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/* len is too big */
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goto err_prep;
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/* No major loops for MPC8303 */
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tcd->biter = 1;
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tcd->citer = 1;
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} else {
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len = sg_dma_len(sg);
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tcd->nbytes = tcd_nunits * tcd->ssize;
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if (!IS_ALIGNED(len, tcd->nbytes))
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goto err_prep;
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iter = len / tcd->nbytes;
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if (iter >= 1 << 15) {
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/* len is too big */
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goto err_prep;
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}
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/* citer_linkch contains the high bits of iter */
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tcd->biter = iter & 0x1ff;
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tcd->biter_linkch = iter >> 9;
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tcd->citer = tcd->biter;
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tcd->citer_linkch = tcd->biter_linkch;
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}
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/* citer_linkch contains the high bits of iter */
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tcd->biter = iter & 0x1ff;
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tcd->biter_linkch = iter >> 9;
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tcd->citer = tcd->biter;
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tcd->citer_linkch = tcd->biter_linkch;
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tcd->e_sg = 0;
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tcd->d_req = 1;
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@ -796,40 +820,62 @@ err_prep:
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return NULL;
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}
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inline bool is_buswidth_valid(u8 buswidth, bool is_mpc8308)
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{
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switch (buswidth) {
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case 16:
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if (is_mpc8308)
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return false;
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case 1:
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case 2:
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case 4:
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case 32:
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break;
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default:
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return false;
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}
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return true;
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}
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static int mpc_dma_device_config(struct dma_chan *chan,
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struct dma_slave_config *cfg)
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{
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struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(chan);
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struct mpc_dma *mdma = dma_chan_to_mpc_dma(&mchan->chan);
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unsigned long flags;
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/*
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* Software constraints:
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* - only transfers between a peripheral device and
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* memory are supported;
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* - only peripheral devices with 4-byte FIFO access register
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* are supported;
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* - minimal transfer chunk is 4 bytes and consequently
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* source and destination addresses must be 4-byte aligned
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* and transfer size must be aligned on (4 * maxburst)
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* boundary;
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* - during the transfer RAM address is being incremented by
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* the size of minimal transfer chunk;
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* - peripheral port's address is constant during the transfer.
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* - only transfers between a peripheral device and memory are
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* supported
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* - transfer chunk sizes of 1, 2, 4, 16 (for MPC512x), and 32 bytes
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* are supported, and, consequently, source addresses and
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* destination addresses; must be aligned accordingly; furthermore,
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* for MPC512x SoCs, the transfer size must be aligned on (chunk
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* size * maxburst)
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* - during the transfer, the RAM address is incremented by the size
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* of transfer chunk
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* - the peripheral port's address is constant during the transfer.
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*/
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if (cfg->src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES ||
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cfg->dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES ||
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!IS_ALIGNED(cfg->src_addr, 4) ||
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!IS_ALIGNED(cfg->dst_addr, 4)) {
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if (!IS_ALIGNED(cfg->src_addr, cfg->src_addr_width) ||
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!IS_ALIGNED(cfg->dst_addr, cfg->dst_addr_width)) {
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return -EINVAL;
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}
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if (!is_buswidth_valid(cfg->src_addr_width, mdma->is_mpc8308) ||
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!is_buswidth_valid(cfg->dst_addr_width, mdma->is_mpc8308))
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return -EINVAL;
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spin_lock_irqsave(&mchan->lock, flags);
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mchan->src_per_paddr = cfg->src_addr;
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mchan->src_tcd_nunits = cfg->src_maxburst;
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mchan->swidth = cfg->src_addr_width;
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mchan->dst_per_paddr = cfg->dst_addr;
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mchan->dst_tcd_nunits = cfg->dst_maxburst;
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mchan->dwidth = cfg->dst_addr_width;
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/* Apply defaults */
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if (mchan->src_tcd_nunits == 0)
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@ -875,7 +921,6 @@ static int mpc_dma_probe(struct platform_device *op)
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mdma = devm_kzalloc(dev, sizeof(struct mpc_dma), GFP_KERNEL);
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if (!mdma) {
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dev_err(dev, "Memory exhausted!\n");
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retval = -ENOMEM;
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goto err;
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}
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@ -999,7 +1044,8 @@ static int mpc_dma_probe(struct platform_device *op)
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out_be32(&mdma->regs->dmaerrl, 0xFFFF);
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} else {
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out_be32(&mdma->regs->dmacr, MPC_DMA_DMACR_EDCG |
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MPC_DMA_DMACR_ERGA | MPC_DMA_DMACR_ERCA);
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MPC_DMA_DMACR_ERGA |
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MPC_DMA_DMACR_ERCA);
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/* Disable hardware DMA requests */
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out_be32(&mdma->regs->dmaerqh, 0);
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