drm/i915: Add HDCP framework + base implementation
This patch adds the framework required to add HDCP support to intel connectors. It implements Aksv loading from fuse, and parts 1/2/3 of the HDCP authentication scheme. Note that without shim implementations, this does not actually implement HDCP. That will come in subsequent patches. Changes in v2: - Don't open code wait_fors (Chris) - drm_hdcp.c under MIT license (Daniel) - Move intel_hdcp_disable() call above ddi_disable (Ram) - Fix // comments (I wore a cone of shame for 12 hours to atone) (Daniel) - Justify intel_hdcp_shim with comments (Daniel) - Fixed async locking issues by adding hdcp_mutex (Daniel) - Don't alter connector_state in enable/disable (Daniel) Changes in v3: - Added hdcp_mutex/hdcp_value to make async reasonable - Added hdcp_prop_work to separate link checking & property setting - Added new helper for atomic_check state tracking (Daniel) - Moved enable/disable into atomic_commit with matching helpers - Moved intel_hdcp_check_link out of all locks when called from dp - Bumped up ksv_fifo timeout (noticed failure on one of my dongles) Changes in v4: - Remove SKL_ prefix from most register names (Daniel) - Move enable/disable back to modeset path (Daniel) - s/get_random_long/get_random_u32/ (Daniel) - Remove mode_config.mutex lock in prop_work (Daniel) - Add intel_hdcp_init to handle init of conn components (Daniel) - Actually check return value of attach_property - Check Bksv is valid before trying to authenticate (Ram) Changes in v5: - checkpatch whitespace changes - s/DRM_MODE_CONTENT_PROTECTION_OFF/DRM_MODE_CONTENT_PROTECTION_UNDESIRED/ - Fix ksv list wait timeout (actually wait 5s) - Increase the R0 timeout to 300ms (Ram) Changes in v6: - SPDX license Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Ramalingam C <ramalingm.c@intel.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20180108195545.218615-6-seanpaul@chromium.org
This commit is contained in:
Sean Paul
Родитель
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Коммит
ee5e5e7a5e
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@ -108,6 +108,7 @@ i915-y += intel_audio.o \
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intel_fbc.o \
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intel_fbc.o \
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intel_fifo_underrun.o \
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intel_fifo_underrun.o \
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intel_frontbuffer.o \
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intel_frontbuffer.o \
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intel_hdcp.o \
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intel_hotplug.o \
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intel_hotplug.o \
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intel_modes.o \
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intel_modes.o \
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intel_overlay.o \
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intel_overlay.o \
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@ -8043,6 +8043,7 @@ enum {
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#define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8
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#define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8
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#define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16
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#define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16
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#define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24
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#define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24
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#define SKL_PCODE_LOAD_HDCP_KEYS 0x5
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#define SKL_PCODE_CDCLK_CONTROL 0x7
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#define SKL_PCODE_CDCLK_CONTROL 0x7
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#define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3
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#define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3
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#define SKL_CDCLK_READY_FOR_CHANGE 0x1
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#define SKL_CDCLK_READY_FOR_CHANGE 0x1
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@ -8345,6 +8346,88 @@ enum skl_power_gate {
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#define SKL_PW_TO_PG(pw) ((pw) - SKL_DISP_PW_1 + SKL_PG1)
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#define SKL_PW_TO_PG(pw) ((pw) - SKL_DISP_PW_1 + SKL_PG1)
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#define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg)))
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#define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg)))
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/* HDCP Key Registers */
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#define HDCP_KEY_CONF _MMIO(0x66c00)
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#define HDCP_AKSV_SEND_TRIGGER BIT(31)
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#define HDCP_CLEAR_KEYS_TRIGGER BIT(30)
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#define HDCP_KEY_STATUS _MMIO(0x66c04)
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#define HDCP_FUSE_IN_PROGRESS BIT(7)
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#define HDCP_FUSE_ERROR BIT(6)
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#define HDCP_FUSE_DONE BIT(5)
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#define HDCP_KEY_LOAD_STATUS BIT(1)
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#define HDCP_KEY_LOAD_DONE BIT(0)
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#define HDCP_AKSV_LO _MMIO(0x66c10)
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#define HDCP_AKSV_HI _MMIO(0x66c14)
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/* HDCP Repeater Registers */
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#define HDCP_REP_CTL _MMIO(0x66d00)
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#define HDCP_DDIB_REP_PRESENT BIT(30)
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#define HDCP_DDIA_REP_PRESENT BIT(29)
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#define HDCP_DDIC_REP_PRESENT BIT(28)
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#define HDCP_DDID_REP_PRESENT BIT(27)
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#define HDCP_DDIF_REP_PRESENT BIT(26)
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#define HDCP_DDIE_REP_PRESENT BIT(25)
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#define HDCP_DDIB_SHA1_M0 (1 << 20)
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#define HDCP_DDIA_SHA1_M0 (2 << 20)
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#define HDCP_DDIC_SHA1_M0 (3 << 20)
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#define HDCP_DDID_SHA1_M0 (4 << 20)
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#define HDCP_DDIF_SHA1_M0 (5 << 20)
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#define HDCP_DDIE_SHA1_M0 (6 << 20) /* Bspec says 5? */
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#define HDCP_SHA1_BUSY BIT(16)
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#define HDCP_SHA1_READY BIT(17)
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#define HDCP_SHA1_COMPLETE BIT(18)
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#define HDCP_SHA1_V_MATCH BIT(19)
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#define HDCP_SHA1_TEXT_32 (1 << 1)
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#define HDCP_SHA1_COMPLETE_HASH (2 << 1)
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#define HDCP_SHA1_TEXT_24 (4 << 1)
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#define HDCP_SHA1_TEXT_16 (5 << 1)
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#define HDCP_SHA1_TEXT_8 (6 << 1)
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#define HDCP_SHA1_TEXT_0 (7 << 1)
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#define HDCP_SHA_V_PRIME_H0 _MMIO(0x66d04)
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#define HDCP_SHA_V_PRIME_H1 _MMIO(0x66d08)
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#define HDCP_SHA_V_PRIME_H2 _MMIO(0x66d0C)
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#define HDCP_SHA_V_PRIME_H3 _MMIO(0x66d10)
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#define HDCP_SHA_V_PRIME_H4 _MMIO(0x66d14)
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#define HDCP_SHA_V_PRIME(h) _MMIO((0x66d04 + h * 4))
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#define HDCP_SHA_TEXT _MMIO(0x66d18)
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/* HDCP Auth Registers */
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#define _PORTA_HDCP_AUTHENC 0x66800
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#define _PORTB_HDCP_AUTHENC 0x66500
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#define _PORTC_HDCP_AUTHENC 0x66600
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#define _PORTD_HDCP_AUTHENC 0x66700
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#define _PORTE_HDCP_AUTHENC 0x66A00
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#define _PORTF_HDCP_AUTHENC 0x66900
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#define _PORT_HDCP_AUTHENC(port, x) _MMIO(_PICK(port, \
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_PORTA_HDCP_AUTHENC, \
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_PORTB_HDCP_AUTHENC, \
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_PORTC_HDCP_AUTHENC, \
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_PORTD_HDCP_AUTHENC, \
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_PORTE_HDCP_AUTHENC, \
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_PORTF_HDCP_AUTHENC) + x)
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#define PORT_HDCP_CONF(port) _PORT_HDCP_AUTHENC(port, 0x0)
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#define HDCP_CONF_CAPTURE_AN BIT(0)
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#define HDCP_CONF_AUTH_AND_ENC (BIT(1) | BIT(0))
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#define PORT_HDCP_ANINIT(port) _PORT_HDCP_AUTHENC(port, 0x4)
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#define PORT_HDCP_ANLO(port) _PORT_HDCP_AUTHENC(port, 0x8)
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#define PORT_HDCP_ANHI(port) _PORT_HDCP_AUTHENC(port, 0xC)
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#define PORT_HDCP_BKSVLO(port) _PORT_HDCP_AUTHENC(port, 0x10)
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#define PORT_HDCP_BKSVHI(port) _PORT_HDCP_AUTHENC(port, 0x14)
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#define PORT_HDCP_RPRIME(port) _PORT_HDCP_AUTHENC(port, 0x18)
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#define PORT_HDCP_STATUS(port) _PORT_HDCP_AUTHENC(port, 0x1C)
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#define HDCP_STATUS_STREAM_A_ENC BIT(31)
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#define HDCP_STATUS_STREAM_B_ENC BIT(30)
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#define HDCP_STATUS_STREAM_C_ENC BIT(29)
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#define HDCP_STATUS_STREAM_D_ENC BIT(28)
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#define HDCP_STATUS_AUTH BIT(21)
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#define HDCP_STATUS_ENC BIT(20)
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#define HDCP_STATUS_RI_MATCH BIT(19)
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#define HDCP_STATUS_R0_READY BIT(18)
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#define HDCP_STATUS_AN_READY BIT(17)
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#define HDCP_STATUS_CIPHER BIT(16)
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#define HDCP_STATUS_FRAME_CNT(x) ((x >> 8) & 0xff)
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/* Per-pipe DDI Function Control */
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/* Per-pipe DDI Function Control */
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#define _TRANS_DDI_FUNC_CTL_A 0x60400
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#define _TRANS_DDI_FUNC_CTL_A 0x60400
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#define _TRANS_DDI_FUNC_CTL_B 0x61400
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#define _TRANS_DDI_FUNC_CTL_B 0x61400
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@ -110,6 +110,8 @@ int intel_digital_connector_atomic_check(struct drm_connector *conn,
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to_intel_digital_connector_state(old_state);
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to_intel_digital_connector_state(old_state);
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struct drm_crtc_state *crtc_state;
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struct drm_crtc_state *crtc_state;
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intel_hdcp_atomic_check(conn, old_state, new_state);
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if (!new_state->crtc)
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if (!new_state->crtc)
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return 0;
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return 0;
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@ -2423,6 +2423,11 @@ static void intel_enable_ddi(struct intel_encoder *encoder,
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intel_enable_ddi_hdmi(encoder, crtc_state, conn_state);
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intel_enable_ddi_hdmi(encoder, crtc_state, conn_state);
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else
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else
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intel_enable_ddi_dp(encoder, crtc_state, conn_state);
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intel_enable_ddi_dp(encoder, crtc_state, conn_state);
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/* Enable hdcp if it's desired */
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if (conn_state->content_protection ==
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DRM_MODE_CONTENT_PROTECTION_DESIRED)
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intel_hdcp_enable(to_intel_connector(conn_state->connector));
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}
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}
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static void intel_disable_ddi_dp(struct intel_encoder *encoder,
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static void intel_disable_ddi_dp(struct intel_encoder *encoder,
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@ -2457,6 +2462,8 @@ static void intel_disable_ddi(struct intel_encoder *encoder,
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const struct intel_crtc_state *old_crtc_state,
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const struct intel_crtc_state *old_crtc_state,
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const struct drm_connector_state *old_conn_state)
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const struct drm_connector_state *old_conn_state)
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{
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{
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intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
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if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
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if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
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intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state);
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intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state);
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else
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else
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@ -15217,6 +15217,10 @@ static void intel_hpd_poll_fini(struct drm_device *dev)
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for_each_intel_connector_iter(connector, &conn_iter) {
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for_each_intel_connector_iter(connector, &conn_iter) {
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if (connector->modeset_retry_work.func)
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if (connector->modeset_retry_work.func)
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cancel_work_sync(&connector->modeset_retry_work);
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cancel_work_sync(&connector->modeset_retry_work);
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if (connector->hdcp_shim) {
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cancel_delayed_work_sync(&connector->hdcp_check_work);
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cancel_work_sync(&connector->hdcp_prop_work);
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}
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}
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}
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drm_connector_list_iter_end(&conn_iter);
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drm_connector_list_iter_end(&conn_iter);
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}
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}
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@ -301,6 +301,76 @@ struct intel_panel {
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} backlight;
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} backlight;
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};
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};
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/*
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* This structure serves as a translation layer between the generic HDCP code
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* and the bus-specific code. What that means is that HDCP over HDMI differs
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* from HDCP over DP, so to account for these differences, we need to
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* communicate with the receiver through this shim.
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*
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* For completeness, the 2 buses differ in the following ways:
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* - DP AUX vs. DDC
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* HDCP registers on the receiver are set via DP AUX for DP, and
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* they are set via DDC for HDMI.
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* - Receiver register offsets
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* The offsets of the registers are different for DP vs. HDMI
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* - Receiver register masks/offsets
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* For instance, the ready bit for the KSV fifo is in a different
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* place on DP vs HDMI
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* - Receiver register names
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* Seriously. In the DP spec, the 16-bit register containing
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* downstream information is called BINFO, on HDMI it's called
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* BSTATUS. To confuse matters further, DP has a BSTATUS register
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* with a completely different definition.
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* - KSV FIFO
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* On HDMI, the ksv fifo is read all at once, whereas on DP it must
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* be read 3 keys at a time
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* - Aksv output
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* Since Aksv is hidden in hardware, there's different procedures
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* to send it over DP AUX vs DDC
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*/
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struct intel_hdcp_shim {
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/* Outputs the transmitter's An and Aksv values to the receiver. */
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int (*write_an_aksv)(struct intel_digital_port *intel_dig_port, u8 *an);
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/* Reads the receiver's key selection vector */
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int (*read_bksv)(struct intel_digital_port *intel_dig_port, u8 *bksv);
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/*
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* Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The
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* definitions are the same in the respective specs, but the names are
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* different. Call it BSTATUS since that's the name the HDMI spec
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* uses and it was there first.
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*/
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int (*read_bstatus)(struct intel_digital_port *intel_dig_port,
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u8 *bstatus);
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/* Determines whether a repeater is present downstream */
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int (*repeater_present)(struct intel_digital_port *intel_dig_port,
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bool *repeater_present);
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/* Reads the receiver's Ri' value */
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int (*read_ri_prime)(struct intel_digital_port *intel_dig_port, u8 *ri);
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/* Determines if the receiver's KSV FIFO is ready for consumption */
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int (*read_ksv_ready)(struct intel_digital_port *intel_dig_port,
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bool *ksv_ready);
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/* Reads the ksv fifo for num_downstream devices */
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int (*read_ksv_fifo)(struct intel_digital_port *intel_dig_port,
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int num_downstream, u8 *ksv_fifo);
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/* Reads a 32-bit part of V' from the receiver */
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int (*read_v_prime_part)(struct intel_digital_port *intel_dig_port,
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int i, u32 *part);
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/* Enables HDCP signalling on the port */
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int (*toggle_signalling)(struct intel_digital_port *intel_dig_port,
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bool enable);
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/* Ensures the link is still protected */
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bool (*check_link)(struct intel_digital_port *intel_dig_port);
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};
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struct intel_connector {
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struct intel_connector {
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struct drm_connector base;
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struct drm_connector base;
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/*
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/*
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@ -332,6 +402,12 @@ struct intel_connector {
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/* Work struct to schedule a uevent on link train failure */
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/* Work struct to schedule a uevent on link train failure */
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struct work_struct modeset_retry_work;
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struct work_struct modeset_retry_work;
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const struct intel_hdcp_shim *hdcp_shim;
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struct mutex hdcp_mutex;
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uint64_t hdcp_value; /* protected by hdcp_mutex */
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struct delayed_work hdcp_check_work;
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struct work_struct hdcp_prop_work;
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};
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};
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struct intel_digital_connector_state {
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struct intel_digital_connector_state {
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@ -1761,6 +1837,15 @@ static inline void intel_backlight_device_unregister(struct intel_connector *con
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}
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}
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#endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
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#endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
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/* intel_hdcp.c */
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void intel_hdcp_atomic_check(struct drm_connector *connector,
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struct drm_connector_state *old_state,
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struct drm_connector_state *new_state);
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int intel_hdcp_init(struct intel_connector *connector,
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const struct intel_hdcp_shim *hdcp_shim);
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int intel_hdcp_enable(struct intel_connector *connector);
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int intel_hdcp_disable(struct intel_connector *connector);
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int intel_hdcp_check_link(struct intel_connector *connector);
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/* intel_psr.c */
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/* intel_psr.c */
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void intel_psr_enable(struct intel_dp *intel_dp,
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void intel_psr_enable(struct intel_dp *intel_dp,
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@ -0,0 +1,723 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright (C) 2017 Google, Inc.
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*
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* Authors:
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* Sean Paul <seanpaul@chromium.org>
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*/
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#include <drm/drmP.h>
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||||||
|
#include <drm/drm_hdcp.h>
|
||||||
|
#include <linux/i2c.h>
|
||||||
|
#include <linux/random.h>
|
||||||
|
|
||||||
|
#include "intel_drv.h"
|
||||||
|
#include "i915_reg.h"
|
||||||
|
|
||||||
|
#define KEY_LOAD_TRIES 5
|
||||||
|
|
||||||
|
static int intel_hdcp_poll_ksv_fifo(struct intel_digital_port *intel_dig_port,
|
||||||
|
const struct intel_hdcp_shim *shim)
|
||||||
|
{
|
||||||
|
int ret, read_ret;
|
||||||
|
bool ksv_ready;
|
||||||
|
|
||||||
|
/* Poll for ksv list ready (spec says max time allowed is 5s) */
|
||||||
|
ret = __wait_for(read_ret = shim->read_ksv_ready(intel_dig_port,
|
||||||
|
&ksv_ready),
|
||||||
|
read_ret || ksv_ready, 5 * 1000 * 1000, 1000,
|
||||||
|
100 * 1000);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
if (read_ret)
|
||||||
|
return read_ret;
|
||||||
|
if (!ksv_ready)
|
||||||
|
return -ETIMEDOUT;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void intel_hdcp_clear_keys(struct drm_i915_private *dev_priv)
|
||||||
|
{
|
||||||
|
I915_WRITE(HDCP_KEY_CONF, HDCP_CLEAR_KEYS_TRIGGER);
|
||||||
|
I915_WRITE(HDCP_KEY_STATUS, HDCP_KEY_LOAD_DONE | HDCP_KEY_LOAD_STATUS |
|
||||||
|
HDCP_FUSE_IN_PROGRESS | HDCP_FUSE_ERROR | HDCP_FUSE_DONE);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int intel_hdcp_load_keys(struct drm_i915_private *dev_priv)
|
||||||
|
{
|
||||||
|
int ret;
|
||||||
|
u32 val;
|
||||||
|
|
||||||
|
/* Initiate loading the HDCP key from fuses */
|
||||||
|
mutex_lock(&dev_priv->pcu_lock);
|
||||||
|
ret = sandybridge_pcode_write(dev_priv, SKL_PCODE_LOAD_HDCP_KEYS, 1);
|
||||||
|
mutex_unlock(&dev_priv->pcu_lock);
|
||||||
|
if (ret) {
|
||||||
|
DRM_ERROR("Failed to initiate HDCP key load (%d)\n", ret);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Wait for the keys to load (500us) */
|
||||||
|
ret = __intel_wait_for_register(dev_priv, HDCP_KEY_STATUS,
|
||||||
|
HDCP_KEY_LOAD_DONE, HDCP_KEY_LOAD_DONE,
|
||||||
|
10, 1, &val);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
else if (!(val & HDCP_KEY_LOAD_STATUS))
|
||||||
|
return -ENXIO;
|
||||||
|
|
||||||
|
/* Send Aksv over to PCH display for use in authentication */
|
||||||
|
I915_WRITE(HDCP_KEY_CONF, HDCP_AKSV_SEND_TRIGGER);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Returns updated SHA-1 index */
|
||||||
|
static int intel_write_sha_text(struct drm_i915_private *dev_priv, u32 sha_text)
|
||||||
|
{
|
||||||
|
I915_WRITE(HDCP_SHA_TEXT, sha_text);
|
||||||
|
if (intel_wait_for_register(dev_priv, HDCP_REP_CTL,
|
||||||
|
HDCP_SHA1_READY, HDCP_SHA1_READY, 1)) {
|
||||||
|
DRM_ERROR("Timed out waiting for SHA1 ready\n");
|
||||||
|
return -ETIMEDOUT;
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static
|
||||||
|
u32 intel_hdcp_get_repeater_ctl(struct intel_digital_port *intel_dig_port)
|
||||||
|
{
|
||||||
|
enum port port = intel_dig_port->base.port;
|
||||||
|
switch (port) {
|
||||||
|
case PORT_A:
|
||||||
|
return HDCP_DDIA_REP_PRESENT | HDCP_DDIA_SHA1_M0;
|
||||||
|
case PORT_B:
|
||||||
|
return HDCP_DDIB_REP_PRESENT | HDCP_DDIB_SHA1_M0;
|
||||||
|
case PORT_C:
|
||||||
|
return HDCP_DDIC_REP_PRESENT | HDCP_DDIC_SHA1_M0;
|
||||||
|
case PORT_D:
|
||||||
|
return HDCP_DDID_REP_PRESENT | HDCP_DDID_SHA1_M0;
|
||||||
|
case PORT_E:
|
||||||
|
return HDCP_DDIE_REP_PRESENT | HDCP_DDIE_SHA1_M0;
|
||||||
|
default:
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
DRM_ERROR("Unknown port %d\n", port);
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
|
||||||
|
static
|
||||||
|
bool intel_hdcp_is_ksv_valid(u8 *ksv)
|
||||||
|
{
|
||||||
|
int i, ones = 0;
|
||||||
|
/* KSV has 20 1's and 20 0's */
|
||||||
|
for (i = 0; i < DRM_HDCP_KSV_LEN; i++)
|
||||||
|
ones += hweight8(ksv[i]);
|
||||||
|
if (ones != 20)
|
||||||
|
return false;
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Implements Part 2 of the HDCP authorization procedure */
|
||||||
|
static
|
||||||
|
int intel_hdcp_auth_downstream(struct intel_digital_port *intel_dig_port,
|
||||||
|
const struct intel_hdcp_shim *shim)
|
||||||
|
{
|
||||||
|
struct drm_i915_private *dev_priv;
|
||||||
|
u32 vprime, sha_text, sha_leftovers, rep_ctl;
|
||||||
|
u8 bstatus[2], num_downstream, *ksv_fifo;
|
||||||
|
int ret, i, j, sha_idx;
|
||||||
|
|
||||||
|
dev_priv = intel_dig_port->base.base.dev->dev_private;
|
||||||
|
|
||||||
|
ret = shim->read_bstatus(intel_dig_port, bstatus);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
/* If there are no downstream devices, we're all done. */
|
||||||
|
num_downstream = DRM_HDCP_NUM_DOWNSTREAM(bstatus[0]);
|
||||||
|
if (num_downstream == 0) {
|
||||||
|
DRM_INFO("HDCP is enabled (no downstream devices)\n");
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = intel_hdcp_poll_ksv_fifo(intel_dig_port, shim);
|
||||||
|
if (ret) {
|
||||||
|
DRM_ERROR("KSV list failed to become ready (%d)\n", ret);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
ksv_fifo = kzalloc(num_downstream * DRM_HDCP_KSV_LEN, GFP_KERNEL);
|
||||||
|
if (!ksv_fifo)
|
||||||
|
return -ENOMEM;
|
||||||
|
|
||||||
|
ret = shim->read_ksv_fifo(intel_dig_port, num_downstream, ksv_fifo);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
/* Process V' values from the receiver */
|
||||||
|
for (i = 0; i < DRM_HDCP_V_PRIME_NUM_PARTS; i++) {
|
||||||
|
ret = shim->read_v_prime_part(intel_dig_port, i, &vprime);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
I915_WRITE(HDCP_SHA_V_PRIME(i), vprime);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* We need to write the concatenation of all device KSVs, BINFO (DP) ||
|
||||||
|
* BSTATUS (HDMI), and M0 (which is added via HDCP_REP_CTL). This byte
|
||||||
|
* stream is written via the HDCP_SHA_TEXT register in 32-bit
|
||||||
|
* increments. Every 64 bytes, we need to write HDCP_REP_CTL again. This
|
||||||
|
* index will keep track of our progress through the 64 bytes as well as
|
||||||
|
* helping us work the 40-bit KSVs through our 32-bit register.
|
||||||
|
*
|
||||||
|
* NOTE: data passed via HDCP_SHA_TEXT should be big-endian
|
||||||
|
*/
|
||||||
|
sha_idx = 0;
|
||||||
|
sha_text = 0;
|
||||||
|
sha_leftovers = 0;
|
||||||
|
rep_ctl = intel_hdcp_get_repeater_ctl(intel_dig_port);
|
||||||
|
I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32);
|
||||||
|
for (i = 0; i < num_downstream; i++) {
|
||||||
|
unsigned int sha_empty;
|
||||||
|
u8 *ksv = &ksv_fifo[i * DRM_HDCP_KSV_LEN];
|
||||||
|
|
||||||
|
/* Fill up the empty slots in sha_text and write it out */
|
||||||
|
sha_empty = sizeof(sha_text) - sha_leftovers;
|
||||||
|
for (j = 0; j < sha_empty; j++)
|
||||||
|
sha_text |= ksv[j] << ((sizeof(sha_text) - j - 1) * 8);
|
||||||
|
|
||||||
|
ret = intel_write_sha_text(dev_priv, sha_text);
|
||||||
|
if (ret < 0)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
/* Programming guide writes this every 64 bytes */
|
||||||
|
sha_idx += sizeof(sha_text);
|
||||||
|
if (!(sha_idx % 64))
|
||||||
|
I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32);
|
||||||
|
|
||||||
|
/* Store the leftover bytes from the ksv in sha_text */
|
||||||
|
sha_leftovers = DRM_HDCP_KSV_LEN - sha_empty;
|
||||||
|
sha_text = 0;
|
||||||
|
for (j = 0; j < sha_leftovers; j++)
|
||||||
|
sha_text |= ksv[sha_empty + j] <<
|
||||||
|
((sizeof(sha_text) - j - 1) * 8);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* If we still have room in sha_text for more data, continue.
|
||||||
|
* Otherwise, write it out immediately.
|
||||||
|
*/
|
||||||
|
if (sizeof(sha_text) > sha_leftovers)
|
||||||
|
continue;
|
||||||
|
|
||||||
|
ret = intel_write_sha_text(dev_priv, sha_text);
|
||||||
|
if (ret < 0)
|
||||||
|
return ret;
|
||||||
|
sha_leftovers = 0;
|
||||||
|
sha_text = 0;
|
||||||
|
sha_idx += sizeof(sha_text);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* We need to write BINFO/BSTATUS, and M0 now. Depending on how many
|
||||||
|
* bytes are leftover from the last ksv, we might be able to fit them
|
||||||
|
* all in sha_text (first 2 cases), or we might need to split them up
|
||||||
|
* into 2 writes (last 2 cases).
|
||||||
|
*/
|
||||||
|
if (sha_leftovers == 0) {
|
||||||
|
/* Write 16 bits of text, 16 bits of M0 */
|
||||||
|
I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_16);
|
||||||
|
ret = intel_write_sha_text(dev_priv,
|
||||||
|
bstatus[0] << 8 | bstatus[1]);
|
||||||
|
if (ret < 0)
|
||||||
|
return ret;
|
||||||
|
sha_idx += sizeof(sha_text);
|
||||||
|
|
||||||
|
/* Write 32 bits of M0 */
|
||||||
|
I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_0);
|
||||||
|
ret = intel_write_sha_text(dev_priv, 0);
|
||||||
|
if (ret < 0)
|
||||||
|
return ret;
|
||||||
|
sha_idx += sizeof(sha_text);
|
||||||
|
|
||||||
|
/* Write 16 bits of M0 */
|
||||||
|
I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_16);
|
||||||
|
ret = intel_write_sha_text(dev_priv, 0);
|
||||||
|
if (ret < 0)
|
||||||
|
return ret;
|
||||||
|
sha_idx += sizeof(sha_text);
|
||||||
|
|
||||||
|
} else if (sha_leftovers == 1) {
|
||||||
|
/* Write 24 bits of text, 8 bits of M0 */
|
||||||
|
I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_24);
|
||||||
|
sha_text |= bstatus[0] << 16 | bstatus[1] << 8;
|
||||||
|
/* Only 24-bits of data, must be in the LSB */
|
||||||
|
sha_text = (sha_text & 0xffffff00) >> 8;
|
||||||
|
ret = intel_write_sha_text(dev_priv, sha_text);
|
||||||
|
if (ret < 0)
|
||||||
|
return ret;
|
||||||
|
sha_idx += sizeof(sha_text);
|
||||||
|
|
||||||
|
/* Write 32 bits of M0 */
|
||||||
|
I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_0);
|
||||||
|
ret = intel_write_sha_text(dev_priv, 0);
|
||||||
|
if (ret < 0)
|
||||||
|
return ret;
|
||||||
|
sha_idx += sizeof(sha_text);
|
||||||
|
|
||||||
|
/* Write 24 bits of M0 */
|
||||||
|
I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_8);
|
||||||
|
ret = intel_write_sha_text(dev_priv, 0);
|
||||||
|
if (ret < 0)
|
||||||
|
return ret;
|
||||||
|
sha_idx += sizeof(sha_text);
|
||||||
|
|
||||||
|
} else if (sha_leftovers == 2) {
|
||||||
|
/* Write 32 bits of text */
|
||||||
|
I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32);
|
||||||
|
sha_text |= bstatus[0] << 24 | bstatus[1] << 16;
|
||||||
|
ret = intel_write_sha_text(dev_priv, sha_text);
|
||||||
|
if (ret < 0)
|
||||||
|
return ret;
|
||||||
|
sha_idx += sizeof(sha_text);
|
||||||
|
|
||||||
|
/* Write 64 bits of M0 */
|
||||||
|
I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_0);
|
||||||
|
for (i = 0; i < 2; i++) {
|
||||||
|
ret = intel_write_sha_text(dev_priv, 0);
|
||||||
|
if (ret < 0)
|
||||||
|
return ret;
|
||||||
|
sha_idx += sizeof(sha_text);
|
||||||
|
}
|
||||||
|
} else if (sha_leftovers == 3) {
|
||||||
|
/* Write 32 bits of text */
|
||||||
|
I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32);
|
||||||
|
sha_text |= bstatus[0] << 24;
|
||||||
|
ret = intel_write_sha_text(dev_priv, sha_text);
|
||||||
|
if (ret < 0)
|
||||||
|
return ret;
|
||||||
|
sha_idx += sizeof(sha_text);
|
||||||
|
|
||||||
|
/* Write 8 bits of text, 24 bits of M0 */
|
||||||
|
I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_8);
|
||||||
|
ret = intel_write_sha_text(dev_priv, bstatus[1]);
|
||||||
|
if (ret < 0)
|
||||||
|
return ret;
|
||||||
|
sha_idx += sizeof(sha_text);
|
||||||
|
|
||||||
|
/* Write 32 bits of M0 */
|
||||||
|
I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_0);
|
||||||
|
ret = intel_write_sha_text(dev_priv, 0);
|
||||||
|
if (ret < 0)
|
||||||
|
return ret;
|
||||||
|
sha_idx += sizeof(sha_text);
|
||||||
|
|
||||||
|
/* Write 8 bits of M0 */
|
||||||
|
I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_24);
|
||||||
|
ret = intel_write_sha_text(dev_priv, 0);
|
||||||
|
if (ret < 0)
|
||||||
|
return ret;
|
||||||
|
sha_idx += sizeof(sha_text);
|
||||||
|
} else {
|
||||||
|
DRM_ERROR("Invalid number of leftovers %d\n", sha_leftovers);
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
|
||||||
|
I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32);
|
||||||
|
/* Fill up to 64-4 bytes with zeros (leave the last write for length) */
|
||||||
|
while ((sha_idx % 64) < (64 - sizeof(sha_text))) {
|
||||||
|
ret = intel_write_sha_text(dev_priv, 0);
|
||||||
|
if (ret < 0)
|
||||||
|
return ret;
|
||||||
|
sha_idx += sizeof(sha_text);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Last write gets the length of the concatenation in bits. That is:
|
||||||
|
* - 5 bytes per device
|
||||||
|
* - 10 bytes for BINFO/BSTATUS(2), M0(8)
|
||||||
|
*/
|
||||||
|
sha_text = (num_downstream * 5 + 10) * 8;
|
||||||
|
ret = intel_write_sha_text(dev_priv, sha_text);
|
||||||
|
if (ret < 0)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
/* Tell the HW we're done with the hash and wait for it to ACK */
|
||||||
|
I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_COMPLETE_HASH);
|
||||||
|
if (intel_wait_for_register(dev_priv, HDCP_REP_CTL,
|
||||||
|
HDCP_SHA1_COMPLETE,
|
||||||
|
HDCP_SHA1_COMPLETE, 1)) {
|
||||||
|
DRM_ERROR("Timed out waiting for SHA1 complete\n");
|
||||||
|
return -ETIMEDOUT;
|
||||||
|
}
|
||||||
|
if (!(I915_READ(HDCP_REP_CTL) & HDCP_SHA1_V_MATCH)) {
|
||||||
|
DRM_ERROR("SHA-1 mismatch, HDCP failed\n");
|
||||||
|
return -ENXIO;
|
||||||
|
}
|
||||||
|
|
||||||
|
DRM_INFO("HDCP is enabled (%d downstream devices)\n", num_downstream);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Implements Part 1 of the HDCP authorization procedure */
|
||||||
|
static int intel_hdcp_auth(struct intel_digital_port *intel_dig_port,
|
||||||
|
const struct intel_hdcp_shim *shim)
|
||||||
|
{
|
||||||
|
struct drm_i915_private *dev_priv;
|
||||||
|
enum port port;
|
||||||
|
unsigned long r0_prime_gen_start;
|
||||||
|
int ret, i;
|
||||||
|
union {
|
||||||
|
u32 reg[2];
|
||||||
|
u8 shim[DRM_HDCP_AN_LEN];
|
||||||
|
} an;
|
||||||
|
union {
|
||||||
|
u32 reg[2];
|
||||||
|
u8 shim[DRM_HDCP_KSV_LEN];
|
||||||
|
} bksv;
|
||||||
|
union {
|
||||||
|
u32 reg;
|
||||||
|
u8 shim[DRM_HDCP_RI_LEN];
|
||||||
|
} ri;
|
||||||
|
bool repeater_present;
|
||||||
|
|
||||||
|
dev_priv = intel_dig_port->base.base.dev->dev_private;
|
||||||
|
|
||||||
|
port = intel_dig_port->base.port;
|
||||||
|
|
||||||
|
/* Initialize An with 2 random values and acquire it */
|
||||||
|
for (i = 0; i < 2; i++)
|
||||||
|
I915_WRITE(PORT_HDCP_ANINIT(port), get_random_u32());
|
||||||
|
I915_WRITE(PORT_HDCP_CONF(port), HDCP_CONF_CAPTURE_AN);
|
||||||
|
|
||||||
|
/* Wait for An to be acquired */
|
||||||
|
if (intel_wait_for_register(dev_priv, PORT_HDCP_STATUS(port),
|
||||||
|
HDCP_STATUS_AN_READY,
|
||||||
|
HDCP_STATUS_AN_READY, 1)) {
|
||||||
|
DRM_ERROR("Timed out waiting for An\n");
|
||||||
|
return -ETIMEDOUT;
|
||||||
|
}
|
||||||
|
|
||||||
|
an.reg[0] = I915_READ(PORT_HDCP_ANLO(port));
|
||||||
|
an.reg[1] = I915_READ(PORT_HDCP_ANHI(port));
|
||||||
|
ret = shim->write_an_aksv(intel_dig_port, an.shim);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
r0_prime_gen_start = jiffies;
|
||||||
|
|
||||||
|
memset(&bksv, 0, sizeof(bksv));
|
||||||
|
ret = shim->read_bksv(intel_dig_port, bksv.shim);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
else if (!intel_hdcp_is_ksv_valid(bksv.shim))
|
||||||
|
return -ENODEV;
|
||||||
|
|
||||||
|
I915_WRITE(PORT_HDCP_BKSVLO(port), bksv.reg[0]);
|
||||||
|
I915_WRITE(PORT_HDCP_BKSVHI(port), bksv.reg[1]);
|
||||||
|
|
||||||
|
ret = shim->repeater_present(intel_dig_port, &repeater_present);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
if (repeater_present)
|
||||||
|
I915_WRITE(HDCP_REP_CTL,
|
||||||
|
intel_hdcp_get_repeater_ctl(intel_dig_port));
|
||||||
|
|
||||||
|
ret = shim->toggle_signalling(intel_dig_port, true);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
I915_WRITE(PORT_HDCP_CONF(port), HDCP_CONF_AUTH_AND_ENC);
|
||||||
|
|
||||||
|
/* Wait for R0 ready */
|
||||||
|
if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
|
||||||
|
(HDCP_STATUS_R0_READY | HDCP_STATUS_ENC), 1)) {
|
||||||
|
DRM_ERROR("Timed out waiting for R0 ready\n");
|
||||||
|
return -ETIMEDOUT;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Wait for R0' to become available. The spec says 100ms from Aksv, but
|
||||||
|
* some monitors can take longer than this. We'll set the timeout at
|
||||||
|
* 300ms just to be sure.
|
||||||
|
*
|
||||||
|
* On DP, there's an R0_READY bit available but no such bit
|
||||||
|
* exists on HDMI. Since the upper-bound is the same, we'll just do
|
||||||
|
* the stupid thing instead of polling on one and not the other.
|
||||||
|
*/
|
||||||
|
wait_remaining_ms_from_jiffies(r0_prime_gen_start, 300);
|
||||||
|
|
||||||
|
ri.reg = 0;
|
||||||
|
ret = shim->read_ri_prime(intel_dig_port, ri.shim);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);
|
||||||
|
|
||||||
|
/* Wait for Ri prime match */
|
||||||
|
if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
|
||||||
|
(HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
|
||||||
|
DRM_ERROR("Timed out waiting for Ri prime match (%x)\n",
|
||||||
|
I915_READ(PORT_HDCP_STATUS(port)));
|
||||||
|
return -ETIMEDOUT;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Wait for encryption confirmation */
|
||||||
|
if (intel_wait_for_register(dev_priv, PORT_HDCP_STATUS(port),
|
||||||
|
HDCP_STATUS_ENC, HDCP_STATUS_ENC, 20)) {
|
||||||
|
DRM_ERROR("Timed out waiting for encryption\n");
|
||||||
|
return -ETIMEDOUT;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* XXX: If we have MST-connected devices, we need to enable encryption
|
||||||
|
* on those as well.
|
||||||
|
*/
|
||||||
|
|
||||||
|
return intel_hdcp_auth_downstream(intel_dig_port, shim);
|
||||||
|
}
|
||||||
|
|
||||||
|
static
|
||||||
|
struct intel_digital_port *conn_to_dig_port(struct intel_connector *connector)
|
||||||
|
{
|
||||||
|
return enc_to_dig_port(&intel_attached_encoder(&connector->base)->base);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int _intel_hdcp_disable(struct intel_connector *connector)
|
||||||
|
{
|
||||||
|
struct drm_i915_private *dev_priv = connector->base.dev->dev_private;
|
||||||
|
struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
|
||||||
|
enum port port = intel_dig_port->base.port;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
I915_WRITE(PORT_HDCP_CONF(port), 0);
|
||||||
|
if (intel_wait_for_register(dev_priv, PORT_HDCP_STATUS(port), ~0, 0,
|
||||||
|
20)) {
|
||||||
|
DRM_ERROR("Failed to disable HDCP, timeout clearing status\n");
|
||||||
|
return -ETIMEDOUT;
|
||||||
|
}
|
||||||
|
|
||||||
|
intel_hdcp_clear_keys(dev_priv);
|
||||||
|
|
||||||
|
ret = connector->hdcp_shim->toggle_signalling(intel_dig_port, false);
|
||||||
|
if (ret) {
|
||||||
|
DRM_ERROR("Failed to disable HDCP signalling\n");
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
DRM_INFO("HDCP is disabled\n");
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int _intel_hdcp_enable(struct intel_connector *connector)
|
||||||
|
{
|
||||||
|
struct drm_i915_private *dev_priv = connector->base.dev->dev_private;
|
||||||
|
int i, ret;
|
||||||
|
|
||||||
|
if (!(I915_READ(SKL_FUSE_STATUS) & SKL_FUSE_PG_DIST_STATUS(1))) {
|
||||||
|
DRM_ERROR("PG1 is disabled, cannot load keys\n");
|
||||||
|
return -ENXIO;
|
||||||
|
}
|
||||||
|
|
||||||
|
for (i = 0; i < KEY_LOAD_TRIES; i++) {
|
||||||
|
ret = intel_hdcp_load_keys(dev_priv);
|
||||||
|
if (!ret)
|
||||||
|
break;
|
||||||
|
intel_hdcp_clear_keys(dev_priv);
|
||||||
|
}
|
||||||
|
if (ret) {
|
||||||
|
DRM_ERROR("Could not load HDCP keys, (%d)\n", ret);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = intel_hdcp_auth(conn_to_dig_port(connector),
|
||||||
|
connector->hdcp_shim);
|
||||||
|
if (ret) {
|
||||||
|
DRM_ERROR("Failed to authenticate HDCP (%d)\n", ret);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void intel_hdcp_check_work(struct work_struct *work)
|
||||||
|
{
|
||||||
|
struct intel_connector *connector = container_of(to_delayed_work(work),
|
||||||
|
struct intel_connector,
|
||||||
|
hdcp_check_work);
|
||||||
|
if (!intel_hdcp_check_link(connector))
|
||||||
|
schedule_delayed_work(&connector->hdcp_check_work,
|
||||||
|
DRM_HDCP_CHECK_PERIOD_MS);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void intel_hdcp_prop_work(struct work_struct *work)
|
||||||
|
{
|
||||||
|
struct intel_connector *connector = container_of(work,
|
||||||
|
struct intel_connector,
|
||||||
|
hdcp_prop_work);
|
||||||
|
struct drm_device *dev = connector->base.dev;
|
||||||
|
struct drm_connector_state *state;
|
||||||
|
|
||||||
|
drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
|
||||||
|
mutex_lock(&connector->hdcp_mutex);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* This worker is only used to flip between ENABLED/DESIRED. Either of
|
||||||
|
* those to UNDESIRED is handled by core. If hdcp_value == UNDESIRED,
|
||||||
|
* we're running just after hdcp has been disabled, so just exit
|
||||||
|
*/
|
||||||
|
if (connector->hdcp_value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
|
||||||
|
state = connector->base.state;
|
||||||
|
state->content_protection = connector->hdcp_value;
|
||||||
|
}
|
||||||
|
|
||||||
|
mutex_unlock(&connector->hdcp_mutex);
|
||||||
|
drm_modeset_unlock(&dev->mode_config.connection_mutex);
|
||||||
|
}
|
||||||
|
|
||||||
|
int intel_hdcp_init(struct intel_connector *connector,
|
||||||
|
const struct intel_hdcp_shim *hdcp_shim)
|
||||||
|
{
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
ret = drm_connector_attach_content_protection_property(
|
||||||
|
&connector->base);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
connector->hdcp_shim = hdcp_shim;
|
||||||
|
mutex_init(&connector->hdcp_mutex);
|
||||||
|
INIT_DELAYED_WORK(&connector->hdcp_check_work, intel_hdcp_check_work);
|
||||||
|
INIT_WORK(&connector->hdcp_prop_work, intel_hdcp_prop_work);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int intel_hdcp_enable(struct intel_connector *connector)
|
||||||
|
{
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
if (!connector->hdcp_shim)
|
||||||
|
return -ENOENT;
|
||||||
|
|
||||||
|
mutex_lock(&connector->hdcp_mutex);
|
||||||
|
|
||||||
|
ret = _intel_hdcp_enable(connector);
|
||||||
|
if (ret)
|
||||||
|
goto out;
|
||||||
|
|
||||||
|
connector->hdcp_value = DRM_MODE_CONTENT_PROTECTION_ENABLED;
|
||||||
|
schedule_work(&connector->hdcp_prop_work);
|
||||||
|
schedule_delayed_work(&connector->hdcp_check_work,
|
||||||
|
DRM_HDCP_CHECK_PERIOD_MS);
|
||||||
|
out:
|
||||||
|
mutex_unlock(&connector->hdcp_mutex);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
int intel_hdcp_disable(struct intel_connector *connector)
|
||||||
|
{
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
if (!connector->hdcp_shim)
|
||||||
|
return -ENOENT;
|
||||||
|
|
||||||
|
mutex_lock(&connector->hdcp_mutex);
|
||||||
|
|
||||||
|
connector->hdcp_value = DRM_MODE_CONTENT_PROTECTION_UNDESIRED;
|
||||||
|
ret = _intel_hdcp_disable(connector);
|
||||||
|
|
||||||
|
mutex_unlock(&connector->hdcp_mutex);
|
||||||
|
cancel_delayed_work_sync(&connector->hdcp_check_work);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
void intel_hdcp_atomic_check(struct drm_connector *connector,
|
||||||
|
struct drm_connector_state *old_state,
|
||||||
|
struct drm_connector_state *new_state)
|
||||||
|
{
|
||||||
|
uint64_t old_cp = old_state->content_protection;
|
||||||
|
uint64_t new_cp = new_state->content_protection;
|
||||||
|
struct drm_crtc_state *crtc_state;
|
||||||
|
|
||||||
|
if (!new_state->crtc) {
|
||||||
|
/*
|
||||||
|
* If the connector is being disabled with CP enabled, mark it
|
||||||
|
* desired so it's re-enabled when the connector is brought back
|
||||||
|
*/
|
||||||
|
if (old_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED)
|
||||||
|
new_state->content_protection =
|
||||||
|
DRM_MODE_CONTENT_PROTECTION_DESIRED;
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Nothing to do if the state didn't change, or HDCP was activated since
|
||||||
|
* the last commit
|
||||||
|
*/
|
||||||
|
if (old_cp == new_cp ||
|
||||||
|
(old_cp == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
|
||||||
|
new_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED))
|
||||||
|
return;
|
||||||
|
|
||||||
|
crtc_state = drm_atomic_get_new_crtc_state(new_state->state,
|
||||||
|
new_state->crtc);
|
||||||
|
crtc_state->mode_changed = true;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Implements Part 3 of the HDCP authorization procedure */
|
||||||
|
int intel_hdcp_check_link(struct intel_connector *connector)
|
||||||
|
{
|
||||||
|
struct drm_i915_private *dev_priv = connector->base.dev->dev_private;
|
||||||
|
struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
|
||||||
|
enum port port = intel_dig_port->base.port;
|
||||||
|
int ret = 0;
|
||||||
|
|
||||||
|
if (!connector->hdcp_shim)
|
||||||
|
return -ENOENT;
|
||||||
|
|
||||||
|
mutex_lock(&connector->hdcp_mutex);
|
||||||
|
|
||||||
|
if (connector->hdcp_value == DRM_MODE_CONTENT_PROTECTION_UNDESIRED)
|
||||||
|
goto out;
|
||||||
|
|
||||||
|
if (!(I915_READ(PORT_HDCP_STATUS(port)) & HDCP_STATUS_ENC)) {
|
||||||
|
DRM_ERROR("HDCP check failed: link is not encrypted, %x\n",
|
||||||
|
I915_READ(PORT_HDCP_STATUS(port)));
|
||||||
|
ret = -ENXIO;
|
||||||
|
connector->hdcp_value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
|
||||||
|
schedule_work(&connector->hdcp_prop_work);
|
||||||
|
goto out;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (connector->hdcp_shim->check_link(intel_dig_port)) {
|
||||||
|
if (connector->hdcp_value !=
|
||||||
|
DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
|
||||||
|
connector->hdcp_value =
|
||||||
|
DRM_MODE_CONTENT_PROTECTION_ENABLED;
|
||||||
|
schedule_work(&connector->hdcp_prop_work);
|
||||||
|
}
|
||||||
|
goto out;
|
||||||
|
}
|
||||||
|
|
||||||
|
DRM_INFO("HDCP link failed, retrying authentication\n");
|
||||||
|
|
||||||
|
ret = _intel_hdcp_disable(connector);
|
||||||
|
if (ret) {
|
||||||
|
DRM_ERROR("Failed to disable hdcp (%d)\n", ret);
|
||||||
|
connector->hdcp_value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
|
||||||
|
schedule_work(&connector->hdcp_prop_work);
|
||||||
|
goto out;
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = _intel_hdcp_enable(connector);
|
||||||
|
if (ret) {
|
||||||
|
DRM_ERROR("Failed to enable hdcp (%d)\n", ret);
|
||||||
|
connector->hdcp_value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
|
||||||
|
schedule_work(&connector->hdcp_prop_work);
|
||||||
|
goto out;
|
||||||
|
}
|
||||||
|
|
||||||
|
out:
|
||||||
|
mutex_unlock(&connector->hdcp_mutex);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
Загрузка…
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