sis900: remove TxIDLE
Before "sis900: fix TX completion" patch, TX completion was done on TxIDLE interrupt. TX completion also was the only thing done on TxIDLE interrupt. Since "sis900: fix TX completion", TX completion is done on TxDESC interrupt. So it is not necessary any more to set and to check for TxIDLE. Eliminate TxIDLE from sis900. Correct some typos, too. Signed-off-by: Sergej Benilov <sergej.benilov@googlemail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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ee7dd7733b
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@ -360,7 +360,7 @@ static int sis635_get_mac_addr(struct pci_dev *pci_dev,
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* SiS962 or SiS963 model, use EEPROM to store MAC address. And EEPROM
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* is shared by
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* LAN and 1394. When access EEPROM, send EEREQ signal to hardware first
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* and wait for EEGNT. If EEGNT is ON, EEPROM is permitted to be access
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* and wait for EEGNT. If EEGNT is ON, EEPROM is permitted to be accessed
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* by LAN, otherwise is not. After MAC address is read from EEPROM, send
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* EEDONE signal to refuse EEPROM access by LAN.
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* The EEPROM map of SiS962 or SiS963 is different to SiS900.
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@ -882,7 +882,7 @@ static void mdio_reset(struct sis900_private *sp)
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* mdio_read - read MII PHY register
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* @net_dev: the net device to read
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* @phy_id: the phy address to read
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* @location: the phy regiester id to read
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* @location: the phy register id to read
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*
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* Read MII registers through MDIO and MDC
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* using MDIO management frame structure and protocol(defined by ISO/IEC).
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@ -926,7 +926,7 @@ static int mdio_read(struct net_device *net_dev, int phy_id, int location)
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* mdio_write - write MII PHY register
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* @net_dev: the net device to write
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* @phy_id: the phy address to write
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* @location: the phy regiester id to write
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* @location: the phy register id to write
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* @value: the register value to write with
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*
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* Write MII registers with @value through MDIO and MDC
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@ -1057,7 +1057,7 @@ sis900_open(struct net_device *net_dev)
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sis900_set_mode(sis_priv, HW_SPEED_10_MBPS, FDX_CAPABLE_HALF_SELECTED);
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/* Enable all known interrupts by setting the interrupt mask. */
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sw32(imr, RxSOVR | RxORN | RxERR | RxOK | TxURN | TxERR | TxIDLE | TxDESC);
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sw32(imr, RxSOVR | RxORN | RxERR | RxOK | TxURN | TxERR | TxDESC);
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sw32(cr, RxENA | sr32(cr));
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sw32(ier, IE);
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@ -1101,7 +1101,7 @@ sis900_init_rxfilter (struct net_device * net_dev)
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sw32(rfdr, w);
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if (netif_msg_hw(sis_priv)) {
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printk(KERN_DEBUG "%s: Receive Filter Addrss[%d]=%x\n",
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printk(KERN_DEBUG "%s: Receive Filter Address[%d]=%x\n",
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net_dev->name, i, sr32(rfdr));
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}
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}
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@ -1148,7 +1148,7 @@ sis900_init_tx_ring(struct net_device *net_dev)
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* @net_dev: the net device to initialize for
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*
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* Initialize the Rx descriptor ring,
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* and pre-allocate recevie buffers (socket buffer)
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* and pre-allocate receive buffers (socket buffer)
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*/
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static void
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@ -1578,7 +1578,7 @@ static void sis900_tx_timeout(struct net_device *net_dev)
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sw32(txdp, sis_priv->tx_ring_dma);
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/* Enable all known interrupts by setting the interrupt mask. */
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sw32(imr, RxSOVR | RxORN | RxERR | RxOK | TxURN | TxERR | TxIDLE | TxDESC);
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sw32(imr, RxSOVR | RxORN | RxERR | RxOK | TxURN | TxERR | TxDESC);
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}
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/**
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@ -1674,8 +1674,8 @@ static irqreturn_t sis900_interrupt(int irq, void *dev_instance)
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do {
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status = sr32(isr);
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if ((status & (HIBERR|TxURN|TxERR|TxIDLE|TxDESC|RxORN|RxERR|RxOK)) == 0)
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/* nothing intresting happened */
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if ((status & (HIBERR|TxURN|TxERR|TxDESC|RxORN|RxERR|RxOK)) == 0)
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/* nothing interesting happened */
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break;
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handled = 1;
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@ -1684,7 +1684,7 @@ static irqreturn_t sis900_interrupt(int irq, void *dev_instance)
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/* Rx interrupt */
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sis900_rx(net_dev);
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if (status & (TxURN | TxERR | TxIDLE | TxDESC))
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if (status & (TxURN | TxERR | TxDESC))
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/* Tx interrupt */
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sis900_finish_xmit(net_dev);
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@ -1897,7 +1897,7 @@ static void sis900_finish_xmit (struct net_device *net_dev)
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if (tx_status & OWN) {
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/* The packet is not transmitted yet (owned by hardware) !
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* Note: this is an almost impossible condition
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* in case of TxDESC ('descriptor interrupt') */
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* on TxDESC interrupt ('descriptor interrupt') */
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break;
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}
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@ -2473,7 +2473,7 @@ static int sis900_resume(struct pci_dev *pci_dev)
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sis900_set_mode(sis_priv, HW_SPEED_10_MBPS, FDX_CAPABLE_HALF_SELECTED);
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/* Enable all known interrupts by setting the interrupt mask. */
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sw32(imr, RxSOVR | RxORN | RxERR | RxOK | TxURN | TxERR | TxIDLE | TxDESC);
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sw32(imr, RxSOVR | RxORN | RxERR | RxOK | TxURN | TxERR | TxDESC);
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sw32(cr, RxENA | sr32(cr));
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sw32(ier, IE);
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