RDMA/hns: Refactor reset state checking flow
The 'HNS_ROCE_OPC_QUERY_MB_ST' command will response the mailbox complete status and hardware busy flag, and the complete status is only valid when the busy flag is 0, so it's better to query these two fields at a time rather than separately. Link: https://lore.kernel.org/r/1616815294-13434-4-git-send-email-liweihang@huawei.com Signed-off-by: Xi Wang <wangxi11@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
This commit is contained in:
Xi Wang
Jason Gunthorpe
Родитель
d102a6e374
Коммит
ee82e68850
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@ -73,7 +73,7 @@ static int __hns_roce_cmd_mbox_poll(struct hns_roce_dev *hr_dev, u64 in_param,
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return ret;
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}
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return hr_dev->hw->chk_mbox(hr_dev, timeout);
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return hr_dev->hw->poll_mbox_done(hr_dev, timeout);
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}
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static int hns_roce_cmd_mbox_poll(struct hns_roce_dev *hr_dev, u64 in_param,
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@ -175,33 +175,20 @@ int hns_roce_cmd_mbox(struct hns_roce_dev *hr_dev, u64 in_param, u64 out_param,
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unsigned long in_modifier, u8 op_modifier, u16 op,
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unsigned int timeout)
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{
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int ret;
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bool is_busy;
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if (hr_dev->hw->rst_prc_mbox) {
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ret = hr_dev->hw->rst_prc_mbox(hr_dev);
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if (ret == CMD_RST_PRC_SUCCESS)
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return 0;
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else if (ret == CMD_RST_PRC_EBUSY)
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return -EBUSY;
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}
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if (hr_dev->hw->chk_mbox_avail)
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if (!hr_dev->hw->chk_mbox_avail(hr_dev, &is_busy))
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return is_busy ? -EBUSY : 0;
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if (hr_dev->cmd.use_events)
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ret = hns_roce_cmd_mbox_wait(hr_dev, in_param, out_param,
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in_modifier, op_modifier, op,
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timeout);
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return hns_roce_cmd_mbox_wait(hr_dev, in_param, out_param,
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in_modifier, op_modifier, op,
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timeout);
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else
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ret = hns_roce_cmd_mbox_poll(hr_dev, in_param, out_param,
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in_modifier, op_modifier, op,
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timeout);
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if (ret == CMD_RST_PRC_EBUSY)
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return -EBUSY;
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if (ret && (hr_dev->hw->rst_prc_mbox &&
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hr_dev->hw->rst_prc_mbox(hr_dev) == CMD_RST_PRC_SUCCESS))
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return 0;
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return ret;
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return hns_roce_cmd_mbox_poll(hr_dev, in_param, out_param,
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in_modifier, op_modifier, op,
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timeout);
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}
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int hns_roce_cmd_init(struct hns_roce_dev *hr_dev)
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@ -218,12 +218,6 @@ enum {
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HNS_ROCE_RST_DIRECT_RETURN = 0,
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};
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enum {
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CMD_RST_PRC_OTHERS,
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CMD_RST_PRC_SUCCESS,
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CMD_RST_PRC_EBUSY,
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};
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#define HNS_ROCE_CMD_SUCCESS 1
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/* The minimum page size is 4K for hardware */
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@ -896,8 +890,9 @@ struct hns_roce_hw {
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int (*post_mbox)(struct hns_roce_dev *hr_dev, u64 in_param,
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u64 out_param, u32 in_modifier, u8 op_modifier, u16 op,
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u16 token, int event);
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int (*chk_mbox)(struct hns_roce_dev *hr_dev, unsigned int timeout);
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int (*rst_prc_mbox)(struct hns_roce_dev *hr_dev);
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int (*poll_mbox_done)(struct hns_roce_dev *hr_dev,
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unsigned int timeout);
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bool (*chk_mbox_avail)(struct hns_roce_dev *hr_dev, bool *is_busy);
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int (*set_gid)(struct hns_roce_dev *hr_dev, u32 port, int gid_index,
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const union ib_gid *gid, const struct ib_gid_attr *attr);
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int (*set_mac)(struct hns_roce_dev *hr_dev, u8 phy_port, u8 *addr);
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@ -4349,7 +4349,7 @@ static const struct hns_roce_hw hns_roce_hw_v1 = {
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.hw_init = hns_roce_v1_init,
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.hw_exit = hns_roce_v1_exit,
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.post_mbox = hns_roce_v1_post_mbox,
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.chk_mbox = hns_roce_v1_chk_mbox,
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.poll_mbox_done = hns_roce_v1_chk_mbox,
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.set_gid = hns_roce_v1_set_gid,
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.set_mac = hns_roce_v1_set_mac,
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.set_mtu = hns_roce_v1_set_mtu,
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@ -48,6 +48,12 @@
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#include "hns_roce_hem.h"
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#include "hns_roce_hw_v2.h"
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enum {
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CMD_RST_PRC_OTHERS,
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CMD_RST_PRC_SUCCESS,
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CMD_RST_PRC_EBUSY,
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};
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static inline void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg,
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struct ib_sge *sg)
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{
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@ -1029,7 +1035,7 @@ static int hns_roce_v2_post_srq_recv(struct ib_srq *ibsrq,
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return ret;
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}
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static int hns_roce_v2_cmd_hw_reseted(struct hns_roce_dev *hr_dev,
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static u32 hns_roce_v2_cmd_hw_reseted(struct hns_roce_dev *hr_dev,
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unsigned long instance_stage,
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unsigned long reset_stage)
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{
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@ -1052,7 +1058,7 @@ static int hns_roce_v2_cmd_hw_reseted(struct hns_roce_dev *hr_dev,
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return CMD_RST_PRC_SUCCESS;
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}
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static int hns_roce_v2_cmd_hw_resetting(struct hns_roce_dev *hr_dev,
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static u32 hns_roce_v2_cmd_hw_resetting(struct hns_roce_dev *hr_dev,
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unsigned long instance_stage,
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unsigned long reset_stage)
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{
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@ -1080,7 +1086,7 @@ static int hns_roce_v2_cmd_hw_resetting(struct hns_roce_dev *hr_dev,
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return CMD_RST_PRC_SUCCESS;
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}
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static int hns_roce_v2_cmd_sw_resetting(struct hns_roce_dev *hr_dev)
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static u32 hns_roce_v2_cmd_sw_resetting(struct hns_roce_dev *hr_dev)
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{
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struct hns_roce_v2_priv *priv = hr_dev->priv;
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struct hnae3_handle *handle = priv->handle;
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@ -1097,10 +1103,9 @@ static int hns_roce_v2_cmd_sw_resetting(struct hns_roce_dev *hr_dev)
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return CMD_RST_PRC_EBUSY;
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}
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static int hns_roce_v2_rst_process_cmd(struct hns_roce_dev *hr_dev)
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static u32 check_aedev_reset_status(struct hns_roce_dev *hr_dev,
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struct hnae3_handle *handle)
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{
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struct hns_roce_v2_priv *priv = hr_dev->priv;
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struct hnae3_handle *handle = priv->handle;
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const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
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unsigned long instance_stage; /* the current instance stage */
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unsigned long reset_stage; /* the current reset stage */
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@ -1108,9 +1113,6 @@ static int hns_roce_v2_rst_process_cmd(struct hns_roce_dev *hr_dev)
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bool sw_resetting;
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bool hw_resetting;
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if (hr_dev->is_reset)
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return CMD_RST_PRC_SUCCESS;
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/* Get information about reset from NIC driver or RoCE driver itself,
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* the meaning of the following variables from NIC driver are described
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* as below:
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@ -1121,19 +1123,53 @@ static int hns_roce_v2_rst_process_cmd(struct hns_roce_dev *hr_dev)
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instance_stage = handle->rinfo.instance_state;
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reset_stage = handle->rinfo.reset_state;
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reset_cnt = ops->ae_dev_reset_cnt(handle);
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hw_resetting = ops->get_cmdq_stat(handle);
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sw_resetting = ops->ae_dev_resetting(handle);
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if (reset_cnt != hr_dev->reset_cnt)
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return hns_roce_v2_cmd_hw_reseted(hr_dev, instance_stage,
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reset_stage);
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else if (hw_resetting)
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hw_resetting = ops->get_cmdq_stat(handle);
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if (hw_resetting)
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return hns_roce_v2_cmd_hw_resetting(hr_dev, instance_stage,
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reset_stage);
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else if (sw_resetting && instance_stage == HNS_ROCE_STATE_INIT)
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sw_resetting = ops->ae_dev_resetting(handle);
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if (sw_resetting && instance_stage == HNS_ROCE_STATE_INIT)
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return hns_roce_v2_cmd_sw_resetting(hr_dev);
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return 0;
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return CMD_RST_PRC_OTHERS;
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}
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static bool check_device_is_in_reset(struct hns_roce_dev *hr_dev)
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{
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struct hns_roce_v2_priv *priv = hr_dev->priv;
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struct hnae3_handle *handle = priv->handle;
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const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
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if (hr_dev->reset_cnt != ops->ae_dev_reset_cnt(handle))
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return true;
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if (ops->get_hw_reset_stat(handle))
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return true;
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if (ops->ae_dev_resetting(handle))
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return true;
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return false;
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}
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static bool v2_chk_mbox_is_avail(struct hns_roce_dev *hr_dev, bool *busy)
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{
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struct hns_roce_v2_priv *priv = hr_dev->priv;
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u32 status;
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if (hr_dev->is_reset)
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status = CMD_RST_PRC_SUCCESS;
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else
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status = check_aedev_reset_status(hr_dev, priv->handle);
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*busy = (status == CMD_RST_PRC_EBUSY);
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return status == CMD_RST_PRC_OTHERS;
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}
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static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev,
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@ -1349,22 +1385,16 @@ static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev,
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static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev,
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struct hns_roce_cmq_desc *desc, int num)
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{
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int retval;
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bool busy;
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int ret;
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ret = hns_roce_v2_rst_process_cmd(hr_dev);
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if (ret == CMD_RST_PRC_SUCCESS)
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return 0;
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if (ret == CMD_RST_PRC_EBUSY)
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return -EBUSY;
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if (!v2_chk_mbox_is_avail(hr_dev, &busy))
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return busy ? -EBUSY : 0;
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ret = __hns_roce_cmq_send(hr_dev, desc, num);
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if (ret) {
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retval = hns_roce_v2_rst_process_cmd(hr_dev);
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if (retval == CMD_RST_PRC_SUCCESS)
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return 0;
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else if (retval == CMD_RST_PRC_EBUSY)
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return -EBUSY;
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if (!v2_chk_mbox_is_avail(hr_dev, &busy))
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return busy ? -EBUSY : 0;
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}
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return ret;
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@ -1388,91 +1418,89 @@ static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev)
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return 0;
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}
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static bool hns_roce_func_clr_chk_rst(struct hns_roce_dev *hr_dev)
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static void func_clr_hw_resetting_state(struct hns_roce_dev *hr_dev,
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struct hnae3_handle *handle)
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{
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struct hns_roce_v2_priv *priv = hr_dev->priv;
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struct hnae3_handle *handle = priv->handle;
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const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
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unsigned long reset_cnt;
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bool sw_resetting;
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bool hw_resetting;
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unsigned long end;
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reset_cnt = ops->ae_dev_reset_cnt(handle);
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hw_resetting = ops->get_hw_reset_stat(handle);
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sw_resetting = ops->ae_dev_resetting(handle);
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hr_dev->dis_db = true;
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if (reset_cnt != hr_dev->reset_cnt || hw_resetting || sw_resetting)
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return true;
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dev_warn(hr_dev->dev,
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"Func clear is pending, device in resetting state.\n");
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end = HNS_ROCE_V2_HW_RST_TIMEOUT;
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while (end) {
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if (!ops->get_hw_reset_stat(handle)) {
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hr_dev->is_reset = true;
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dev_info(hr_dev->dev,
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"Func clear success after reset.\n");
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return;
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}
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msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT);
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end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT;
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}
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return false;
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dev_warn(hr_dev->dev, "Func clear failed.\n");
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}
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static void hns_roce_func_clr_rst_prc(struct hns_roce_dev *hr_dev, int retval,
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int flag)
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static void func_clr_sw_resetting_state(struct hns_roce_dev *hr_dev,
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struct hnae3_handle *handle)
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{
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const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
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unsigned long end;
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hr_dev->dis_db = true;
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dev_warn(hr_dev->dev,
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"Func clear is pending, device in resetting state.\n");
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end = HNS_ROCE_V2_HW_RST_TIMEOUT;
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while (end) {
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if (ops->ae_dev_reset_cnt(handle) !=
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hr_dev->reset_cnt) {
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hr_dev->is_reset = true;
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dev_info(hr_dev->dev,
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"Func clear success after sw reset\n");
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return;
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}
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msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT);
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end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT;
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}
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dev_warn(hr_dev->dev, "Func clear failed because of unfinished sw reset\n");
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}
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static void hns_roce_func_clr_rst_proc(struct hns_roce_dev *hr_dev, int retval,
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int flag)
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{
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struct hns_roce_v2_priv *priv = hr_dev->priv;
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struct hnae3_handle *handle = priv->handle;
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const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
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unsigned long instance_stage;
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unsigned long reset_cnt;
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unsigned long end;
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bool sw_resetting;
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bool hw_resetting;
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instance_stage = handle->rinfo.instance_state;
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reset_cnt = ops->ae_dev_reset_cnt(handle);
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hw_resetting = ops->get_hw_reset_stat(handle);
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sw_resetting = ops->ae_dev_resetting(handle);
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if (reset_cnt != hr_dev->reset_cnt) {
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if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt) {
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hr_dev->dis_db = true;
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hr_dev->is_reset = true;
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dev_info(hr_dev->dev, "Func clear success after reset.\n");
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} else if (hw_resetting) {
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hr_dev->dis_db = true;
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dev_warn(hr_dev->dev,
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"Func clear is pending, device in resetting state.\n");
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end = HNS_ROCE_V2_HW_RST_TIMEOUT;
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while (end) {
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if (!ops->get_hw_reset_stat(handle)) {
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hr_dev->is_reset = true;
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dev_info(hr_dev->dev,
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"Func clear success after reset.\n");
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return;
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}
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msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT);
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end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT;
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}
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dev_warn(hr_dev->dev, "Func clear failed.\n");
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} else if (sw_resetting && instance_stage == HNS_ROCE_STATE_INIT) {
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hr_dev->dis_db = true;
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dev_warn(hr_dev->dev,
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"Func clear is pending, device in resetting state.\n");
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end = HNS_ROCE_V2_HW_RST_TIMEOUT;
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while (end) {
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if (ops->ae_dev_reset_cnt(handle) !=
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hr_dev->reset_cnt) {
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hr_dev->is_reset = true;
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dev_info(hr_dev->dev,
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"Func clear success after sw reset\n");
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return;
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}
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msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT);
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end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT;
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}
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dev_warn(hr_dev->dev, "Func clear failed because of unfinished sw reset\n");
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} else {
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if (retval && !flag)
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dev_warn(hr_dev->dev,
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"Func clear read failed, ret = %d.\n", retval);
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dev_warn(hr_dev->dev, "Func clear failed.\n");
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return;
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}
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if (ops->get_hw_reset_stat(handle)) {
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func_clr_hw_resetting_state(hr_dev, handle);
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return;
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}
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if (ops->ae_dev_resetting(handle) &&
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handle->rinfo.instance_state == HNS_ROCE_STATE_INIT) {
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func_clr_sw_resetting_state(hr_dev, handle);
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return;
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}
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if (retval && !flag)
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dev_warn(hr_dev->dev,
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"Func clear read failed, ret = %d.\n", retval);
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|
||||
dev_warn(hr_dev->dev, "Func clear failed.\n");
|
||||
}
|
||||
|
||||
static void hns_roce_function_clear(struct hns_roce_dev *hr_dev)
|
||||
{
|
||||
bool fclr_write_fail_flag = false;
|
||||
|
|
@ -1481,7 +1509,7 @@ static void hns_roce_function_clear(struct hns_roce_dev *hr_dev)
|
|||
unsigned long end;
|
||||
int ret = 0;
|
||||
|
||||
if (hns_roce_func_clr_chk_rst(hr_dev))
|
||||
if (check_device_is_in_reset(hr_dev))
|
||||
goto out;
|
||||
|
||||
hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, false);
|
||||
|
|
@ -1498,7 +1526,7 @@ static void hns_roce_function_clear(struct hns_roce_dev *hr_dev)
|
|||
msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL);
|
||||
end = HNS_ROCE_V2_FUNC_CLEAR_TIMEOUT_MSECS;
|
||||
while (end) {
|
||||
if (hns_roce_func_clr_chk_rst(hr_dev))
|
||||
if (check_device_is_in_reset(hr_dev))
|
||||
goto out;
|
||||
msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT);
|
||||
end -= HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT;
|
||||
|
|
@ -1517,7 +1545,7 @@ static void hns_roce_function_clear(struct hns_roce_dev *hr_dev)
|
|||
}
|
||||
|
||||
out:
|
||||
hns_roce_func_clr_rst_prc(hr_dev, ret, fclr_write_fail_flag);
|
||||
hns_roce_func_clr_rst_proc(hr_dev, ret, fclr_write_fail_flag);
|
||||
}
|
||||
|
||||
static int hns_roce_query_fw_ver(struct hns_roce_dev *hr_dev)
|
||||
|
|
@ -2658,36 +2686,6 @@ static void hns_roce_v2_exit(struct hns_roce_dev *hr_dev)
|
|||
free_dip_list(hr_dev);
|
||||
}
|
||||
|
||||
static int hns_roce_query_mbox_status(struct hns_roce_dev *hr_dev)
|
||||
{
|
||||
struct hns_roce_cmq_desc desc;
|
||||
struct hns_roce_mbox_status *mb_st =
|
||||
(struct hns_roce_mbox_status *)desc.data;
|
||||
int status;
|
||||
|
||||
hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_MB_ST, true);
|
||||
|
||||
status = hns_roce_cmq_send(hr_dev, &desc, 1);
|
||||
if (status)
|
||||
return status;
|
||||
|
||||
return le32_to_cpu(mb_st->mb_status_hw_run);
|
||||
}
|
||||
|
||||
static int hns_roce_v2_cmd_pending(struct hns_roce_dev *hr_dev)
|
||||
{
|
||||
u32 status = hns_roce_query_mbox_status(hr_dev);
|
||||
|
||||
return status >> HNS_ROCE_HW_RUN_BIT_SHIFT;
|
||||
}
|
||||
|
||||
static int hns_roce_v2_cmd_complete(struct hns_roce_dev *hr_dev)
|
||||
{
|
||||
u32 status = hns_roce_query_mbox_status(hr_dev);
|
||||
|
||||
return status & HNS_ROCE_HW_MB_STATUS_MASK;
|
||||
}
|
||||
|
||||
static int hns_roce_mbox_post(struct hns_roce_dev *hr_dev, u64 in_param,
|
||||
u64 out_param, u32 in_modifier, u8 op_modifier,
|
||||
u16 op, u16 token, int event)
|
||||
|
|
@ -2707,58 +2705,97 @@ static int hns_roce_mbox_post(struct hns_roce_dev *hr_dev, u64 in_param,
|
|||
return hns_roce_cmq_send(hr_dev, &desc, 1);
|
||||
}
|
||||
|
||||
static int hns_roce_v2_post_mbox(struct hns_roce_dev *hr_dev, u64 in_param,
|
||||
u64 out_param, u32 in_modifier, u8 op_modifier,
|
||||
u16 op, u16 token, int event)
|
||||
static int v2_wait_mbox_complete(struct hns_roce_dev *hr_dev, u32 timeout,
|
||||
u8 *complete_status)
|
||||
{
|
||||
struct device *dev = hr_dev->dev;
|
||||
struct hns_roce_mbox_status *mb_st;
|
||||
struct hns_roce_cmq_desc desc;
|
||||
unsigned long end;
|
||||
int ret;
|
||||
int ret = -EBUSY;
|
||||
u32 status;
|
||||
bool busy;
|
||||
|
||||
end = msecs_to_jiffies(HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS) + jiffies;
|
||||
while (hns_roce_v2_cmd_pending(hr_dev)) {
|
||||
if (time_after(jiffies, end)) {
|
||||
dev_dbg(dev, "jiffies=%d end=%d\n", (int)jiffies,
|
||||
(int)end);
|
||||
return -EAGAIN;
|
||||
mb_st = (struct hns_roce_mbox_status *)desc.data;
|
||||
end = msecs_to_jiffies(timeout) + jiffies;
|
||||
while (v2_chk_mbox_is_avail(hr_dev, &busy)) {
|
||||
status = 0;
|
||||
hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_MB_ST,
|
||||
true);
|
||||
ret = __hns_roce_cmq_send(hr_dev, &desc, 1);
|
||||
if (!ret) {
|
||||
status = le32_to_cpu(mb_st->mb_status_hw_run);
|
||||
/* No pending message exists in ROCEE mbox. */
|
||||
if (!(status & MB_ST_HW_RUN_M))
|
||||
break;
|
||||
} else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) {
|
||||
break;
|
||||
}
|
||||
|
||||
if (time_after(jiffies, end)) {
|
||||
dev_err_ratelimited(hr_dev->dev,
|
||||
"failed to wait mbox status 0x%x\n",
|
||||
status);
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
cond_resched();
|
||||
ret = -EBUSY;
|
||||
}
|
||||
|
||||
ret = hns_roce_mbox_post(hr_dev, in_param, out_param, in_modifier,
|
||||
op_modifier, op, token, event);
|
||||
if (ret)
|
||||
dev_err(dev, "Post mailbox fail(%d)\n", ret);
|
||||
if (!ret) {
|
||||
*complete_status = (u8)(status & MB_ST_COMPLETE_M);
|
||||
} else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) {
|
||||
/* Ignore all errors if the mbox is unavailable. */
|
||||
ret = 0;
|
||||
*complete_status = MB_ST_COMPLETE_M;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int hns_roce_v2_chk_mbox(struct hns_roce_dev *hr_dev,
|
||||
unsigned int timeout)
|
||||
static int v2_post_mbox(struct hns_roce_dev *hr_dev, u64 in_param,
|
||||
u64 out_param, u32 in_modifier, u8 op_modifier,
|
||||
u16 op, u16 token, int event)
|
||||
{
|
||||
struct device *dev = hr_dev->dev;
|
||||
unsigned long end;
|
||||
u32 status;
|
||||
u8 status = 0;
|
||||
int ret;
|
||||
|
||||
end = msecs_to_jiffies(timeout) + jiffies;
|
||||
while (hns_roce_v2_cmd_pending(hr_dev) && time_before(jiffies, end))
|
||||
cond_resched();
|
||||
|
||||
if (hns_roce_v2_cmd_pending(hr_dev)) {
|
||||
dev_err(dev, "[cmd_poll]hw run cmd TIMEDOUT!\n");
|
||||
return -ETIMEDOUT;
|
||||
/* Waiting for the mbox to be idle */
|
||||
ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS,
|
||||
&status);
|
||||
if (unlikely(ret)) {
|
||||
dev_err_ratelimited(hr_dev->dev,
|
||||
"failed to check post mbox status = 0x%x, ret = %d.\n",
|
||||
status, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
status = hns_roce_v2_cmd_complete(hr_dev);
|
||||
if (status != 0x1) {
|
||||
if (status == CMD_RST_PRC_EBUSY)
|
||||
return status;
|
||||
/* Post new message to mbox */
|
||||
ret = hns_roce_mbox_post(hr_dev, in_param, out_param, in_modifier,
|
||||
op_modifier, op, token, event);
|
||||
if (ret)
|
||||
dev_err_ratelimited(hr_dev->dev,
|
||||
"failed to post mailbox, ret = %d.\n", ret);
|
||||
|
||||
dev_err(dev, "mailbox status 0x%x!\n", status);
|
||||
return -EBUSY;
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int v2_poll_mbox_done(struct hns_roce_dev *hr_dev, unsigned int timeout)
|
||||
{
|
||||
u8 status = 0;
|
||||
int ret;
|
||||
|
||||
ret = v2_wait_mbox_complete(hr_dev, timeout, &status);
|
||||
if (!ret) {
|
||||
if (status != MB_ST_COMPLETE_SUCC)
|
||||
return -EBUSY;
|
||||
} else {
|
||||
dev_err_ratelimited(hr_dev->dev,
|
||||
"failed to check mbox status = 0x%x, ret = %d.\n",
|
||||
status, ret);
|
||||
}
|
||||
|
||||
return 0;
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void copy_gid(void *dest, const union ib_gid *gid)
|
||||
|
|
@ -6453,6 +6490,8 @@ static void hns_roce_v2_cleanup_eq_table(struct hns_roce_dev *hr_dev)
|
|||
hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE);
|
||||
|
||||
__hns_roce_free_irq(hr_dev);
|
||||
flush_workqueue(hr_dev->irq_workq);
|
||||
destroy_workqueue(hr_dev->irq_workq);
|
||||
|
||||
for (i = 0; i < eq_num; i++) {
|
||||
hns_roce_v2_destroy_eqc(hr_dev, i);
|
||||
|
|
@ -6461,9 +6500,6 @@ static void hns_roce_v2_cleanup_eq_table(struct hns_roce_dev *hr_dev)
|
|||
}
|
||||
|
||||
kfree(eq_table->eq);
|
||||
|
||||
flush_workqueue(hr_dev->irq_workq);
|
||||
destroy_workqueue(hr_dev->irq_workq);
|
||||
}
|
||||
|
||||
static const struct hns_roce_dfx_hw hns_roce_dfx_hw_v2 = {
|
||||
|
|
@ -6492,9 +6528,9 @@ static const struct hns_roce_hw hns_roce_hw_v2 = {
|
|||
.hw_profile = hns_roce_v2_profile,
|
||||
.hw_init = hns_roce_v2_init,
|
||||
.hw_exit = hns_roce_v2_exit,
|
||||
.post_mbox = hns_roce_v2_post_mbox,
|
||||
.chk_mbox = hns_roce_v2_chk_mbox,
|
||||
.rst_prc_mbox = hns_roce_v2_rst_process_cmd,
|
||||
.post_mbox = v2_post_mbox,
|
||||
.poll_mbox_done = v2_poll_mbox_done,
|
||||
.chk_mbox_avail = v2_chk_mbox_is_avail,
|
||||
.set_gid = hns_roce_v2_set_gid,
|
||||
.set_mac = hns_roce_v2_set_mac,
|
||||
.write_mtpt = hns_roce_v2_write_mtpt,
|
||||
|
|
|
|||
|
|
@ -1588,6 +1588,13 @@ struct hns_roce_mbox_status {
|
|||
__le32 rsv[5];
|
||||
};
|
||||
|
||||
#define HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS 10000
|
||||
|
||||
#define MB_ST_HW_RUN_M BIT(31)
|
||||
#define MB_ST_COMPLETE_M GENMASK(7, 0)
|
||||
|
||||
#define MB_ST_COMPLETE_SUCC 1
|
||||
|
||||
struct hns_roce_cfg_bt_attr {
|
||||
__le32 vf_qpc_cfg;
|
||||
__le32 vf_srqc_cfg;
|
||||
|
|
@ -1893,11 +1900,6 @@ struct hns_roce_cmq_desc {
|
|||
|
||||
};
|
||||
|
||||
#define HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS 10000
|
||||
|
||||
#define HNS_ROCE_HW_RUN_BIT_SHIFT 31
|
||||
#define HNS_ROCE_HW_MB_STATUS_MASK 0xFF
|
||||
|
||||
struct hns_roce_v2_cmq_ring {
|
||||
dma_addr_t desc_dma_addr;
|
||||
struct hns_roce_cmq_desc *desc;
|
||||
|
|
|
|||
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