drm/radeon: remove gui_idle interrupt infrastructure
It was only used for dynpm, but has been replaced with a better implementation using fences. Remove it. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Родитель
95f5a3acfa
Коммит
ee93b86be1
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@ -2528,10 +2528,6 @@ int evergreen_irq_set(struct radeon_device *rdev)
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DRM_DEBUG("evergreen_irq_set: hdmi 5\n");
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afmt6 |= AFMT_AZ_FORMAT_WTRIG_MASK;
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}
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if (rdev->irq.gui_idle) {
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DRM_DEBUG("gui idle\n");
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grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
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}
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if (rdev->family >= CHIP_CAYMAN) {
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cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl);
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@ -3066,7 +3062,6 @@ restart_ih:
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break;
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case 233: /* GUI IDLE */
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DRM_DEBUG("IH: GUI idle\n");
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wake_up(&rdev->irq.idle_queue);
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break;
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default:
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DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
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@ -700,9 +700,6 @@ int r100_irq_set(struct radeon_device *rdev)
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if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
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tmp |= RADEON_SW_INT_ENABLE;
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}
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if (rdev->irq.gui_idle) {
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tmp |= RADEON_GUI_IDLE_MASK;
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}
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if (rdev->irq.crtc_vblank_int[0] ||
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atomic_read(&rdev->irq.pflip[0])) {
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tmp |= RADEON_CRTC_VBLANK_MASK;
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@ -739,12 +736,6 @@ static uint32_t r100_irq_ack(struct radeon_device *rdev)
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RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
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RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
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/* the interrupt works, but the status bit is permanently asserted */
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if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
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if (!rdev->irq.gui_idle_acked)
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irq_mask |= RADEON_GUI_IDLE_STAT;
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}
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if (irqs) {
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WREG32(RADEON_GEN_INT_STATUS, irqs);
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}
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@ -756,9 +747,6 @@ int r100_irq_process(struct radeon_device *rdev)
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uint32_t status, msi_rearm;
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bool queue_hotplug = false;
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/* reset gui idle ack. the status bit is broken */
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rdev->irq.gui_idle_acked = false;
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status = r100_irq_ack(rdev);
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if (!status) {
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return IRQ_NONE;
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@ -771,11 +759,6 @@ int r100_irq_process(struct radeon_device *rdev)
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if (status & RADEON_SW_INT_TEST) {
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radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
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}
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/* gui idle interrupt */
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if (status & RADEON_GUI_IDLE_STAT) {
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rdev->irq.gui_idle_acked = true;
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wake_up(&rdev->irq.idle_queue);
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}
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/* Vertical blank interrupts */
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if (status & RADEON_CRTC_VBLANK_STAT) {
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if (rdev->irq.crtc_vblank_int[0]) {
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@ -805,8 +788,6 @@ int r100_irq_process(struct radeon_device *rdev)
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}
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status = r100_irq_ack(rdev);
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}
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/* reset gui idle ack. the status bit is broken */
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rdev->irq.gui_idle_acked = false;
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if (queue_hotplug)
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schedule_work(&rdev->hotplug_work);
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if (rdev->msi_enabled) {
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@ -3088,10 +3088,6 @@ int r600_irq_set(struct radeon_device *rdev)
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DRM_DEBUG("r600_irq_set: hdmi 0\n");
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hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
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}
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if (rdev->irq.gui_idle) {
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DRM_DEBUG("gui idle\n");
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grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
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}
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WREG32(CP_INT_CNTL, cp_int_cntl);
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WREG32(DxMODE_INT_MASK, mode_int);
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@ -3475,7 +3471,6 @@ restart_ih:
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break;
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case 233: /* GUI IDLE */
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DRM_DEBUG("IH: GUI idle\n");
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wake_up(&rdev->irq.idle_queue);
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break;
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default:
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DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
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@ -566,9 +566,6 @@ struct radeon_irq {
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atomic_t pflip[RADEON_MAX_CRTCS];
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wait_queue_head_t vblank_queue;
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bool hpd[RADEON_MAX_HPD_PINS];
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bool gui_idle;
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bool gui_idle_acked;
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wait_queue_head_t idle_queue;
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bool afmt[RADEON_MAX_AFMT_BLOCKS];
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union radeon_irq_stat_regs stat_regs;
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};
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@ -583,7 +580,6 @@ void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
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void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
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void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
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void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
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int radeon_irq_kms_wait_gui_idle(struct radeon_device *rdev);
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/*
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* CP & rings.
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@ -1013,7 +1013,6 @@ int radeon_device_init(struct radeon_device *rdev,
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init_rwsem(&rdev->pm.mclk_lock);
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init_rwsem(&rdev->exclusive_lock);
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init_waitqueue_head(&rdev->irq.vblank_queue);
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init_waitqueue_head(&rdev->irq.idle_queue);
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r = radeon_gem_init(rdev);
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if (r)
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return r;
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@ -99,7 +99,6 @@ void radeon_driver_irq_preinstall_kms(struct drm_device *dev)
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/* Disable *all* interrupts */
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for (i = 0; i < RADEON_NUM_RINGS; i++)
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atomic_set(&rdev->irq.ring_int[i], 0);
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rdev->irq.gui_idle = false;
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for (i = 0; i < RADEON_MAX_HPD_PINS; i++)
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rdev->irq.hpd[i] = false;
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for (i = 0; i < RADEON_MAX_CRTCS; i++) {
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@ -147,7 +146,6 @@ void radeon_driver_irq_uninstall_kms(struct drm_device *dev)
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/* Disable *all* interrupts */
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for (i = 0; i < RADEON_NUM_RINGS; i++)
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atomic_set(&rdev->irq.ring_int[i], 0);
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rdev->irq.gui_idle = false;
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for (i = 0; i < RADEON_MAX_HPD_PINS; i++)
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rdev->irq.hpd[i] = false;
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for (i = 0; i < RADEON_MAX_CRTCS; i++) {
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@ -457,34 +455,3 @@ void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask)
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spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
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}
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/**
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* radeon_irq_kms_wait_gui_idle - waits for drawing engine to be idle
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*
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* @rdev: radeon device pointer
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*
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* Enabled the GUI idle interrupt and waits for it to fire (r6xx+).
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* This is currently used to make sure the 3D engine is idle for power
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* management, but should be replaces with proper fence waits.
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* GUI idle interrupts don't work very well on pre-r6xx hw and it also
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* does not take into account other aspects of the chip that may be busy.
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* DO NOT USE GOING FORWARD.
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*/
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int radeon_irq_kms_wait_gui_idle(struct radeon_device *rdev)
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{
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unsigned long irqflags;
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int r;
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spin_lock_irqsave(&rdev->irq.lock, irqflags);
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rdev->irq.gui_idle = true;
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radeon_irq_set(rdev);
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spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
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r = wait_event_timeout(rdev->irq.idle_queue, radeon_gui_idle(rdev),
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msecs_to_jiffies(RADEON_WAIT_IDLE_TIMEOUT));
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spin_lock_irqsave(&rdev->irq.lock, irqflags);
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rdev->irq.gui_idle = false;
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radeon_irq_set(rdev);
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spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
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return r;
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}
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@ -575,9 +575,6 @@ int rs600_irq_set(struct radeon_device *rdev)
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if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
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tmp |= S_000040_SW_INT_EN(1);
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}
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if (rdev->irq.gui_idle) {
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tmp |= S_000040_GUI_IDLE(1);
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}
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if (rdev->irq.crtc_vblank_int[0] ||
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atomic_read(&rdev->irq.pflip[0])) {
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mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1);
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@ -610,12 +607,6 @@ static inline u32 rs600_irq_ack(struct radeon_device *rdev)
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uint32_t irq_mask = S_000044_SW_INT(1);
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u32 tmp;
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/* the interrupt works, but the status bit is permanently asserted */
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if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
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if (!rdev->irq.gui_idle_acked)
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irq_mask |= S_000044_GUI_IDLE_STAT(1);
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}
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if (G_000044_DISPLAY_INT_STAT(irqs)) {
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rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
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if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
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@ -675,9 +666,6 @@ int rs600_irq_process(struct radeon_device *rdev)
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bool queue_hotplug = false;
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bool queue_hdmi = false;
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/* reset gui idle ack. the status bit is broken */
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rdev->irq.gui_idle_acked = false;
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status = rs600_irq_ack(rdev);
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if (!status &&
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!rdev->irq.stat_regs.r500.disp_int &&
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@ -691,11 +679,6 @@ int rs600_irq_process(struct radeon_device *rdev)
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if (G_000044_SW_INT(status)) {
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radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
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}
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/* GUI idle */
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if (G_000040_GUI_IDLE(status)) {
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rdev->irq.gui_idle_acked = true;
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wake_up(&rdev->irq.idle_queue);
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}
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/* Vertical blank interrupts */
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if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
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if (rdev->irq.crtc_vblank_int[0]) {
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@ -729,8 +712,6 @@ int rs600_irq_process(struct radeon_device *rdev)
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}
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status = rs600_irq_ack(rdev);
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}
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/* reset gui idle ack. the status bit is broken */
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rdev->irq.gui_idle_acked = false;
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if (queue_hotplug)
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schedule_work(&rdev->hotplug_work);
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if (queue_hdmi)
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@ -3199,10 +3199,6 @@ int si_irq_set(struct radeon_device *rdev)
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DRM_DEBUG("si_irq_set: hpd 6\n");
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hpd6 |= DC_HPDx_INT_EN;
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}
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if (rdev->irq.gui_idle) {
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DRM_DEBUG("gui idle\n");
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grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
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}
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WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
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WREG32(CP_INT_CNTL_RING1, cp_int_cntl1);
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@ -3658,7 +3654,6 @@ restart_ih:
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break;
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case 233: /* GUI IDLE */
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DRM_DEBUG("IH: GUI idle\n");
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wake_up(&rdev->irq.idle_queue);
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break;
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default:
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DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
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