[POWERPC] MPC5200 low power mode
Low-power mode implementation for Lite5200b. Some I/O registers are also saved here. A recent U-Boot that supports this (lite5200b_PM_config) is needed. Signed-off-by: Domen Puncer <domen.puncer@telargo.com> Signed-off-by: Sylvain Munaut <tnt@246tNt.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Domen Puncer
Paul Mackerras
Родитель
104f0cc2dc
Коммит
ee983079ce
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@ -10,3 +10,6 @@ obj-$(CONFIG_PPC_EFIKA) += efika.o
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obj-$(CONFIG_PPC_LITE5200) += lite5200.o
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obj-$(CONFIG_PM) += mpc52xx_sleep.o mpc52xx_pm.o
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ifeq ($(CONFIG_PPC_LITE5200),y)
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obj-$(CONFIG_PM) += lite5200_sleep.o lite5200_pm.o
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endif
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@ -85,7 +85,6 @@ error:
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}
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#ifdef CONFIG_PM
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static u32 descr_a;
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static void lite5200_suspend_prepare(void __iomem *mbar)
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{
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u8 pin = 1; /* GPIO_WKUP_1 (GPIO_PSC2_4) */
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@ -96,13 +95,18 @@ static void lite5200_suspend_prepare(void __iomem *mbar)
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* power down usb port
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* this needs to be called before of-ohci suspend code
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*/
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descr_a = in_be32(mbar + 0x1048);
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out_be32(mbar + 0x1048, (descr_a & ~0x200) | 0x100);
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/* set ports to "power switched" and "powered at the same time"
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* USB Rh descriptor A: NPS = 0, PSM = 0 */
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out_be32(mbar + 0x1048, in_be32(mbar + 0x1048) & ~0x300);
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/* USB Rh status: LPS = 1 - turn off power */
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out_be32(mbar + 0x1050, 0x00000001);
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}
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static void lite5200_resume_finish(void __iomem *mbar)
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{
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out_be32(mbar + 0x1048, descr_a);
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/* USB Rh status: LPSC = 1 - turn on power */
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out_be32(mbar + 0x1050, 0x00010000);
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}
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#endif
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@ -122,7 +126,7 @@ static void __init lite5200_setup_arch(void)
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#ifdef CONFIG_PM
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mpc52xx_suspend.board_suspend_prepare = lite5200_suspend_prepare;
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mpc52xx_suspend.board_resume_finish = lite5200_resume_finish;
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mpc52xx_pm_init();
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lite5200_pm_init();
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#endif
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#ifdef CONFIG_PCI
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@ -0,0 +1,213 @@
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#include <linux/init.h>
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#include <linux/pm.h>
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#include <asm/io.h>
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#include <asm/time.h>
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#include <asm/mpc52xx.h>
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#include "mpc52xx_pic.h"
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/* defined in lite5200_sleep.S and only used here */
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extern void lite5200_low_power(void __iomem *sram, void __iomem *mbar);
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static struct mpc52xx_cdm __iomem *cdm;
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static struct mpc52xx_intr __iomem *pic;
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static struct mpc52xx_sdma __iomem *bes;
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static struct mpc52xx_xlb __iomem *xlb;
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static struct mpc52xx_gpio __iomem *gps;
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static struct mpc52xx_gpio_wkup __iomem *gpw;
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static void __iomem *sram;
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static const int sram_size = 0x4000; /* 16 kBytes */
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static void __iomem *mbar;
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static int lite5200_pm_valid(suspend_state_t state)
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{
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switch (state) {
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case PM_SUSPEND_STANDBY:
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case PM_SUSPEND_MEM:
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return 1;
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default:
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return 0;
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}
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}
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static int lite5200_pm_prepare(suspend_state_t state)
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{
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/* deep sleep? let mpc52xx code handle that */
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if (state == PM_SUSPEND_STANDBY)
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return mpc52xx_pm_prepare(state);
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if (state != PM_SUSPEND_MEM)
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return -EINVAL;
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/* map registers */
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mbar = mpc52xx_find_and_map("mpc5200");
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if (!mbar) {
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printk(KERN_ERR "%s:%i Error mapping registers\n", __func__, __LINE__);
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return -ENOSYS;
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}
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cdm = mbar + 0x200;
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pic = mbar + 0x500;
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gps = mbar + 0xb00;
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gpw = mbar + 0xc00;
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bes = mbar + 0x1200;
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xlb = mbar + 0x1f00;
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sram = mbar + 0x8000;
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return 0;
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}
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/* save and restore registers not bound to any real devices */
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static struct mpc52xx_cdm scdm;
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static struct mpc52xx_intr spic;
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static struct mpc52xx_sdma sbes;
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static struct mpc52xx_xlb sxlb;
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static struct mpc52xx_gpio sgps;
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static struct mpc52xx_gpio_wkup sgpw;
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static void lite5200_save_regs(void)
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{
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_memcpy_fromio(&spic, pic, sizeof(*pic));
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_memcpy_fromio(&sbes, bes, sizeof(*bes));
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_memcpy_fromio(&scdm, cdm, sizeof(*cdm));
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_memcpy_fromio(&sxlb, xlb, sizeof(*xlb));
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_memcpy_fromio(&sgps, gps, sizeof(*gps));
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_memcpy_fromio(&sgpw, gpw, sizeof(*gpw));
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_memcpy_fromio(saved_sram, sram, sram_size);
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}
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static void lite5200_restore_regs(void)
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{
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int i;
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_memcpy_toio(sram, saved_sram, sram_size);
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/*
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* GPIOs. Interrupt Master Enable has higher address then other
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* registers, so just memcpy is ok.
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*/
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_memcpy_toio(gpw, &sgpw, sizeof(*gpw));
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_memcpy_toio(gps, &sgps, sizeof(*gps));
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/* XLB Arbitrer */
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out_be32(&xlb->snoop_window, sxlb.snoop_window);
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out_be32(&xlb->master_priority, sxlb.master_priority);
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out_be32(&xlb->master_pri_enable, sxlb.master_pri_enable);
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/* enable */
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out_be32(&xlb->int_enable, sxlb.int_enable);
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out_be32(&xlb->config, sxlb.config);
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/* CDM - Clock Distribution Module */
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out_8(&cdm->ipb_clk_sel, scdm.ipb_clk_sel);
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out_8(&cdm->pci_clk_sel, scdm.pci_clk_sel);
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out_8(&cdm->ext_48mhz_en, scdm.ext_48mhz_en);
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out_8(&cdm->fd_enable, scdm.fd_enable);
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out_be16(&cdm->fd_counters, scdm.fd_counters);
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out_be32(&cdm->clk_enables, scdm.clk_enables);
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out_8(&cdm->osc_disable, scdm.osc_disable);
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out_be16(&cdm->mclken_div_psc1, scdm.mclken_div_psc1);
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out_be16(&cdm->mclken_div_psc2, scdm.mclken_div_psc2);
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out_be16(&cdm->mclken_div_psc3, scdm.mclken_div_psc3);
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out_be16(&cdm->mclken_div_psc6, scdm.mclken_div_psc6);
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/* BESTCOMM */
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out_be32(&bes->taskBar, sbes.taskBar);
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out_be32(&bes->currentPointer, sbes.currentPointer);
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out_be32(&bes->endPointer, sbes.endPointer);
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out_be32(&bes->variablePointer, sbes.variablePointer);
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out_8(&bes->IntVect1, sbes.IntVect1);
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out_8(&bes->IntVect2, sbes.IntVect2);
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out_be16(&bes->PtdCntrl, sbes.PtdCntrl);
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for (i=0; i<32; i++)
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out_8(&bes->ipr[i], sbes.ipr[i]);
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out_be32(&bes->cReqSelect, sbes.cReqSelect);
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out_be32(&bes->task_size0, sbes.task_size0);
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out_be32(&bes->task_size1, sbes.task_size1);
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out_be32(&bes->MDEDebug, sbes.MDEDebug);
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out_be32(&bes->ADSDebug, sbes.ADSDebug);
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out_be32(&bes->Value1, sbes.Value1);
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out_be32(&bes->Value2, sbes.Value2);
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out_be32(&bes->Control, sbes.Control);
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out_be32(&bes->Status, sbes.Status);
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out_be32(&bes->PTDDebug, sbes.PTDDebug);
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/* restore tasks */
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for (i=0; i<16; i++)
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out_be16(&bes->tcr[i], sbes.tcr[i]);
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/* enable interrupts */
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out_be32(&bes->IntPend, sbes.IntPend);
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out_be32(&bes->IntMask, sbes.IntMask);
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/* PIC */
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out_be32(&pic->per_pri1, spic.per_pri1);
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out_be32(&pic->per_pri2, spic.per_pri2);
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out_be32(&pic->per_pri3, spic.per_pri3);
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out_be32(&pic->main_pri1, spic.main_pri1);
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out_be32(&pic->main_pri2, spic.main_pri2);
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out_be32(&pic->enc_status, spic.enc_status);
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/* unmask and enable interrupts */
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out_be32(&pic->per_mask, spic.per_mask);
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out_be32(&pic->main_mask, spic.main_mask);
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out_be32(&pic->ctrl, spic.ctrl);
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}
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static int lite5200_pm_enter(suspend_state_t state)
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{
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/* deep sleep? let mpc52xx code handle that */
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if (state == PM_SUSPEND_STANDBY) {
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return mpc52xx_pm_enter(state);
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}
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lite5200_save_regs();
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/* effectively save FP regs */
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enable_kernel_fp();
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lite5200_low_power(sram, mbar);
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lite5200_restore_regs();
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/* restart jiffies */
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wakeup_decrementer();
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iounmap(mbar);
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return 0;
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}
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static int lite5200_pm_finish(suspend_state_t state)
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{
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/* deep sleep? let mpc52xx code handle that */
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if (state == PM_SUSPEND_STANDBY) {
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return mpc52xx_pm_finish(state);
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}
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return 0;
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}
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static struct pm_ops lite5200_pm_ops = {
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.valid = lite5200_pm_valid,
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.prepare = lite5200_pm_prepare,
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.enter = lite5200_pm_enter,
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.finish = lite5200_pm_finish,
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};
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int __init lite5200_pm_init(void)
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{
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pm_set_ops(&lite5200_pm_ops);
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return 0;
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}
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@ -0,0 +1,412 @@
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#include <asm/reg.h>
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#include <asm/ppc_asm.h>
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#include <asm/processor.h>
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#include <asm/cache.h>
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#define SDRAM_CTRL 0x104
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#define SC_MODE_EN (1<<31)
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#define SC_CKE (1<<30)
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#define SC_REF_EN (1<<28)
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#define SC_SOFT_PRE (1<<1)
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#define GPIOW_GPIOE 0xc00
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#define GPIOW_DDR 0xc08
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#define GPIOW_DVO 0xc0c
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#define CDM_CE 0x214
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#define CDM_SDRAM (1<<3)
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/* helpers... beware: r10 and r4 are overwritten */
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#define SAVE_SPRN(reg, addr) \
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mfspr r10, SPRN_##reg; \
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stw r10, ((addr)*4)(r4);
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#define LOAD_SPRN(reg, addr) \
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lwz r10, ((addr)*4)(r4); \
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mtspr SPRN_##reg, r10; \
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sync; \
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isync;
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.data
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registers:
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.space 0x5c*4
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.text
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/* ---------------------------------------------------------------------- */
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/* low-power mode with help of M68HLC908QT1 */
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.globl lite5200_low_power
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lite5200_low_power:
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mr r7, r3 /* save SRAM va */
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mr r8, r4 /* save MBAR va */
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/* setup wakeup address for u-boot at physical location 0x0 */
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lis r3, CONFIG_KERNEL_START@h
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lis r4, lite5200_wakeup@h
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ori r4, r4, lite5200_wakeup@l
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sub r4, r4, r3
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stw r4, 0(r3)
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/*
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* save stuff BDI overwrites
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* 0xf0 (0xe0->0x100 gets overwritten when BDI connected;
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* even when CONFIG_BDI* is disabled and MMU XLAT commented; heisenbug?))
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* WARNING: self-refresh doesn't seem to work when BDI2000 is connected,
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* possibly because BDI sets SDRAM registers before wakeup code does
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*/
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lis r4, registers@h
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ori r4, r4, registers@l
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lwz r10, 0xf0(r3)
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stw r10, (0x1d*4)(r4)
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/* save registers to r4 [destroys r10] */
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SAVE_SPRN(LR, 0x1c)
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bl save_regs
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/* flush caches [destroys r3, r4] */
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bl flush_data_cache
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/* copy code to sram */
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mr r4, r7
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li r3, (sram_code_end - sram_code)/4
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mtctr r3
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lis r3, sram_code@h
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ori r3, r3, sram_code@l
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1:
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lwz r5, 0(r3)
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stw r5, 0(r4)
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addi r3, r3, 4
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addi r4, r4, 4
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bdnz 1b
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/* get tb_ticks_per_usec */
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lis r3, tb_ticks_per_usec@h
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lwz r11, tb_ticks_per_usec@l(r3)
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/* disable I and D caches */
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mfspr r3, SPRN_HID0
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ori r3, r3, HID0_ICE | HID0_DCE
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xori r3, r3, HID0_ICE | HID0_DCE
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sync; isync;
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mtspr SPRN_HID0, r3
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sync; isync;
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/* jump to sram */
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mtlr r7
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blrl
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/* doesn't return */
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sram_code:
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/* self refresh */
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lwz r4, SDRAM_CTRL(r8)
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/* send NOP (precharge) */
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oris r4, r4, SC_MODE_EN@h /* mode_en */
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stw r4, SDRAM_CTRL(r8)
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sync
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ori r4, r4, SC_SOFT_PRE /* soft_pre */
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stw r4, SDRAM_CTRL(r8)
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sync
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xori r4, r4, SC_SOFT_PRE
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xoris r4, r4, SC_MODE_EN@h /* !mode_en */
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stw r4, SDRAM_CTRL(r8)
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sync
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/* delay (for NOP to finish) */
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li r12, 1
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bl udelay
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/*
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* mode_en must not be set when enabling self-refresh
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* send AR with CKE low (self-refresh)
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*/
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oris r4, r4, (SC_REF_EN | SC_CKE)@h
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xoris r4, r4, (SC_CKE)@h /* ref_en !cke */
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stw r4, SDRAM_CTRL(r8)
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sync
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/* delay (after !CKE there should be two cycles) */
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li r12, 1
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bl udelay
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/* disable clock */
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lwz r4, CDM_CE(r8)
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ori r4, r4, CDM_SDRAM
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xori r4, r4, CDM_SDRAM
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stw r4, CDM_CE(r8)
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sync
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/* delay a bit */
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li r12, 1
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bl udelay
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/* turn off with QT chip */
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li r4, 0x02
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stb r4, GPIOW_GPIOE(r8) /* enable gpio_wkup1 */
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sync
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stb r4, GPIOW_DVO(r8) /* "output" high */
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sync
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stb r4, GPIOW_DDR(r8) /* output */
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sync
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stb r4, GPIOW_DVO(r8) /* output high */
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sync
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/* 10uS delay */
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li r12, 10
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bl udelay
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/* turn off */
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li r4, 0
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stb r4, GPIOW_DVO(r8) /* output low */
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sync
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/* wait until we're offline */
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1:
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b 1b
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/* local udelay in sram is needed */
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udelay: /* r11 - tb_ticks_per_usec, r12 - usecs, overwrites r13 */
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mullw r12, r12, r11
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mftb r13 /* start */
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addi r12, r13, r12 /* end */
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1:
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mftb r13 /* current */
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cmp cr0, r13, r12
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blt 1b
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blr
|
||||
|
||||
sram_code_end:
|
||||
|
||||
|
||||
|
||||
/* uboot jumps here on resume */
|
||||
lite5200_wakeup:
|
||||
bl restore_regs
|
||||
|
||||
|
||||
/* HIDs, MSR */
|
||||
LOAD_SPRN(HID1, 0x19)
|
||||
LOAD_SPRN(HID2, 0x1a)
|
||||
|
||||
|
||||
/* address translation is tricky (see turn_on_mmu) */
|
||||
mfmsr r10
|
||||
ori r10, r10, MSR_DR | MSR_IR
|
||||
|
||||
|
||||
mtspr SPRN_SRR1, r10
|
||||
lis r10, mmu_on@h
|
||||
ori r10, r10, mmu_on@l
|
||||
mtspr SPRN_SRR0, r10
|
||||
sync
|
||||
rfi
|
||||
mmu_on:
|
||||
/* kernel offset (r4 is still set from restore_registers) */
|
||||
addis r4, r4, CONFIG_KERNEL_START@h
|
||||
|
||||
|
||||
/* restore MSR */
|
||||
lwz r10, (4*0x1b)(r4)
|
||||
mtmsr r10
|
||||
sync; isync;
|
||||
|
||||
/* invalidate caches */
|
||||
mfspr r10, SPRN_HID0
|
||||
ori r5, r10, HID0_ICFI | HID0_DCI
|
||||
mtspr SPRN_HID0, r5 /* invalidate caches */
|
||||
sync; isync;
|
||||
mtspr SPRN_HID0, r10
|
||||
sync; isync;
|
||||
|
||||
/* enable caches */
|
||||
lwz r10, (4*0x18)(r4)
|
||||
mtspr SPRN_HID0, r10 /* restore (enable caches, DPM) */
|
||||
/* ^ this has to be after address translation set in MSR */
|
||||
sync
|
||||
isync
|
||||
|
||||
|
||||
/* restore 0xf0 (BDI2000) */
|
||||
lis r3, CONFIG_KERNEL_START@h
|
||||
lwz r10, (0x1d*4)(r4)
|
||||
stw r10, 0xf0(r3)
|
||||
|
||||
LOAD_SPRN(LR, 0x1c)
|
||||
|
||||
|
||||
blr
|
||||
|
||||
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/* boring code: helpers */
|
||||
|
||||
/* save registers */
|
||||
#define SAVE_BAT(n, addr) \
|
||||
SAVE_SPRN(DBAT##n##L, addr); \
|
||||
SAVE_SPRN(DBAT##n##U, addr+1); \
|
||||
SAVE_SPRN(IBAT##n##L, addr+2); \
|
||||
SAVE_SPRN(IBAT##n##U, addr+3);
|
||||
|
||||
#define SAVE_SR(n, addr) \
|
||||
mfsr r10, n; \
|
||||
stw r10, ((addr)*4)(r4);
|
||||
|
||||
#define SAVE_4SR(n, addr) \
|
||||
SAVE_SR(n, addr); \
|
||||
SAVE_SR(n+1, addr+1); \
|
||||
SAVE_SR(n+2, addr+2); \
|
||||
SAVE_SR(n+3, addr+3);
|
||||
|
||||
save_regs:
|
||||
stw r0, 0(r4)
|
||||
stw r1, 0x4(r4)
|
||||
stw r2, 0x8(r4)
|
||||
stmw r11, 0xc(r4) /* 0xc -> 0x5f, (0x18*4-1) */
|
||||
|
||||
SAVE_SPRN(HID0, 0x18)
|
||||
SAVE_SPRN(HID1, 0x19)
|
||||
SAVE_SPRN(HID2, 0x1a)
|
||||
mfmsr r10
|
||||
stw r10, (4*0x1b)(r4)
|
||||
/*SAVE_SPRN(LR, 0x1c) have to save it before the call */
|
||||
/* 0x1d reserved by 0xf0 */
|
||||
SAVE_SPRN(RPA, 0x1e)
|
||||
SAVE_SPRN(SDR1, 0x1f)
|
||||
|
||||
/* save MMU regs */
|
||||
SAVE_BAT(0, 0x20)
|
||||
SAVE_BAT(1, 0x24)
|
||||
SAVE_BAT(2, 0x28)
|
||||
SAVE_BAT(3, 0x2c)
|
||||
SAVE_BAT(4, 0x30)
|
||||
SAVE_BAT(5, 0x34)
|
||||
SAVE_BAT(6, 0x38)
|
||||
SAVE_BAT(7, 0x3c)
|
||||
|
||||
SAVE_4SR(0, 0x40)
|
||||
SAVE_4SR(4, 0x44)
|
||||
SAVE_4SR(8, 0x48)
|
||||
SAVE_4SR(12, 0x4c)
|
||||
|
||||
SAVE_SPRN(SPRG0, 0x50)
|
||||
SAVE_SPRN(SPRG1, 0x51)
|
||||
SAVE_SPRN(SPRG2, 0x52)
|
||||
SAVE_SPRN(SPRG3, 0x53)
|
||||
SAVE_SPRN(SPRG4, 0x54)
|
||||
SAVE_SPRN(SPRG5, 0x55)
|
||||
SAVE_SPRN(SPRG6, 0x56)
|
||||
SAVE_SPRN(SPRG7, 0x57)
|
||||
|
||||
SAVE_SPRN(IABR, 0x58)
|
||||
SAVE_SPRN(DABR, 0x59)
|
||||
SAVE_SPRN(TBRL, 0x5a)
|
||||
SAVE_SPRN(TBRU, 0x5b)
|
||||
|
||||
blr
|
||||
|
||||
|
||||
/* restore registers */
|
||||
#define LOAD_BAT(n, addr) \
|
||||
LOAD_SPRN(DBAT##n##L, addr); \
|
||||
LOAD_SPRN(DBAT##n##U, addr+1); \
|
||||
LOAD_SPRN(IBAT##n##L, addr+2); \
|
||||
LOAD_SPRN(IBAT##n##U, addr+3);
|
||||
|
||||
#define LOAD_SR(n, addr) \
|
||||
lwz r10, ((addr)*4)(r4); \
|
||||
mtsr n, r10;
|
||||
|
||||
#define LOAD_4SR(n, addr) \
|
||||
LOAD_SR(n, addr); \
|
||||
LOAD_SR(n+1, addr+1); \
|
||||
LOAD_SR(n+2, addr+2); \
|
||||
LOAD_SR(n+3, addr+3);
|
||||
|
||||
restore_regs:
|
||||
lis r4, registers@h
|
||||
ori r4, r4, registers@l
|
||||
|
||||
/* MMU is not up yet */
|
||||
subis r4, r4, CONFIG_KERNEL_START@h
|
||||
|
||||
lwz r0, 0(r4)
|
||||
lwz r1, 0x4(r4)
|
||||
lwz r2, 0x8(r4)
|
||||
lmw r11, 0xc(r4)
|
||||
|
||||
/*
|
||||
* these are a bit tricky
|
||||
*
|
||||
* 0x18 - HID0
|
||||
* 0x19 - HID1
|
||||
* 0x1a - HID2
|
||||
* 0x1b - MSR
|
||||
* 0x1c - LR
|
||||
* 0x1d - reserved by 0xf0 (BDI2000)
|
||||
*/
|
||||
LOAD_SPRN(RPA, 0x1e);
|
||||
LOAD_SPRN(SDR1, 0x1f);
|
||||
|
||||
/* restore MMU regs */
|
||||
LOAD_BAT(0, 0x20)
|
||||
LOAD_BAT(1, 0x24)
|
||||
LOAD_BAT(2, 0x28)
|
||||
LOAD_BAT(3, 0x2c)
|
||||
LOAD_BAT(4, 0x30)
|
||||
LOAD_BAT(5, 0x34)
|
||||
LOAD_BAT(6, 0x38)
|
||||
LOAD_BAT(7, 0x3c)
|
||||
|
||||
LOAD_4SR(0, 0x40)
|
||||
LOAD_4SR(4, 0x44)
|
||||
LOAD_4SR(8, 0x48)
|
||||
LOAD_4SR(12, 0x4c)
|
||||
|
||||
/* rest of regs */
|
||||
LOAD_SPRN(SPRG0, 0x50);
|
||||
LOAD_SPRN(SPRG1, 0x51);
|
||||
LOAD_SPRN(SPRG2, 0x52);
|
||||
LOAD_SPRN(SPRG3, 0x53);
|
||||
LOAD_SPRN(SPRG4, 0x54);
|
||||
LOAD_SPRN(SPRG5, 0x55);
|
||||
LOAD_SPRN(SPRG6, 0x56);
|
||||
LOAD_SPRN(SPRG7, 0x57);
|
||||
|
||||
LOAD_SPRN(IABR, 0x58);
|
||||
LOAD_SPRN(DABR, 0x59);
|
||||
LOAD_SPRN(TBWL, 0x5a); /* these two have separate R/W regs */
|
||||
LOAD_SPRN(TBWU, 0x5b);
|
||||
|
||||
blr
|
||||
|
||||
|
||||
|
||||
/* cache flushing code. copied from arch/ppc/boot/util.S */
|
||||
#define NUM_CACHE_LINES (128*8)
|
||||
|
||||
/*
|
||||
* Flush data cache
|
||||
* Do this by just reading lots of stuff into the cache.
|
||||
*/
|
||||
flush_data_cache:
|
||||
lis r3,CONFIG_KERNEL_START@h
|
||||
ori r3,r3,CONFIG_KERNEL_START@l
|
||||
li r4,NUM_CACHE_LINES
|
||||
mtctr r4
|
||||
1:
|
||||
lwz r4,0(r3)
|
||||
addi r3,r3,L1_CACHE_BYTES /* Next line, please */
|
||||
bdnz 1b
|
||||
blr
|
||||
|
|
@ -262,6 +262,16 @@ struct mpc52xx_suspend {
|
|||
extern struct mpc52xx_suspend mpc52xx_suspend;
|
||||
extern int __init mpc52xx_pm_init(void);
|
||||
extern int mpc52xx_set_wakeup_gpio(u8 pin, u8 level);
|
||||
|
||||
#ifdef CONFIG_PPC_LITE5200
|
||||
extern int __init lite5200_pm_init(void);
|
||||
|
||||
/* lite5200 calls mpc5200 suspend functions, so here they are */
|
||||
extern int mpc52xx_pm_prepare(suspend_state_t);
|
||||
extern int mpc52xx_pm_enter(suspend_state_t);
|
||||
extern int mpc52xx_pm_finish(suspend_state_t);
|
||||
extern char saved_sram[0x4000]; /* reuse buffer from mpc52xx suspend */
|
||||
#endif
|
||||
#endif /* CONFIG_PM */
|
||||
|
||||
#endif /* __ASM_POWERPC_MPC52xx_H__ */
|
||||
|
|
|
|||
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