ARM: msm: Rework timer binding to be more general
The msm timer binding I wrote is bad. First off, the clock frequency in the binding for the dgt is wrong. Software divides down the input rate by 4 to achieve the rate listed in the binding. We also treat each individual timer as a separate hardware component, when in reality there is one timer block (that may be duplicated per cpu) with multiple timers within it. Depending on the version of the hardware there can be one or two general purpose timers, status and divider control registers, and an entirely different register layout. In the next patch we'll need to know about the different register layouts so that we can properly check the status register after clearing the count. The current binding makes this complicated because the general purpose timer's reg property doesn't indicate where that status register is, and in fact it is beyond the size of the reg property. Clean all this up by just having one node for the timer hardware, and describe all the interrupts and clock frequencies supported while having one reg property that covers the entire timer register region. We'll use the compatible field in the future to determine different register layouts and if we should read the status registers, etc. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org>
This commit is contained in:
Stephen Boyd
David Brown
Родитель
f6161aa153
Коммит
eebdb0c1e1
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@ -3,36 +3,35 @@
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Properties:
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- compatible : Should at least contain "qcom,msm-timer". More specific
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properties such as "qcom,msm-gpt" and "qcom,msm-dgt" specify a general
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purpose timer and a debug timer respectively.
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properties specify which subsystem the timers are paired with.
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- interrupts : Interrupt indicating a match event.
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"qcom,kpss-timer" - krait subsystem
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"qcom,scss-timer" - scorpion subsystem
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- reg : Specifies the base address of the timer registers. The second region
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specifies an optional register used to configure the clock divider.
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- interrupts : Interrupts for the the debug timer, the first general purpose
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timer, and optionally a second general purpose timer in that
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order.
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- clock-frequency : The frequency of the timer in Hz.
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- reg : Specifies the base address of the timer registers.
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- clock-frequency : The frequency of the debug timer and the general purpose
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timer(s) in Hz in that order.
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Optional:
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- cpu-offset : per-cpu offset used when the timer is accessed without the
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CPU remapping facilities. The offset is cpu-offset * cpu-nr.
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CPU remapping facilities. The offset is
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cpu-offset + (0x10000 * cpu-nr).
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Example:
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timer@200a004 {
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compatible = "qcom,msm-gpt", "qcom,msm-timer";
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interrupts = <1 2 0x301>;
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reg = <0x0200a004 0x10>;
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clock-frequency = <32768>;
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cpu-offset = <0x40000>;
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};
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timer@200a024 {
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compatible = "qcom,msm-dgt", "qcom,msm-timer";
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interrupts = <1 3 0x301>;
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reg = <0x0200a024 0x10>,
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<0x0200a034 0x4>;
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clock-frequency = <6750000>;
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timer@200a000 {
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compatible = "qcom,scss-timer", "qcom,msm-timer";
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interrupts = <1 1 0x301>,
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<1 2 0x301>,
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<1 3 0x301>;
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reg = <0x0200a000 0x100>;
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clock-frequency = <19200000>,
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<32768>;
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cpu-offset = <0x40000>;
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};
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@ -16,19 +16,13 @@
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};
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timer@2000004 {
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compatible = "qcom,msm-gpt", "qcom,msm-timer";
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interrupts = <1 1 0x301>;
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reg = <0x02000004 0x10>;
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clock-frequency = <32768>;
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cpu-offset = <0x40000>;
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};
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timer@2000024 {
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compatible = "qcom,msm-dgt", "qcom,msm-timer";
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interrupts = <1 0 0x301>;
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reg = <0x02000024 0x10>,
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<0x02000034 0x4>;
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clock-frequency = <6750000>;
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compatible = "qcom,scss-timer", "qcom,msm-timer";
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interrupts = <1 0 0x301>,
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<1 1 0x301>,
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<1 2 0x301>;
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reg = <0x02000000 0x100>;
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clock-frequency = <27000000>,
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<32768>;
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cpu-offset = <0x40000>;
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};
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@ -15,20 +15,14 @@
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< 0x02002000 0x1000 >;
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};
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timer@200a004 {
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compatible = "qcom,msm-gpt", "qcom,msm-timer";
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interrupts = <1 2 0x301>;
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reg = <0x0200a004 0x10>;
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clock-frequency = <32768>;
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cpu-offset = <0x80000>;
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};
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timer@200a024 {
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compatible = "qcom,msm-dgt", "qcom,msm-timer";
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interrupts = <1 1 0x301>;
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reg = <0x0200a024 0x10>,
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<0x0200a034 0x4>;
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clock-frequency = <6750000>;
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timer@200a000 {
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compatible = "qcom,kpss-timer", "qcom,msm-timer";
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interrupts = <1 1 0x301>,
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<1 2 0x301>,
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<1 3 0x301>;
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reg = <0x0200a000 0x100>;
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clock-frequency = <27000000>,
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<32768>;
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cpu-offset = <0x80000>;
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};
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@ -36,6 +36,7 @@
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#define TIMER_ENABLE_CLR_ON_MATCH_EN BIT(1)
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#define TIMER_ENABLE_EN BIT(0)
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#define TIMER_CLEAR 0x000C
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#define DGT_CLK_CTL 0x10
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#define DGT_CLK_CTL_DIV_4 0x3
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#define GPT_HZ 32768
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@ -214,13 +215,9 @@ err:
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}
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#ifdef CONFIG_OF
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static const struct of_device_id msm_dgt_match[] __initconst = {
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{ .compatible = "qcom,msm-dgt" },
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{ },
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};
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static const struct of_device_id msm_gpt_match[] __initconst = {
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{ .compatible = "qcom,msm-gpt" },
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static const struct of_device_id msm_timer_match[] __initconst = {
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{ .compatible = "qcom,kpss-timer" },
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{ .compatible = "qcom,scss-timer" },
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{ },
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};
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@ -231,33 +228,29 @@ void __init msm_dt_timer_init(void)
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int irq;
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struct resource res;
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u32 percpu_offset;
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void __iomem *dgt_clk_ctl;
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void __iomem *base;
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void __iomem *cpu0_base;
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np = of_find_matching_node(NULL, msm_gpt_match);
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np = of_find_matching_node(NULL, msm_timer_match);
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if (!np) {
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pr_err("Can't find GPT DT node\n");
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pr_err("Can't find msm timer DT node\n");
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return;
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}
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event_base = of_iomap(np, 0);
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if (!event_base) {
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base = of_iomap(np, 0);
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if (!base) {
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pr_err("Failed to map event base\n");
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return;
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}
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irq = irq_of_parse_and_map(np, 0);
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/* We use GPT0 for the clockevent */
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irq = irq_of_parse_and_map(np, 1);
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if (irq <= 0) {
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pr_err("Can't get irq\n");
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return;
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}
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of_node_put(np);
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np = of_find_matching_node(NULL, msm_dgt_match);
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if (!np) {
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pr_err("Can't find DGT DT node\n");
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return;
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}
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/* We use CPU0's DGT for the clocksource */
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if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
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percpu_offset = 0;
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@ -266,45 +259,39 @@ void __init msm_dt_timer_init(void)
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return;
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}
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source_base = ioremap(res.start + percpu_offset, resource_size(&res));
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if (!source_base) {
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cpu0_base = ioremap(res.start + percpu_offset, resource_size(&res));
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if (!cpu0_base) {
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pr_err("Failed to map source base\n");
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return;
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}
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if (!of_address_to_resource(np, 1, &res)) {
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dgt_clk_ctl = ioremap(res.start + percpu_offset,
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resource_size(&res));
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if (!dgt_clk_ctl) {
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pr_err("Failed to map DGT control base\n");
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return;
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}
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writel_relaxed(DGT_CLK_CTL_DIV_4, dgt_clk_ctl);
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iounmap(dgt_clk_ctl);
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}
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if (of_property_read_u32(np, "clock-frequency", &freq)) {
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pr_err("Unknown frequency\n");
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return;
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}
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of_node_put(np);
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event_base = base + 0x4;
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source_base = cpu0_base + 0x24;
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freq /= 4;
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writel_relaxed(DGT_CLK_CTL_DIV_4, source_base + DGT_CLK_CTL);
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msm_timer_init(freq, 32, irq, !!percpu_offset);
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}
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#endif
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static int __init msm_timer_map(phys_addr_t event, phys_addr_t source)
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static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source)
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{
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event_base = ioremap(event, SZ_64);
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if (!event_base) {
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pr_err("Failed to map event base\n");
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return 1;
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}
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source_base = ioremap(source, SZ_64);
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if (!source_base) {
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pr_err("Failed to map source base\n");
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return 1;
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void __iomem *base;
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base = ioremap(addr, SZ_256);
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if (!base) {
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pr_err("Failed to map timer base\n");
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return -ENOMEM;
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}
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event_base = base + event;
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source_base = base + source;
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return 0;
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}
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@ -312,7 +299,7 @@ void __init msm7x01_timer_init(void)
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{
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struct clocksource *cs = &msm_clocksource;
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if (msm_timer_map(0xc0100000, 0xc0100010))
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if (msm_timer_map(0xc0100000, 0x0, 0x10))
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return;
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cs->read = msm_read_timer_count_shift;
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cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT));
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@ -323,14 +310,14 @@ void __init msm7x01_timer_init(void)
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void __init msm7x30_timer_init(void)
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{
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if (msm_timer_map(0xc0100004, 0xc0100024))
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if (msm_timer_map(0xc0100000, 0x4, 0x24))
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return;
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msm_timer_init(24576000 / 4, 32, 1, false);
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}
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void __init qsd8x50_timer_init(void)
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{
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if (msm_timer_map(0xAC100000, 0xAC100010))
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if (msm_timer_map(0xAC100000, 0x0, 0x10))
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return;
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msm_timer_init(19200000 / 4, 32, 7, false);
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}
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