include/asm-mips/: Spelling fixes
Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Adrian Bunk <bunk@kernel.org>
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@ -3,7 +3,7 @@
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/**
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* Adress alignment of the individual FPGA bytes.
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* Address alignment of the individual FPGA bytes.
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* The address arrangement of the individual bytes of the FPGA is two
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* byte aligned at the embedded MK2 platform.
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*/
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@ -45,7 +45,7 @@
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#define GT_PCI_IO_SIZE 0x02000000UL
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/*
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* PCI interrupts will come in on either the INTA or INTD interrups lines,
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* PCI interrupts will come in on either the INTA or INTD interrupt lines,
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* which are mapped to the #2 and #5 interrupt pins of the MIPS. On our
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* boards, they all either come in on IntD or they all come in on IntA, they
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* aren't mixed. There can be numerous PCI interrupts, so we keep a list of the
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@ -15,7 +15,7 @@
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/*
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* These are the virtual IRQ numbers, we divide all IRQ's into
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* 'spaces', the 'space' determines where and how to enable/disable
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* that particular IRQ on an SGI machine. HPC DMA and MC DMA interrups
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* that particular IRQ on an SGI machine. HPC DMA and MC DMA interrupts
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* are not supported this way. Driver is supposed to allocate HPC/MC
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* interrupt as shareable and then look to proper status bit (see
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* HAL2 driver). This will prevent many complications, trust me ;-)
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@ -338,7 +338,7 @@ typedef union io_perf_cnt {
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#define IIO_IFDR 0x400398 /* IOQ FIFO Depth */
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#define IIO_IIAP 0x4003a0 /* IIQ Arbitration Parameters */
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#define IIO_IMMR IIO_IIAP
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#define IIO_ICMR 0x4003a8 /* CRB Managment Register */
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#define IIO_ICMR 0x4003a8 /* CRB Management Register */
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#define IIO_ICCR 0x4003b0 /* CRB Control Register */
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#define IIO_ICTO 0x4003b8 /* CRB Time Out Register */
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#define IIO_ICTP 0x4003c0 /* CRB Time Out Prescalar */
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