ARC fixes for 4.10-rc6
- Fix for unaligned access emulation corner case - fix for udelay loop inline asm regression - Fix irq affinity finally for AXS103 board [Yuriy] - Final fixes for setting IO-coherency sanely in SMP -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJYi8faAAoJEGnX8d3iisJeU5wP/A1OM9S6TOCe4Ikguhp8UDgS UaGXboVpAAJNr6B+NfzvUbxi3VybgqooRM6tEU33A4eDzmfCTKBxMbvvE77rOuPC CC/8wxQ87wDqU+6GGL5DoTTc4rrxnNoEK6MOh2/Rv76idEi8Z2eo4INfm6FkBjGY +2WkuSpegBIxKrvFmBK9JC7cYaR3KBGSxW3rjLaK6xn0yt+LT1LQKJ/4OFLke7zy HWNVVnXnyJhn6z7v+Bum3hjnA8bhnDEVKAM0XgD/8TtjkhS6aod4HS2mjvcKnGc/ vyAk3B4fgq0EKFXX0IyHNnWI92gCnACWs8sHAQ/UBB4GHf0z1ScoihJeE4VAqRS4 kJ6SKAIHEtwY1nQV5GgVE2ddMgTDEXwAKCna99ejoUMMmQZFaRy80YuuSMLIjEuz H16oPkSzJDsR6Z9ocoC5mATWnHxsFZsCAX72u88X+ylaJmBziF2VmjaKRIXB8Psn YVz02U1YlONJTesEI7lnLD3fwx6pzu/XJjNTe4saiJFAoxaGuPbjRg6sJq3URDj6 3CJ89OFRbgx78jbk7QpYlc6m9SdTM2F5T7ICi6yxElok1dn+i+UQhnBXCinIvTcL 5w9IKA/9qeqjyT76vy1cPY2KlSDGj0kqjI+63IzpGtTScRuyflA5S1CvqyNeUbQq Vrtw/IRz5pvS7iaCDwuc =u+Jp -----END PGP SIGNATURE----- Merge tag 'arc-4.10-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc Pull ARC fixes from Vineet Gupta: "Hopefully last set of changes for ARC for 4.10: - fix for unaligned access emulation corner case - fix for udelay loop inline asm regression - fix irq affinity finally for AXS103 board [Yuriy] - final fixes for setting IO-coherency sanely in SMP" * tag 'arc-4.10-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: ARC: [arcompact] handle unaligned access delay slot corner case ARCv2: smp-boot: wake_flag polling by non-Masters needs to be uncached ARC: smp-boot: Decouple Non masters waiting API from jump to entry point ARCv2: MCIP: update the BCR per current changes ARC: udelay: fix inline assembler by adding LP_COUNT to clobber list ARCv2: MCIP: Deprecate setting of affinity in Device Tree
This commit is contained in:
Linus Torvalds
Коммит
ef1dce990b
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@ -15,6 +15,9 @@ Properties:
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Second cell specifies the irq distribution mode to cores
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0=Round Robin; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
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The second cell in interrupts property is deprecated and may be ignored by
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the kernel.
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intc accessed via the special ARC AUX register interface, hence "reg" property
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is not specified.
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@ -26,7 +26,9 @@ static inline void __delay(unsigned long loops)
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" lp 1f \n"
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" nop \n"
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"1: \n"
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: : "r"(loops));
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:
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: "r"(loops)
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: "lp_count");
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}
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extern void __bad_udelay(void);
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@ -71,14 +71,14 @@ ENTRY(stext)
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GET_CPU_ID r5
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cmp r5, 0
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mov.nz r0, r5
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#ifdef CONFIG_ARC_SMP_HALT_ON_RESET
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; Non-Master can proceed as system would be booted sufficiently
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jnz first_lines_of_secondary
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#else
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bz .Lmaster_proceed
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; Non-Masters wait for Master to boot enough and bring them up
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jnz arc_platform_smp_wait_to_boot
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#endif
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; Master falls thru
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; when they resume, tail-call to entry point
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mov blink, @first_lines_of_secondary
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j arc_platform_smp_wait_to_boot
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.Lmaster_proceed:
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#endif
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; Clear BSS before updating any globals
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@ -93,11 +93,10 @@ static void mcip_probe_n_setup(void)
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READ_BCR(ARC_REG_MCIP_BCR, mp);
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sprintf(smp_cpuinfo_buf,
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"Extn [SMP]\t: ARConnect (v%d): %d cores with %s%s%s%s%s\n",
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"Extn [SMP]\t: ARConnect (v%d): %d cores with %s%s%s%s\n",
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mp.ver, mp.num_cores,
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IS_AVAIL1(mp.ipi, "IPI "),
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IS_AVAIL1(mp.idu, "IDU "),
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IS_AVAIL1(mp.llm, "LLM "),
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IS_AVAIL1(mp.dbg, "DEBUG "),
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IS_AVAIL1(mp.gfrc, "GFRC"));
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@ -175,7 +174,6 @@ static void idu_irq_unmask(struct irq_data *data)
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raw_spin_unlock_irqrestore(&mcip_lock, flags);
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}
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#ifdef CONFIG_SMP
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static int
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idu_irq_set_affinity(struct irq_data *data, const struct cpumask *cpumask,
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bool force)
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@ -205,12 +203,27 @@ idu_irq_set_affinity(struct irq_data *data, const struct cpumask *cpumask,
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return IRQ_SET_MASK_OK;
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}
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#endif
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static void idu_irq_enable(struct irq_data *data)
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{
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/*
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* By default send all common interrupts to all available online CPUs.
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* The affinity of common interrupts in IDU must be set manually since
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* in some cases the kernel will not call irq_set_affinity() by itself:
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* 1. When the kernel is not configured with support of SMP.
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* 2. When the kernel is configured with support of SMP but upper
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* interrupt controllers does not support setting of the affinity
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* and cannot propagate it to IDU.
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*/
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idu_irq_set_affinity(data, cpu_online_mask, false);
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idu_irq_unmask(data);
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}
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static struct irq_chip idu_irq_chip = {
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.name = "MCIP IDU Intc",
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.irq_mask = idu_irq_mask,
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.irq_unmask = idu_irq_unmask,
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.irq_enable = idu_irq_enable,
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#ifdef CONFIG_SMP
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.irq_set_affinity = idu_irq_set_affinity,
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#endif
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@ -243,36 +256,14 @@ static int idu_irq_xlate(struct irq_domain *d, struct device_node *n,
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const u32 *intspec, unsigned int intsize,
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irq_hw_number_t *out_hwirq, unsigned int *out_type)
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{
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irq_hw_number_t hwirq = *out_hwirq = intspec[0];
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int distri = intspec[1];
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unsigned long flags;
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/*
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* Ignore value of interrupt distribution mode for common interrupts in
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* IDU which resides in intspec[1] since setting an affinity using value
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* from Device Tree is deprecated in ARC.
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*/
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*out_hwirq = intspec[0];
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*out_type = IRQ_TYPE_NONE;
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/* XXX: validate distribution scheme again online cpu mask */
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if (distri == 0) {
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/* 0 - Round Robin to all cpus, otherwise 1 bit per core */
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raw_spin_lock_irqsave(&mcip_lock, flags);
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idu_set_dest(hwirq, BIT(num_online_cpus()) - 1);
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idu_set_mode(hwirq, IDU_M_TRIG_LEVEL, IDU_M_DISTRI_RR);
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raw_spin_unlock_irqrestore(&mcip_lock, flags);
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} else {
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/*
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* DEST based distribution for Level Triggered intr can only
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* have 1 CPU, so generalize it to always contain 1 cpu
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*/
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int cpu = ffs(distri);
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if (cpu != fls(distri))
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pr_warn("IDU irq %lx distri mode set to cpu %x\n",
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hwirq, cpu);
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raw_spin_lock_irqsave(&mcip_lock, flags);
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idu_set_dest(hwirq, cpu);
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idu_set_mode(hwirq, IDU_M_TRIG_LEVEL, IDU_M_DISTRI_DEST);
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raw_spin_unlock_irqrestore(&mcip_lock, flags);
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}
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return 0;
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}
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@ -90,22 +90,37 @@ void __init smp_cpus_done(unsigned int max_cpus)
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*/
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static volatile int wake_flag;
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#ifdef CONFIG_ISA_ARCOMPACT
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#define __boot_read(f) f
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#define __boot_write(f, v) f = v
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#else
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#define __boot_read(f) arc_read_uncached_32(&f)
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#define __boot_write(f, v) arc_write_uncached_32(&f, v)
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#endif
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static void arc_default_smp_cpu_kick(int cpu, unsigned long pc)
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{
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BUG_ON(cpu == 0);
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wake_flag = cpu;
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__boot_write(wake_flag, cpu);
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}
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void arc_platform_smp_wait_to_boot(int cpu)
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{
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while (wake_flag != cpu)
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/* for halt-on-reset, we've waited already */
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if (IS_ENABLED(CONFIG_ARC_SMP_HALT_ON_RESET))
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return;
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while (__boot_read(wake_flag) != cpu)
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;
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wake_flag = 0;
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__asm__ __volatile__("j @first_lines_of_secondary \n");
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__boot_write(wake_flag, 0);
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}
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const char *arc_platform_smp_cpuinfo(void)
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{
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return plat_smp_ops.info ? : "";
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@ -241,8 +241,9 @@ int misaligned_fixup(unsigned long address, struct pt_regs *regs,
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if (state.fault)
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goto fault;
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/* clear any remanants of delay slot */
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if (delay_mode(regs)) {
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regs->ret = regs->bta;
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regs->ret = regs->bta ~1U;
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regs->status32 &= ~STATUS_DE_MASK;
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} else {
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regs->ret += state.instr_len;
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@ -55,17 +55,17 @@ struct mcip_cmd {
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struct mcip_bcr {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad3:8,
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idu:1, llm:1, num_cores:6,
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iocoh:1, gfrc:1, dbg:1, pad2:1,
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msg:1, sem:1, ipi:1, pad:1,
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unsigned int pad4:6, pw_dom:1, pad3:1,
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idu:1, pad2:1, num_cores:6,
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pad:1, gfrc:1, dbg:1, pw:1,
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msg:1, sem:1, ipi:1, slv:1,
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ver:8;
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#else
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unsigned int ver:8,
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pad:1, ipi:1, sem:1, msg:1,
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pad2:1, dbg:1, gfrc:1, iocoh:1,
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num_cores:6, llm:1, idu:1,
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pad3:8;
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slv:1, ipi:1, sem:1, msg:1,
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pw:1, dbg:1, gfrc:1, pad:1,
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num_cores:6, pad2:1, idu:1,
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pad3:1, pw_dom:1, pad4:6;
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#endif
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};
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