spi: cs42l43: Add SPI controller support
The CS42L43 is an audio CODEC with integrated MIPI SoundWire interface (Version 1.2.1 compliant), I2C, SPI, and I2S/TDM interfaces designed for portable applications. It provides a high dynamic range, stereo DAC for headphone output, two integrated Class D amplifiers for loudspeakers, and two ADCs for wired headset microphone input or stereo line input. PDM inputs are provided for digital microphones. The SPI component incorporates a SPI controller interface for communication with other peripheral components. Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com> Signed-off-by: Maciej Strozek <mstrozek@opensource.cirrus.com> Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20230804104602.395892-6-ckeepax@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -4888,6 +4888,7 @@ S: Maintained
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F: Documentation/devicetree/bindings/sound/cirrus,cs*
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F: drivers/mfd/cs42l43*
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F: drivers/pinctrl/cirrus/pinctrl-cs42l43*
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F: drivers/spi/spi-cs42l43*
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F: include/dt-bindings/sound/cs*
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F: include/linux/mfd/cs42l43*
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F: include/sound/cs*
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@ -281,6 +281,13 @@ config SPI_COLDFIRE_QSPI
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This enables support for the Coldfire QSPI controller in master
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mode.
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config SPI_CS42L43
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tristate "Cirrus Logic CS42L43 SPI controller"
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depends on MFD_CS42L43 && PINCTRL_CS42L43
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help
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This enables support for the SPI controller inside the Cirrus Logic
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CS42L43 audio codec.
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config SPI_DAVINCI
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tristate "Texas Instruments DaVinci/DA8x/OMAP-L/AM1x SoC SPI controller"
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depends on ARCH_DAVINCI || ARCH_KEYSTONE || COMPILE_TEST
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@ -40,6 +40,7 @@ obj-$(CONFIG_SPI_CADENCE_QUADSPI) += spi-cadence-quadspi.o
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obj-$(CONFIG_SPI_CADENCE_XSPI) += spi-cadence-xspi.o
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obj-$(CONFIG_SPI_CLPS711X) += spi-clps711x.o
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obj-$(CONFIG_SPI_COLDFIRE_QSPI) += spi-coldfire-qspi.o
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obj-$(CONFIG_SPI_CS42L43) += spi-cs42l43.o
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obj-$(CONFIG_SPI_DAVINCI) += spi-davinci.o
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obj-$(CONFIG_SPI_DLN2) += spi-dln2.o
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obj-$(CONFIG_SPI_DESIGNWARE) += spi-dw.o
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@ -0,0 +1,284 @@
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// SPDX-License-Identifier: GPL-2.0
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//
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// CS42L43 SPI Controller Driver
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//
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// Copyright (C) 2022-2023 Cirrus Logic, Inc. and
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// Cirrus Logic International Semiconductor Ltd.
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#include <linux/bits.h>
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#include <linux/bitfield.h>
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#include <linux/device.h>
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#include <linux/errno.h>
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#include <linux/mfd/cs42l43.h>
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#include <linux/mfd/cs42l43-regs.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <linux/spi/spi.h>
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#include <linux/units.h>
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#define CS42L43_FIFO_SIZE 16
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#define CS42L43_SPI_ROOT_HZ (40 * HZ_PER_MHZ)
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#define CS42L43_SPI_MAX_LENGTH 65532
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enum cs42l43_spi_cmd {
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CS42L43_WRITE,
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CS42L43_READ
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};
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struct cs42l43_spi {
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struct device *dev;
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struct regmap *regmap;
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struct spi_controller *ctlr;
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};
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static const unsigned int cs42l43_clock_divs[] = {
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2, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
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};
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static int cs42l43_spi_tx(struct regmap *regmap, const u8 *buf, unsigned int len)
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{
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const u8 *end = buf + len;
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u32 val = 0;
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int ret;
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while (buf < end) {
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const u8 *block = min(buf + CS42L43_FIFO_SIZE, end);
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while (buf < block) {
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const u8 *word = min(buf + sizeof(u32), block);
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int pad = (buf + sizeof(u32)) - word;
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while (buf < word) {
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val >>= BITS_PER_BYTE;
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val |= FIELD_PREP(GENMASK(31, 24), *buf);
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buf++;
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}
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val >>= pad * BITS_PER_BYTE;
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regmap_write(regmap, CS42L43_TX_DATA, val);
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}
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regmap_write(regmap, CS42L43_TRAN_CONFIG8, CS42L43_SPI_TX_DONE_MASK);
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ret = regmap_read_poll_timeout(regmap, CS42L43_TRAN_STATUS1,
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val, (val & CS42L43_SPI_TX_REQUEST_MASK),
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1000, 5000);
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if (ret)
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return ret;
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}
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return 0;
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}
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static int cs42l43_spi_rx(struct regmap *regmap, u8 *buf, unsigned int len)
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{
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u8 *end = buf + len;
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u32 val;
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int ret;
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while (buf < end) {
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u8 *block = min(buf + CS42L43_FIFO_SIZE, end);
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ret = regmap_read_poll_timeout(regmap, CS42L43_TRAN_STATUS1,
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val, (val & CS42L43_SPI_RX_REQUEST_MASK),
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1000, 5000);
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if (ret)
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return ret;
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while (buf < block) {
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u8 *word = min(buf + sizeof(u32), block);
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ret = regmap_read(regmap, CS42L43_RX_DATA, &val);
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if (ret)
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return ret;
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while (buf < word) {
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*buf = FIELD_GET(GENMASK(7, 0), val);
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val >>= BITS_PER_BYTE;
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buf++;
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}
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}
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regmap_write(regmap, CS42L43_TRAN_CONFIG8, CS42L43_SPI_RX_DONE_MASK);
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}
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return 0;
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}
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static int cs42l43_transfer_one(struct spi_controller *ctlr, struct spi_device *spi,
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struct spi_transfer *tfr)
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{
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struct cs42l43_spi *priv = spi_controller_get_devdata(spi->controller);
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int i, ret = -EINVAL;
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for (i = 0; i < ARRAY_SIZE(cs42l43_clock_divs); i++) {
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if (CS42L43_SPI_ROOT_HZ / cs42l43_clock_divs[i] <= tfr->speed_hz)
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break;
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}
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if (i == ARRAY_SIZE(cs42l43_clock_divs))
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return -EINVAL;
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regmap_write(priv->regmap, CS42L43_SPI_CLK_CONFIG1, i);
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if (tfr->tx_buf) {
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regmap_write(priv->regmap, CS42L43_TRAN_CONFIG3, CS42L43_WRITE);
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regmap_write(priv->regmap, CS42L43_TRAN_CONFIG4, tfr->len - 1);
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} else if (tfr->rx_buf) {
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regmap_write(priv->regmap, CS42L43_TRAN_CONFIG3, CS42L43_READ);
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regmap_write(priv->regmap, CS42L43_TRAN_CONFIG5, tfr->len - 1);
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}
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regmap_write(priv->regmap, CS42L43_TRAN_CONFIG1, CS42L43_SPI_START_MASK);
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if (tfr->tx_buf)
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ret = cs42l43_spi_tx(priv->regmap, (const u8 *)tfr->tx_buf, tfr->len);
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else if (tfr->rx_buf)
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ret = cs42l43_spi_rx(priv->regmap, (u8 *)tfr->rx_buf, tfr->len);
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return ret;
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}
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static void cs42l43_set_cs(struct spi_device *spi, bool is_high)
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{
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struct cs42l43_spi *priv = spi_controller_get_devdata(spi->controller);
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if (spi_get_chipselect(spi, 0) == 0)
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regmap_write(priv->regmap, CS42L43_SPI_CONFIG2, !is_high);
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}
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static int cs42l43_prepare_message(struct spi_controller *ctlr, struct spi_message *msg)
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{
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struct cs42l43_spi *priv = spi_controller_get_devdata(ctlr);
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struct spi_device *spi = msg->spi;
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unsigned int spi_config1 = 0;
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/* select another internal CS, which doesn't exist, so CS 0 is not used */
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if (spi_get_csgpiod(spi, 0))
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spi_config1 |= 1 << CS42L43_SPI_SS_SEL_SHIFT;
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if (spi->mode & SPI_CPOL)
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spi_config1 |= CS42L43_SPI_CPOL_MASK;
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if (spi->mode & SPI_CPHA)
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spi_config1 |= CS42L43_SPI_CPHA_MASK;
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if (spi->mode & SPI_3WIRE)
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spi_config1 |= CS42L43_SPI_THREE_WIRE_MASK;
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regmap_write(priv->regmap, CS42L43_SPI_CONFIG1, spi_config1);
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return 0;
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}
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static int cs42l43_prepare_transfer_hardware(struct spi_controller *ctlr)
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{
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struct cs42l43_spi *priv = spi_controller_get_devdata(ctlr);
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int ret;
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ret = regmap_write(priv->regmap, CS42L43_BLOCK_EN2, CS42L43_SPI_MSTR_EN_MASK);
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if (ret)
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dev_err(priv->dev, "Failed to enable SPI controller: %d\n", ret);
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return ret;
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}
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static int cs42l43_unprepare_transfer_hardware(struct spi_controller *ctlr)
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{
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struct cs42l43_spi *priv = spi_controller_get_devdata(ctlr);
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int ret;
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ret = regmap_write(priv->regmap, CS42L43_BLOCK_EN2, 0);
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if (ret)
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dev_err(priv->dev, "Failed to disable SPI controller: %d\n", ret);
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return ret;
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}
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static size_t cs42l43_spi_max_length(struct spi_device *spi)
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{
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return CS42L43_SPI_MAX_LENGTH;
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}
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static int cs42l43_spi_probe(struct platform_device *pdev)
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{
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struct cs42l43 *cs42l43 = dev_get_drvdata(pdev->dev.parent);
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struct cs42l43_spi *priv;
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struct fwnode_handle *fwnode = dev_fwnode(cs42l43->dev);
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int ret;
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priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->ctlr = devm_spi_alloc_master(&pdev->dev, sizeof(*priv->ctlr));
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if (!priv->ctlr)
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return -ENOMEM;
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spi_controller_set_devdata(priv->ctlr, priv);
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priv->dev = &pdev->dev;
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priv->regmap = cs42l43->regmap;
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priv->ctlr->prepare_message = cs42l43_prepare_message;
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priv->ctlr->prepare_transfer_hardware = cs42l43_prepare_transfer_hardware;
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priv->ctlr->unprepare_transfer_hardware = cs42l43_unprepare_transfer_hardware;
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priv->ctlr->transfer_one = cs42l43_transfer_one;
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priv->ctlr->set_cs = cs42l43_set_cs;
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priv->ctlr->max_transfer_size = cs42l43_spi_max_length;
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if (is_of_node(fwnode))
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fwnode = fwnode_get_named_child_node(fwnode, "spi");
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device_set_node(&priv->ctlr->dev, fwnode);
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priv->ctlr->mode_bits = SPI_3WIRE | SPI_MODE_X_MASK;
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priv->ctlr->flags = SPI_CONTROLLER_HALF_DUPLEX;
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priv->ctlr->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) |
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SPI_BPW_MASK(32);
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priv->ctlr->min_speed_hz = CS42L43_SPI_ROOT_HZ /
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cs42l43_clock_divs[ARRAY_SIZE(cs42l43_clock_divs) - 1];
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priv->ctlr->max_speed_hz = CS42L43_SPI_ROOT_HZ / cs42l43_clock_divs[0];
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priv->ctlr->use_gpio_descriptors = true;
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priv->ctlr->auto_runtime_pm = true;
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devm_pm_runtime_enable(priv->dev);
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pm_runtime_idle(priv->dev);
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regmap_write(priv->regmap, CS42L43_TRAN_CONFIG6, CS42L43_FIFO_SIZE - 1);
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regmap_write(priv->regmap, CS42L43_TRAN_CONFIG7, CS42L43_FIFO_SIZE - 1);
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// Disable Watchdog timer and enable stall
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regmap_write(priv->regmap, CS42L43_SPI_CONFIG3, 0);
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regmap_write(priv->regmap, CS42L43_SPI_CONFIG4, CS42L43_SPI_STALL_ENA_MASK);
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ret = devm_spi_register_controller(priv->dev, priv->ctlr);
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if (ret) {
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pm_runtime_disable(priv->dev);
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dev_err(priv->dev, "Failed to register SPI controller: %d\n", ret);
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}
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return ret;
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}
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static const struct platform_device_id cs42l43_spi_id_table[] = {
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{ "cs42l43-spi", },
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{}
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};
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MODULE_DEVICE_TABLE(platform, cs42l43_spi_id_table);
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static struct platform_driver cs42l43_spi_driver = {
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.driver = {
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.name = "cs42l43-spi",
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},
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.probe = cs42l43_spi_probe,
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.id_table = cs42l43_spi_id_table,
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};
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module_platform_driver(cs42l43_spi_driver);
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MODULE_DESCRIPTION("CS42L43 SPI Driver");
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MODULE_AUTHOR("Lucas Tanure <tanureal@opensource.cirrus.com>");
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MODULE_AUTHOR("Maciej Strozek <mstrozek@opensource.cirrus.com>");
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MODULE_LICENSE("GPL");
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