ARM: OMAP4+: control: remove support for legacy pad read/write
omap4_ctrl_pad_readl/writel are no longer used by anybody, so remove these. Syscon / pinctrl should be used to access the padconf area instead. Signed-off-by: Tero Kristo <t-kristo@ti.com>
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@ -36,7 +36,6 @@
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static void __iomem *omap2_ctrl_base;
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static s16 omap2_ctrl_offset;
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static void __iomem *omap4_ctrl_pad_base;
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static struct regmap *omap2_ctrl_syscon;
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#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
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@ -139,13 +138,9 @@ struct omap3_control_regs {
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static struct omap3_control_regs control_context;
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#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
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#define OMAP4_CTRL_PAD_REGADDR(reg) (omap4_ctrl_pad_base + (reg))
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void __init omap2_set_globals_control(void __iomem *ctrl,
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void __iomem *ctrl_pad)
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void __init omap2_set_globals_control(void __iomem *ctrl)
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{
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omap2_ctrl_base = ctrl;
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omap4_ctrl_pad_base = ctrl_pad;
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}
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u8 omap_ctrl_readb(u16 offset)
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@ -218,23 +213,6 @@ void omap_ctrl_writel(u32 val, u16 offset)
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val);
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}
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/*
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* On OMAP4 control pad are not addressable from control
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* core base. So the common omap_ctrl_read/write APIs breaks
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* Hence export separate APIs to manage the omap4 pad control
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* registers. This APIs will work only for OMAP4
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*/
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u32 omap4_ctrl_pad_readl(u16 offset)
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{
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return readl_relaxed(OMAP4_CTRL_PAD_REGADDR(offset));
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}
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void omap4_ctrl_pad_writel(u32 val, u16 offset)
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{
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writel_relaxed(val, OMAP4_CTRL_PAD_REGADDR(offset));
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}
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#ifdef CONFIG_ARCH_OMAP3
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/**
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@ -443,11 +443,9 @@
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extern u8 omap_ctrl_readb(u16 offset);
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extern u16 omap_ctrl_readw(u16 offset);
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extern u32 omap_ctrl_readl(u16 offset);
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extern u32 omap4_ctrl_pad_readl(u16 offset);
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extern void omap_ctrl_writeb(u8 val, u16 offset);
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extern void omap_ctrl_writew(u16 val, u16 offset);
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extern void omap_ctrl_writel(u32 val, u16 offset);
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extern void omap4_ctrl_pad_writel(u32 val, u16 offset);
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extern void omap3_save_scratchpad_contents(void);
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extern void omap3_clear_scratchpad_contents(void);
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@ -465,8 +463,7 @@ extern int omap3_ctrl_save_padconf(void);
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void omap3_ctrl_init(void);
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int omap2_control_base_init(void);
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int omap_control_init(void);
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extern void omap2_set_globals_control(void __iomem *ctrl,
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void __iomem *ctrl_pad);
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void omap2_set_globals_control(void __iomem *ctrl);
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void __init omap3_control_legacy_iomap_init(void);
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#else
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#define omap_ctrl_readb(x) 0
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@ -443,7 +443,7 @@ void __init omap3_init_early(void)
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/* XXX: remove these once OMAP3 is DT only */
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if (!of_have_populated_dt()) {
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omap2_set_globals_control(
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OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE), NULL);
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OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE));
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omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE));
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omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE),
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NULL);
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@ -631,8 +631,7 @@ void __init omap4430_init_early(void)
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{
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omap2_set_globals_tap(OMAP443X_CLASS,
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OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
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omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
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OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE));
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omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
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omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
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omap4xxx_check_revision();
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omap4xxx_check_features();
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@ -660,8 +659,7 @@ void __init omap5_init_early(void)
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{
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omap2_set_globals_tap(OMAP54XX_CLASS,
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OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
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omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
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OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE));
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omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
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omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
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omap4_pm_init_early();
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omap2_prcm_base_init();
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@ -686,8 +684,7 @@ void __init omap5_init_late(void)
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void __init dra7xx_init_early(void)
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{
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omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
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omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
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OMAP2_L4_IO_ADDRESS(DRA7XX_CTRL_BASE));
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omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
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omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
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omap4_pm_init_early();
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omap2_prcm_base_init();
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