arm/imx/iomux-v1: make base address a runtime choice
While at it move register modification to static inlines and so make the relevant code more readable. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
This commit is contained in:
Uwe Kleine-König
Родитель
5e2e95f520
Коммит
f021b5a1ef
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@ -24,7 +24,6 @@
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* GPIO Module and I/O Multiplexer
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* x = 0..3 for reg_A, reg_B, reg_C, reg_D
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*/
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#define VA_GPIO_BASE IO_ADDRESS(GPIO_BASE_ADDR)
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#define MXC_DDIR(x) (0x00 + ((x) << 8))
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#define MXC_OCR1(x) (0x04 + ((x) << 8))
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#define MXC_OCR2(x) (0x08 + ((x) << 8))
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@ -1,9 +1,8 @@
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/*
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* arch/arm/plat-mxc/iomux-v1.c
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*
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* author: Sascha Hauer
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* Created: april 20th, 2004
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* Copyright: Synertronixx GmbH
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* Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH
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* Copyright (C) 2009 Uwe Kleine-Koenig, Pengutronix
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*
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* Common code for i.MX1, i.MX21 and i.MX27
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*
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@ -18,9 +17,8 @@
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* along with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#include <linux/errno.h>
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@ -34,78 +32,119 @@
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#include <asm/mach/map.h>
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#include <mach/iomux.h>
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static void __iomem *imx_iomuxv1_baseaddr;
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static inline unsigned long imx_iomuxv1_readl(unsigned offset)
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{
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return __raw_readl(imx_iomuxv1_baseaddr + offset);
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}
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static inline void imx_iomuxv1_writel(unsigned long val, unsigned offset)
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{
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__raw_writel(val, imx_iomuxv1_baseaddr + offset);
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}
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static inline void imx_iomuxv1_rmwl(unsigned offset,
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unsigned long mask, unsigned long value)
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{
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unsigned long reg = imx_iomuxv1_readl(offset);
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reg &= ~mask;
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reg |= value;
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imx_iomuxv1_writel(reg, offset);
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}
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static inline void imx_iomuxv1_set_puen(
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unsigned int port, unsigned int pin, int on)
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{
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unsigned long mask = 1 << pin;
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imx_iomuxv1_rmwl(MXC_PUEN(port), mask, on ? mask : 0);
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}
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static inline void imx_iomuxv1_set_ddir(
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unsigned int port, unsigned int pin, int out)
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{
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unsigned long mask = 1 << pin;
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imx_iomuxv1_rmwl(MXC_DDIR(port), mask, out ? mask : 0);
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}
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static inline void imx_iomuxv1_set_gpr(
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unsigned int port, unsigned int pin, int af)
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{
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unsigned long mask = 1 << pin;
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imx_iomuxv1_rmwl(MXC_GPR(port), mask, af ? mask : 0);
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}
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static inline void imx_iomuxv1_set_gius(
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unsigned int port, unsigned int pin, int inuse)
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{
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unsigned long mask = 1 << pin;
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imx_iomuxv1_rmwl(MXC_GIUS(port), mask, inuse ? mask : 0);
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}
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static inline void imx_iomuxv1_set_ocr(
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unsigned int port, unsigned int pin, unsigned int ocr)
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{
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unsigned long shift = (pin & 0xf) << 1;
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unsigned long mask = 3 << shift;
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unsigned long value = ocr << shift;
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unsigned long offset = pin < 16 ? MXC_OCR1(port) : MXC_OCR2(port);
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imx_iomuxv1_rmwl(offset, mask, value);
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}
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static inline void imx_iomuxv1_set_iconfa(
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unsigned int port, unsigned int pin, unsigned int aout)
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{
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unsigned long shift = (pin & 0xf) << 1;
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unsigned long mask = 3 << shift;
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unsigned long value = aout << shift;
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unsigned long offset = pin < 16 ? MXC_ICONFA1(port) : MXC_ICONFA2(port);
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imx_iomuxv1_rmwl(offset, mask, value);
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}
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static inline void imx_iomuxv1_set_iconfb(
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unsigned int port, unsigned int pin, unsigned int bout)
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{
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unsigned long shift = (pin & 0xf) << 1;
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unsigned long mask = 3 << shift;
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unsigned long value = bout << shift;
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unsigned long offset = pin < 16 ? MXC_ICONFB1(port) : MXC_ICONFB2(port);
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imx_iomuxv1_rmwl(offset, mask, value);
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}
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void mxc_gpio_mode(int gpio_mode)
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{
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unsigned int pin = gpio_mode & GPIO_PIN_MASK;
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unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
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unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT;
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unsigned int tmp;
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unsigned int aout = (gpio_mode >> GPIO_AOUT_SHIFT) & 3;
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unsigned int bout = (gpio_mode >> GPIO_BOUT_SHIFT) & 3;
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/* Pullup enable */
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tmp = __raw_readl(VA_GPIO_BASE + MXC_PUEN(port));
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if (gpio_mode & GPIO_PUEN)
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tmp |= (1 << pin);
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else
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tmp &= ~(1 << pin);
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__raw_writel(tmp, VA_GPIO_BASE + MXC_PUEN(port));
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imx_iomuxv1_set_puen(port, pin, gpio_mode & GPIO_PUEN);
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/* Data direction */
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tmp = __raw_readl(VA_GPIO_BASE + MXC_DDIR(port));
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if (gpio_mode & GPIO_OUT)
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tmp |= 1 << pin;
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else
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tmp &= ~(1 << pin);
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__raw_writel(tmp, VA_GPIO_BASE + MXC_DDIR(port));
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imx_iomuxv1_set_ddir(port, pin, gpio_mode & GPIO_OUT);
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/* Primary / alternate function */
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tmp = __raw_readl(VA_GPIO_BASE + MXC_GPR(port));
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if (gpio_mode & GPIO_AF)
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tmp |= (1 << pin);
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else
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tmp &= ~(1 << pin);
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__raw_writel(tmp, VA_GPIO_BASE + MXC_GPR(port));
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imx_iomuxv1_set_gpr(port, pin, gpio_mode & GPIO_AF);
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/* use as gpio? */
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tmp = __raw_readl(VA_GPIO_BASE + MXC_GIUS(port));
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if (gpio_mode & (GPIO_PF | GPIO_AF))
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tmp &= ~(1 << pin);
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else
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tmp |= (1 << pin);
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__raw_writel(tmp, VA_GPIO_BASE + MXC_GIUS(port));
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imx_iomuxv1_set_gius(port, pin, !(gpio_mode & (GPIO_PF | GPIO_AF)));
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if (pin < 16) {
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tmp = __raw_readl(VA_GPIO_BASE + MXC_OCR1(port));
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tmp &= ~(3 << (pin * 2));
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tmp |= (ocr << (pin * 2));
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__raw_writel(tmp, VA_GPIO_BASE + MXC_OCR1(port));
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imx_iomuxv1_set_ocr(port, pin, ocr);
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tmp = __raw_readl(VA_GPIO_BASE + MXC_ICONFA1(port));
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tmp &= ~(3 << (pin * 2));
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tmp |= ((gpio_mode >> GPIO_AOUT_SHIFT) & 3) << (pin * 2);
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__raw_writel(tmp, VA_GPIO_BASE + MXC_ICONFA1(port));
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imx_iomuxv1_set_iconfa(port, pin, aout);
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tmp = __raw_readl(VA_GPIO_BASE + MXC_ICONFB1(port));
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tmp &= ~(3 << (pin * 2));
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tmp |= ((gpio_mode >> GPIO_BOUT_SHIFT) & 3) << (pin * 2);
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__raw_writel(tmp, VA_GPIO_BASE + MXC_ICONFB1(port));
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} else {
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pin -= 16;
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tmp = __raw_readl(VA_GPIO_BASE + MXC_OCR2(port));
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tmp &= ~(3 << (pin * 2));
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tmp |= (ocr << (pin * 2));
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__raw_writel(tmp, VA_GPIO_BASE + MXC_OCR2(port));
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tmp = __raw_readl(VA_GPIO_BASE + MXC_ICONFA2(port));
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tmp &= ~(3 << (pin * 2));
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tmp |= ((gpio_mode >> GPIO_AOUT_SHIFT) & 3) << (pin * 2);
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__raw_writel(tmp, VA_GPIO_BASE + MXC_ICONFA2(port));
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tmp = __raw_readl(VA_GPIO_BASE + MXC_ICONFB2(port));
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tmp &= ~(3 << (pin * 2));
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tmp |= ((gpio_mode >> GPIO_BOUT_SHIFT) & 3) << (pin * 2);
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__raw_writel(tmp, VA_GPIO_BASE + MXC_ICONFB2(port));
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}
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imx_iomuxv1_set_iconfb(port, pin, bout);
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}
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EXPORT_SYMBOL(mxc_gpio_mode);
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@ -151,6 +190,28 @@ void mxc_gpio_release_multiple_pins(const int *pin_list, int count)
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gpio_free(gpio);
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p++;
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}
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}
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EXPORT_SYMBOL(mxc_gpio_release_multiple_pins);
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static int imx_iomuxv1_init(void)
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{
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#ifdef CONFIG_ARCH_MX1
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if (cpu_is_mx1())
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imx_iomuxv1_baseaddr = MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR);
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else
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#endif
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#ifdef CONFIG_MACH_MX21
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if (cpu_is_mx21())
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imx_iomuxv1_baseaddr = MX21_IO_ADDRESS(MX21_GPIO_BASE_ADDR);
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else
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#endif
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#ifdef CONFIG_MACH_MX27
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if (cpu_is_mx27())
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imx_iomuxv1_baseaddr = MX27_IO_ADDRESS(MX27_GPIO_BASE_ADDR);
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else
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#endif
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return -ENODEV;
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return 0;
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}
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pure_initcall(imx_iomuxv1_init);
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