ARM: at91: pm: add self-refresh support for sama7g5
Add self-refresh support for SAMA7G5. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210415105010.569620-13-claudiu.beznea@microchip.com
This commit is contained in:
Claudiu Beznea
Nicolas Ferre
Родитель
d8c7983f31
Коммит
f0bbf17958
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@ -12,6 +12,7 @@
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#include <linux/mfd/syscon/atmel-mc.h>
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#include <soc/at91/at91sam9_ddrsdr.h>
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#include <soc/at91/at91sam9_sdramc.h>
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#include <soc/at91/sama7-ddr.h>
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#define AT91_MEMCTRL_MC 0
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#define AT91_MEMCTRL_SDRAMC 1
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@ -27,6 +28,7 @@
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struct at91_pm_data {
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void __iomem *pmc;
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void __iomem *ramc[2];
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void __iomem *ramc_phy;
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unsigned long uhp_udp_mask;
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unsigned int memctrl;
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unsigned int mode;
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@ -8,6 +8,8 @@ int main(void)
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DEFINE(PM_DATA_PMC, offsetof(struct at91_pm_data, pmc));
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DEFINE(PM_DATA_RAMC0, offsetof(struct at91_pm_data, ramc[0]));
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DEFINE(PM_DATA_RAMC1, offsetof(struct at91_pm_data, ramc[1]));
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DEFINE(PM_DATA_RAMC_PHY, offsetof(struct at91_pm_data,
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ramc_phy));
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DEFINE(PM_DATA_MEMCTRL, offsetof(struct at91_pm_data, memctrl));
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DEFINE(PM_DATA_MODE, offsetof(struct at91_pm_data, mode));
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DEFINE(PM_DATA_SHDWC, offsetof(struct at91_pm_data, shdwc));
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@ -87,6 +87,200 @@ tmp3 .req r6
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.arm
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#ifdef CONFIG_SOC_SAMA7
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/**
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* Enable self-refresh
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*
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* Side effects: overwrites r2, r3, tmp1, tmp2, tmp3, r7
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*/
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.macro at91_sramc_self_refresh_ena
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ldr r2, .sramc_base
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ldr r3, .sramc_phy_base
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ldr r7, .pm_mode
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dsb
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/* Disable all AXI ports. */
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ldr tmp1, [r2, #UDDRC_PCTRL_0]
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bic tmp1, tmp1, #0x1
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str tmp1, [r2, #UDDRC_PCTRL_0]
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ldr tmp1, [r2, #UDDRC_PCTRL_1]
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bic tmp1, tmp1, #0x1
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str tmp1, [r2, #UDDRC_PCTRL_1]
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ldr tmp1, [r2, #UDDRC_PCTRL_2]
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bic tmp1, tmp1, #0x1
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str tmp1, [r2, #UDDRC_PCTRL_2]
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ldr tmp1, [r2, #UDDRC_PCTRL_3]
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bic tmp1, tmp1, #0x1
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str tmp1, [r2, #UDDRC_PCTRL_3]
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ldr tmp1, [r2, #UDDRC_PCTRL_4]
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bic tmp1, tmp1, #0x1
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str tmp1, [r2, #UDDRC_PCTRL_4]
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sr_ena_1:
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/* Wait for all ports to disable. */
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ldr tmp1, [r2, #UDDRC_PSTAT]
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ldr tmp2, =UDDRC_PSTAT_ALL_PORTS
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tst tmp1, tmp2
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bne sr_ena_1
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/* Switch to self-refresh. */
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ldr tmp1, [r2, #UDDRC_PWRCTL]
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orr tmp1, tmp1, #UDDRC_PWRCTRL_SELFREF_SW
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str tmp1, [r2, #UDDRC_PWRCTL]
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sr_ena_2:
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/* Wait for self-refresh enter. */
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ldr tmp1, [r2, #UDDRC_STAT]
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bic tmp1, tmp1, #~UDDRC_STAT_SELFREF_TYPE_MSK
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cmp tmp1, #UDDRC_STAT_SELFREF_TYPE_SW
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bne sr_ena_2
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/* Put DDR PHY's DLL in bypass mode for non-backup modes. */
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cmp r7, #AT91_PM_BACKUP
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beq sr_ena_3
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ldr tmp1, [r3, #DDR3PHY_PIR]
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orr tmp1, tmp1, #DDR3PHY_PIR_DLLBYP
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str tmp1, [r3, #DDR3PHY_PIR]
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sr_ena_3:
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/* Power down DDR PHY data receivers. */
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ldr tmp1, [r3, #DDR3PHY_DXCCR]
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orr tmp1, tmp1, #DDR3PHY_DXCCR_DXPDR
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str tmp1, [r3, #DDR3PHY_DXCCR]
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/* Power down ADDR/CMD IO. */
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ldr tmp1, [r3, #DDR3PHY_ACIOCR]
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orr tmp1, tmp1, #DDR3PHY_ACIORC_ACPDD
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orr tmp1, tmp1, #DDR3PHY_ACIOCR_CKPDD_CK0
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orr tmp1, tmp1, #DDR3PHY_ACIOCR_CSPDD_CS0
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str tmp1, [r3, #DDR3PHY_ACIOCR]
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/* Power down ODT. */
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ldr tmp1, [r3, #DDR3PHY_DSGCR]
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orr tmp1, tmp1, #DDR3PHY_DSGCR_ODTPDD_ODT0
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str tmp1, [r3, #DDR3PHY_DSGCR]
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.endm
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/**
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* Disable self-refresh
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*
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* Side effects: overwrites r2, r3, tmp1, tmp2, tmp3
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*/
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.macro at91_sramc_self_refresh_dis
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ldr r2, .sramc_base
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ldr r3, .sramc_phy_base
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/* Power up DDR PHY data receivers. */
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ldr tmp1, [r3, #DDR3PHY_DXCCR]
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bic tmp1, tmp1, #DDR3PHY_DXCCR_DXPDR
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str tmp1, [r3, #DDR3PHY_DXCCR]
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/* Power up the output of CK and CS pins. */
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ldr tmp1, [r3, #DDR3PHY_ACIOCR]
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bic tmp1, tmp1, #DDR3PHY_ACIORC_ACPDD
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bic tmp1, tmp1, #DDR3PHY_ACIOCR_CKPDD_CK0
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bic tmp1, tmp1, #DDR3PHY_ACIOCR_CSPDD_CS0
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str tmp1, [r3, #DDR3PHY_ACIOCR]
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/* Power up ODT. */
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ldr tmp1, [r3, #DDR3PHY_DSGCR]
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bic tmp1, tmp1, #DDR3PHY_DSGCR_ODTPDD_ODT0
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str tmp1, [r3, #DDR3PHY_DSGCR]
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/* Take DDR PHY's DLL out of bypass mode. */
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ldr tmp1, [r3, #DDR3PHY_PIR]
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bic tmp1, tmp1, #DDR3PHY_PIR_DLLBYP
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str tmp1, [r3, #DDR3PHY_PIR]
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/* Enable quasi-dynamic programming. */
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mov tmp1, #0
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str tmp1, [r2, #UDDRC_SWCTRL]
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/* De-assert SDRAM initialization. */
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ldr tmp1, [r2, #UDDRC_DFIMISC]
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bic tmp1, tmp1, #UDDRC_DFIMISC_DFI_INIT_COMPLETE_EN
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str tmp1, [r2, #UDDRC_DFIMISC]
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/* Quasi-dynamic programming done. */
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mov tmp1, #UDDRC_SWCTRL_SW_DONE
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str tmp1, [r2, #UDDRC_SWCTRL]
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sr_dis_1:
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ldr tmp1, [r2, #UDDRC_SWSTAT]
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tst tmp1, #UDDRC_SWSTAT_SW_DONE_ACK
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beq sr_dis_1
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/* DLL soft-reset + DLL lock wait + ITM reset */
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mov tmp1, #(DDR3PHY_PIR_INIT | DDR3PHY_PIR_DLLSRST | \
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DDR3PHY_PIR_DLLLOCK | DDR3PHY_PIR_ITMSRST)
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str tmp1, [r3, #DDR3PHY_PIR]
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sr_dis_4:
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/* Wait for it. */
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ldr tmp1, [r3, #DDR3PHY_PGSR]
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tst tmp1, #DDR3PHY_PGSR_IDONE
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beq sr_dis_4
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/* Enable quasi-dynamic programming. */
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mov tmp1, #0
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str tmp1, [r2, #UDDRC_SWCTRL]
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/* Assert PHY init complete enable signal. */
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ldr tmp1, [r2, #UDDRC_DFIMISC]
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orr tmp1, tmp1, #UDDRC_DFIMISC_DFI_INIT_COMPLETE_EN
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str tmp1, [r2, #UDDRC_DFIMISC]
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/* Programming is done. Set sw_done. */
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mov tmp1, #UDDRC_SWCTRL_SW_DONE
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str tmp1, [r2, #UDDRC_SWCTRL]
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sr_dis_5:
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/* Wait for it. */
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ldr tmp1, [r2, #UDDRC_SWSTAT]
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tst tmp1, #UDDRC_SWSTAT_SW_DONE_ACK
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beq sr_dis_5
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/* Trigger self-refresh exit. */
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ldr tmp1, [r2, #UDDRC_PWRCTL]
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bic tmp1, tmp1, #UDDRC_PWRCTRL_SELFREF_SW
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str tmp1, [r2, #UDDRC_PWRCTL]
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sr_dis_6:
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/* Wait for self-refresh exit done. */
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ldr tmp1, [r2, #UDDRC_STAT]
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bic tmp1, tmp1, #~UDDRC_STAT_OPMODE_MSK
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cmp tmp1, #UDDRC_STAT_OPMODE_NORMAL
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bne sr_dis_6
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/* Enable all AXI ports. */
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ldr tmp1, [r2, #UDDRC_PCTRL_0]
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orr tmp1, tmp1, #0x1
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str tmp1, [r2, #UDDRC_PCTRL_0]
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ldr tmp1, [r2, #UDDRC_PCTRL_1]
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orr tmp1, tmp1, #0x1
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str tmp1, [r2, #UDDRC_PCTRL_1]
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ldr tmp1, [r2, #UDDRC_PCTRL_2]
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orr tmp1, tmp1, #0x1
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str tmp1, [r2, #UDDRC_PCTRL_2]
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ldr tmp1, [r2, #UDDRC_PCTRL_3]
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orr tmp1, tmp1, #0x1
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str tmp1, [r2, #UDDRC_PCTRL_3]
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ldr tmp1, [r2, #UDDRC_PCTRL_4]
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orr tmp1, tmp1, #0x1
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str tmp1, [r2, #UDDRC_PCTRL_4]
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dsb
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.endm
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#else
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/**
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* Enable self-refresh
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*
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@ -228,6 +422,7 @@ sdramc_exit_sf:
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sr_dis_exit:
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.endm
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#endif
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.macro at91_pm_ulp0_mode
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ldr pmc, .pmc_base
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@ -668,6 +863,8 @@ ENTRY(at91_pm_suspend_in_sram)
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str tmp1, .sramc_base
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ldr tmp1, [r0, #PM_DATA_RAMC1]
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str tmp1, .sramc1_base
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ldr tmp1, [r0, #PM_DATA_RAMC_PHY]
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str tmp1, .sramc_phy_base
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ldr tmp1, [r0, #PM_DATA_MEMCTRL]
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str tmp1, .memtype
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ldr tmp1, [r0, #PM_DATA_MODE]
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@ -721,6 +918,8 @@ ENDPROC(at91_pm_suspend_in_sram)
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.word 0
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.sramc1_base:
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.word 0
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.sramc_phy_base:
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.word 0
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.shdwc:
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.word 0
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.sfrbu:
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